A class ab ccii topology based on differential pair with modified output

INTERNATIONAL JOURNAL OF Issue 1, January- February (2013), © IAEME–
International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976
6545(Print), ISSN 0976 – 6553(Online) Volume 4,
ELECTRICAL ENGINEERING
& TECHNOLOGY (IJEET)
ISSN 0976 – 6545(Print)
ISSN 0976 – 6553(Online)
Volume 4, Issue 1, January- February (2013), pp. 68-74 IJEET
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A CLASS AB CCII TOPOLOGY BASED ON DIFFERENTIAL PAIR
WITH MODIFIED OUTPUT STAGE

Raj Kumar Tiwari1, Sachin Kumar1 and G R Mishra2
1
Circuit Design and Simulation Lab, Department of Physics and Electronics
Dr. R.M.L. Avadh University Faizabad (U.P), India
2
Department of Electronics, Amity University, Lucknow Campus
rktiwari2323@yahoo.co.in,sachin.amitylko@yahoo.com, gr_mishra@rediffmail.com

ABSTRACT

Current conveyers are unity gain active element exhibiting wide dynamic range, high
linearity and high frequency performance than there voltage counterparts. A simple CMOS
second generation class AB Current conveyer topology based on differential pair with
modified output stage is presented. The circuit has excellent characteristics and is suitable for
low supply voltage operations; the result is verified through SPICE simulation on BISIM3
Level 3 parameters.

Keywords: Current Conveyer, Current Mirrors, Differential Pair, Parasitic Impedance

I. INTRODUCTION

Development of VLSI technology, together with the request of a large number of
elements on a single chip, has led to an improved interest in analog circuit design, especially
for integrated circuits [1-4]. Recent trend towards miniaturized circuits has given a strong and
decisive boost towards the design of low voltage low power analog integrated circuits, which
are widely utilized in portable system applications. The more gates integrated, the more
important it is to reduce the power consumption. Therefore a low supply voltage is required
to decrease the power consumption of the digital portion of the chip enabling more functions
to be integrated.
Various Current conveyer topologies for low supply voltages have been proposed.
These topologies require complicated input stages to guarantee a rail to rail input common
mode operation while maintaining a constant transconductance, this is important to allow

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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –
6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 1, January- February (2013), © IAEME

optimal frequency compensation. The use of compensating capacitors results in a finite gain
bandwidth product for the operational amplifiers; hence the bandwidth is not utilized
effectively for higher gain values. Recently, current mode circuits have been receiving
significant attention in analog signal processing. This has led to implement new circuit design
strategies for low cost CMOS technology [2-8]. The Current mode circuits are able to
overcome the limitation of a constant gain-bandwidth product and the trade off between
speed and bandwidth, so that performance is improved in terms of slew rate and bandwidth.
The current conveyer introduced by Sedra and Smith in 1968, is a basic current mode circuit
that can be implemented in analog circuit design which had characteristics similar to
operational amplifier. The first block was identified as “first generation current conveyers” or
CCI, later its evolved topology was called “second generation current conveyers” or CCII in
1970 [2, 5-8, 12-15]. Although CMOS realizations of the CCII are available, they usually
operate in a class A mode with a limited voltage swing capability [1-6].
In this paper we propose a high performance improved class AB CCII topology based
on differential pair with modified output stage. The proposed circuit has been simulated using
BISIM3 Level 3 parameters.

II. CURRENT CONVEYER

CCIIs are useful and flexible current-mode building blocks and many authors have
demonstrated their versatility in CMOS analog circuit design. An ideal CCII is a three-
terminal device with two input nodes (X; Y) and an output node (Z). Fig 1a shows block
representation of CCII. The resistance at the Y node is ideally infinite, while that at node X is
low. The voltage in X is a replica of that applied at Y and the current at Z is equal to that
flowing at X. The well-known CCII behavior is summarized in the matrix form shown in Fig
1b, where the signs + and - are used for positive (CCII+) and negative (CCII-) conveyors,
respectively.

Y Iz
Iz Z
Ix
X

Vy Vx

Fig 1a : CCII block Representation

 IY   0 0 0  VY 
V  = 1 0 0   I 
 X   X 
 I Z   0 ± 1 0  VZ 
    

Fig 1b : CCII summarized in matrix form

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X and Y are input terminals and Z is the output terminal. The output current Iz thus depends only on
the input current at terminal X, this current may be injected directly at X, or it may be produced by the
copy of the input voltage Vy from terminal Y acting across the impedance connected at X. In a class
CCII conveyor input Y draws no current, whereas for the older CCI formulation the impedance
connected at X is also reflected at Y. In contrast, a current convertor is represented completely by the
relationship Iz = ±Ix; Vy is effectively shorted out by being grounded. Many different and useful
circuit functions can be realized by different interconnections of one or more current conveyors;
hence the interest in an effective circuit implementation [1-3, 5-8]. Earlier implementation of current
conveyors, however, has suffered from an excessive number of operational amplifiers, tightly
matched resistances and very low bandwidths. More recently, operational transconductance amplifiers
(OTAs) have been employed, or an equivalent operational amplifier synthesis, but again with poor
bandwidth and output capability. Since a current conveyor is intended as a controlled current output
so, it must be capable of driving a short-circuit or very low load resistances, in contrast to voltage
amplifier behavior, and it also provides wide bandwidth and low-power characteristics.
III. PROPOSED CURRENT CONVEYER
The use of differential pair in the implementation of Current Conveyer II can be extended also
to the basic topologies, Fig 2a shows a class AB CCII, here IBias1 and IBias2 have to be equal, in this
circuit, current mirrors have been doubled, this circuit can be employed as a first stage, a differential
pair to give class AB CCII topology based on differential pair with modified output stage shown in
fig 2b.

Fig 2a .Class AB CCII based on current mirrors

Fig 2b. The proposed class AB CCII topology based on differential pair with modified output
stage

70


The circuit consists of first stage of differential pair formed by current mirrors, only Y
terminal is affected by this modification, while nothing changes for X and Z nodes [2, 3, 5, 7-
9].
Using this topology a better response for voltage transfer function (α) between nodes X-Y
can be obtained by simple analysis, given by:

r08r09 ( g m8 + g m9 ) r0
g m1r05 gm5
Vx r08 + r09 2
α= =
VY 1 + r08 r09 ( gm8 + gm9 ) + r08r09 − ( g + g ) r0 g r g
m8 m9 m 2 05 m 5
r08 + r09 r08 + r09 2

gm2
=
g m1

Further a simple analysis for current ratio between Z and X nodes, given by β comes as

I Z g m 9 g m10 g m13 + g m 8 g m11 g m12
β= ≅ =1
IX g m10 g m11 ( g m 8 + g m 9 )
if
g m10 = g m12 and g m11 = g m13
The differential pair allows to have a high Y node impedance, independent from the biasing
current resistances. This obviously improves Zy as compared from the previous configuration
shown in Fig 2a.

Z y = γ W LC ox
Due to feedback effect introduced with differential pair, the parasitic impedance at node X
improves. The resistive contribution at X is given as:
1
RX =
r08 + r09 ro
+ (1 + g m1 r05 g m 5 )( g m8 + g m 9 )
r08 r09 2
2
≅
g m1ro r05 ( g m8 + g m 9 )
This configuration however has a fallback that parasitic impedance now shows an inductive
component given by:
2
Po
LX =
g m 2 ro r05 g m5 ( g m8 + g m9 )
The Z node output impedance remains very high, being given by the transistors output
resistances [8-12, 14-20]
r r
Z Z = 012 013
r012 + r013

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IV. SIMULATION RESULTS
The proposed class AB CCII topology based on differential pair with modified output
stage is shown in fig 2b, the result is simulated on BISIM3 Level 3 parameters. The circuit
consists of first stage of differential pair formed by current mirrors, with this topology a
better response for voltage transfer function (α) between nodes X-Y is obtained. The
differential pair allows to have a high Y node impedance, independent from the biasing
current resistances. This obviously improves Zy. Due to feedback effect introduced with
differential pair, the parasitic impedance at node X improves.

Fig 3a: Transient Analysis of class AB Current conveyer topology based on differential pair
with modified output stage

Fig 3b: AC Analysis of class AB Current conveyer topology based on differential pair with
modified output stage

Figure 3a shows transient response curve of the proposed class AB CCII topology based on
differential pair which confirms that the input and output transitions are similar to each other.
The AC analysis of the circuit is shown in Fig. 3b. The analysis of result shows that the
circuit has excellent characteristics up to 20 MHz, after this performances degrades.

72


V. CONCLUSIONS

The Paper presents a high performance improved class AB CCII topology based on
differential pair with modified output stage. The proposed circuit has excellent transient
response and AC analysis curves and can work satisfactorily up to 20 MHz. The proposed
circuit has better response for voltage transfer function (α) between nodes X-Y, high Y node
impedance and the parasitic impedance at node X improves. The circuit can be used in design
of various analog and mixed mode circuit designs

ACKNOWLEDGEMENT

The authors are thankful to Maj. General K. K. Ohri, AVSM (Retd.) Pro Vice
Chancellor, AUUP, Lucknow Campus, Prof. S. T. H. Abidi (Director, ASET), Brig. Umesh
K. Chopra (Director, AIIT, & Dy. Director, ASET) and Prof O P Singh (Head of Department)
for their cooperation, motivation and suggestive guidance.

REFERENCE

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[21] Raj Kumar Tiwari, Sachin Kumar and G R Mishra, “A Study On Techniques of
Improvement In Current Mirrors Using Wilson Scheme” International journal of
Electronics and Communication Engineering &Technology (IJECET), Volume 3, Issue 2,
2012, pp. 56 - 62, Published by IAEME.
[22] Rajinder Tiwari and R K Singh, “An Optimized High Speed Dual Mode Cmos
Differential Amplifier For Analog VLSI applications” International Journal of Electrical
Engineering & Technology (IJEET), Volume 3, Issue 1, 2012, pp. 180 - 187, Published
by IAEME.
[23] Rajinder Tiwari, R. K. Singh and Ganga Ram Mishra “A New Approach For Design of
CMOS Based Cascode Current Mirror For ASP Applications” International journal of
Electronics and Communication Engineering &Technology (IJECET), Volume 2, Issue 2,
2011, pp. 1 - 7, Published by IAEME.
[24] Rajinder Tiwari and R K Singh, “An Innovative Approach of High Performance CMOS
Current Conveyor - II For Analog Signal Processing Applications” International journal
of Computer Engineering & Technology (IJCET), Volume 3, Issue 1, 2012, pp. 147 - 153,
Published by IAEME

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