A fast acquisition all-digital delay-locked loop using a starting-bit prediction algorithm for the successive-approximation register
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This document introduces a fast-acquisition 11-bit all-digital delay-locked loop (ADDLL) that utilizes a starting-bit prediction algorithm for effective functioning. It eliminates harmonic and false locks, achieving acquisition times of 17.5–23.5 or 17.5–32.5 clock cycles at low and high clock rates, respectively. The ADDLL operates at clock frequencies ranging from 60 MHz to 1.1 GHz and is synthesized using TSMC's 0.18-μm CMOS cell library.
A fast acquisition all-digital delay-locked loop using a starting-bit prediction algorithm for the successive-approximation register
- 1. A FAST-ACQUISITION ALL-DIGITAL DELAY-LOCKED LOOP USING A STARTING-BIT PREDICTION ALGORITHM FOR THE SUCCESSIVE-APPROXIMATION REGISTER ABSTRACT: This brief presents a fast-acquisition 11-bit all-digital delay-locked loop (ADDLL) using a novel starting-bit prediction algorithm for the successive-approximation register (SBP- SAR). It can effectively eliminate the harmonic lock and the false lock. The achievable acquisition time is within 17.5–23.5 or 17.5–32.5 clock cycles when the ADDLL works at the low or high clock rate, respectively. The digital-controlled delay line and the SBP-SAR of the ADDLL chip are synthesized using Taiwan Semiconductor Manufacturing Company’s (TSMC’s) 0.18-μm CMOS cell library. The proposed ADDLL can operate at a clock frequency from 60 MHz to 1.1 GHz.