A review on virtex fpga family from xilinx

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A Review on Virtex FPGA Family from XILINX
Tanmay Bhargava
Dept. of Electronics and Communications
University of Kassel
tanmay5030.05@bitmesra.ac.in
Abstract - Confabulation and segregation about different Virtex FPGA families of XILINX is presented. Starting with the features of latest Spartan-6 FPGA followed by Spartan-3A-DSP, 3AN, 3A, 3E and Spartan-3 are correlated, contrasted accordingly and the changes over these generations are also deliberated. For every family, Introduction and ordering information, Functional description, DC and switching characteristics and Pin out descriptions are mentioned and elucidated. Keywords - Field Programmable Logic Array (FPGA), Look Up Tables (LUT’s).
I. INTRODUCTION
The Field Programmable Gate Arrays (FPGAs) are field programmable integrated circuits that can be tailored according to the end user's requirements. FPGA is similar to a PLD, but whereas PLDs are generally limited to hundreds of gates, FPGAs support thousands of gates. Instead of being restricted to any predetermined hardware function, an FPGA allow to use a product program feature and functions, adapt new standards, reconfigure hardware for specific applications even after product have been installed in the field hence the name - “Field Programmable”. We can use an FPGA to implement any logical function that an Application Specific Integrated Circuit (ASIC) would perform, but ability to update the functionality after shipping offers advantage for many applications. [1] Ross Freeman, the cofounder of Xilinx, invented the first FPGA in 1985. XILNX is a supplier of programmable logic devices. It is known for inventing the field programmable gate array (FPGA) and as the first semiconductor company with a fabless manufacturing model. These FPGAs deliver the performance, cost, power consumption and capacity that at one time could only be met by costly custom chips designed for specific applications. In essence, they offer the design engineer a blank device that can be configured and reconfigured "on the fly" to implement any logic function that can be performed by an application-specific device. They make hundreds of thousands of programmable logic blocks - comprised of billions of transistors - available to the designer to wire together using reconfigurable interconnects to deliver the desired electronic functions. For Xilinx, the programmable imperative represents a two-fold commitment. First, to increase performance, densities and system-level functionality, while driving down cost and power consumption, at each manufacturing process node with every new generation of FPGAs. Secondly, to provide simpler, smarter programmable platforms and design methodologies that free up engineers to focus on end product innovation and differentiation. Xilinx has offered two main FPGA families: the high performance Vertex series and the high volume Spartan series. Virtex-6 and Spartan-6 FPGA families are said to consume 50 percent less power, and have up to twice the logic capacity compared to the previous generation of Xilinx FPGAs. The Virtex series of FPGAs have integrated features that include FIFO and ECC logic, DSP blocks, PCI-Express controllers, Ethernet MAC blocks, and high-speed transceivers. In addition to FPGA logic, the Virtex series includes embedded fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and microprocessor cores. These capabilities are used in applications such as wired and wireless infrastructure equipment, advanced medical equipment, test and measurement, and defense systems. QPro Virtex 2.5V and 1.5V are available in radiation- hardened packages, specifically to operate in space where harmful streams of high-energy particles can play havoc with semiconductors. The Virtex-5QV FPGA is designed to be 100 times more resistant to radiation than previous radiation-resistant models and offers a ten-fold increase in performance. Legacy Virtex devices (Virtex, Virtex-II, Virtex-II Pro, Virtex 4) are still available, but are not recommended for use in new designs. The Virtex-5 LX and the LXT are intended for logic- intensive applications, and the Virtex-5 SXT is for DSP applications. With the Virtex-5, Xilinx changed the logic fabric from four-input LUTs to six-input LUTs. With the increasing complexity of combinational logic functions performed by SoC, the percentage of combinational paths requiring multiple four-input LUTs became a performance and routing bottleneck. The new

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six-input LUT represented a tradeoff between better handling of increasingly complex combinational functions, at the expense of a reduction in the absolute number of LUTs per device. The Virtex-5 series is a 65 nm design fabricated in 1.0 V, triple-oxide process technology. The Virtex-6 family is built on a 40 nm process for compute-intensive electronic systems, and the company claims it consumes 15 percent less power and has 15 percent improved performance over competing 40 nm FPGAs. Xilinx's most recently announced Virtex, the Virtex 7 family, is based on a 28 nm design and is reported to deliver a two-fold system performance improvement at 50 percent lower power compared to previous generation Virtex-6 devices. In addition, Virtex-7 doubles the memory bandwidth compared to previous generation Virtex FPGAs with 1866 Mb/s memory interfacing performance and over two million logic cells. The Virtex-7 2000T FPGA packages four smaller FPGAs into a single chip by placing them on a special silicon communications pad called an interposer which can deliver 6.8 billion transistors in a single large chip. The interposer provides 10,000 data pathways between the individual FPGAs – roughly 10 to 100 times more than usually would be available on a board – to create a single FPGA. This approach allows the FPGA to conserve power, drawing 20 watts of power or less. This approach allows the Virtex-7 2000T FPGA to exceed Moore’s Law – Intel co-founder Gordon Moore’s prediction that the number of those transistors will double roughly every two years – by providing twice the number of transistors in a single FPGA than would be expected under the prediction [2], [3], [4], [5], [6], [7], [8], [11].
II. VIRTEX FPGA FAMILY
The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, VDS, and DDR interfaces. The leading-edge 0.15 μm / 0.12 μm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to10 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask- programmed gates arrays. The Virtex-II family comprises 11 members, ranging from 40K to 8M system gates [2].
The Virtex-II Pro and Virtex-II Pro X families contain platform FPGAs for designs that are based on IP cores and customized modules. The family incorporates multi- gigabit transceivers and PowerPC CPU blocks in Virtex- II Pro Series FPGA architecture. It empowers complete solutions for telecommunication, wireless, networking, video, and DSP applications. The leading-edge 0.13 μm CMOS nine-layer copper process and Virtex-II Pro architecture are optimized for high performance designs in a wide range of densities. Combining a wide variety of flexible features and IP cores, the Virtex-II Pro family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gate arrays [3].
The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 μm CMOS process. These advances make Virtex-E FPGAs powerful and flexible alter- natives to mask- programmed gate arrays. The Virtex-E family includes the nine members in Table 1. Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to- market [4].
Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex-4 family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise three platform families—LX, FX, and SX—offering multiple feature choices and combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high- speed clock management circuitry, and source- synchronous interface blocks. The basic Virtex-4 FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology [5].

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The Virtex-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally- controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power- optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high- performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability [6].
The Virtex-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. Using the third-generation ASMBL™ (Advanced Silicon Modular Block) column - based architecture; the Virtex-6 family contains multiple distinct sub-families. This overview covers the devices in the LXT, SXT, and HXT sub- families. Each sub-family contains a different ratio of features to most efficiently address the needs of a wide variety of advanced logic designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many built-in system-level blocks. These features allow logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 40 nm state-of-the- art copper process technology, Virtex-6 FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high- performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities [7].
Xilinx 7 series FPGAs comprise three new FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, and high-volume applications to ultra- high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series devices are the programmable silicon foundation for Targeted Design Platforms that enable designers to focus on innovation from the outset of their development cycle. The 7 series FPGAs include:
 Artix™-7 Family: Optimized for lowest cost and power with small form-factor packaging for the highest volume applications.
 Kintex™-7 Family: Optimized for best price- performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.
 Virtex-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) technology.
Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. All 7 series devices share a scalable, optimized fourth- generation Advanced Silicon Modular Block (ASMBL™) column-based architecture that reduces system development and deployment time with simplified design portability [8].
III. SUMMARY
In case of independent blocks of logic that are not paired with soft combinational logic elements, distinct tiles containing dedicated hard circuit structures are added to the array of tiles. For example, multi-bit block RAMs that appear in modern FPGAs are common hard

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circuit structures. These RAMs range in size from
hundreds to tens or hundreds of thousands of bits and
are commonly found in contemporary devices such as
the Virtex, Virtex II, Virtex II Pro, Virtex 4 and 5. Block
RAMs typically are aligned in vertical columns within
the basic tile array, as shown in Figure1. Other common
hard circuit structures found in contemporary
commercial FPGAs include the multiplier blocks that
appear in Xilinx Virtex II, Virtex 4, and Virtex 5
FPGAs. Heterogeneity which includes hard circuit
structures can be referred to as tile-based heterogeneity
to reflect the inclusion of diverse tiles on the same
FPGA substrate. Figure1 illustrates an FPGA with a
mixture of different blocks with tile-based
heterogeneity. The Xilinx XC4000 series FPGAs, and
all subsequent Xilinx FPGAs provide the ability to turn
LUTs in the soft fabric into small memories. These
memories can be connected together to form larger
memories. This ability to convert LUTs to memory has
been added in all Xilinx FPGAs since the original
Virtex, the LUT can also be configured to act as a shift
register. An early example of a computation-oriented tile
is the multiplier integrated into the Xilinx Virtex II
FPGA. This tile consisted of an 18 × 18 2’s complement
multiplier that sat alongside a block memory tile. Since
the introduction of the Virtex II, Xilinx have introduced
more sophisticated hard computational units that include
multiplier-accumulators, and some multiplexer
functions. The ratio-based approach to resource
allocation was first introduced commercially by Xilinx
for the Virtex 4 family. This family has three sub-families,
one with a focus on soft logic and memory, one
with a focus on arithmetic computational units, and one
with a processor and high-speed serial interface focus.
Ratio-based subfamilies are also available for the Xilinx
Virtex 5 family. Microprocessors are vital components
in many digital systems. Xilinx introduced Virtex II Pro
FPGAs which included one, two, or four IBM Power PC
cores integrated with a Virtex II logic fabric. Several
Xilinx Virtex 4 and Virtex 5 subfamilies also support
Power PC cores. Virtex 4 family, used basic clusters of
4-input lookup tables to implement logic. The Virtex 5
FPGA, employs a 6-input lookup table that can also
implement two 5-input functions that share five inputs,
or two 4-input functions that share fewer inputs. A 22%
improvement in critical path delay and a 6% area
reduction is seen for a set of 10 benchmark designs. A
form of this approach has been included in the Xilinx
Virtex 5 FPGA family, which includes wires that
connect diagonally [2], [3], [4], [5], [6], [7], [8], [9].
[10], [11].
IV. FUTURE TRENDS
FPGAs play an important role in today's network,
computer, data center, and communication ecosystems.
The latest optical interface on FPGA overcomes the
limits of copper interconnect by integrating the latest
FPGA with a state-of-the-art laser and photon detector at
the FPGA package level. The optical FPGA interface
provides power, cost and density advantages that
dramatically exceeds conventional electrical signaling
and interconnect capabilities. These FPGAs will offer
enhanced critical reconfiguration and system on chip
(SoC) capabilities for data processing and transport, and
faster computation, DSP, packet processing, frame
processing, routing, switching, and bridging capabilities.
The Advanced Transceiver Technology has assured to
provide electrical transmit and receive functionality with
data rates up to 28 Gbps on the 28-nm process node.
These transceivers also support advanced clock
generation, clock recovery, and equalization capabilities.
This advanced transceiver technology integrates the
FPGA with an optical laser and the receiver becomes
seamless.
Figure1. Illustration of tile based heterogeneity. [9]
The FPGA in Figure2 is integrated with optics, such as a
Transmitter Optical Sub-Assembly (TOSA) and
Receiver Optical Sub-Assembly (ROSA), providing
direct optical signal transmitting and receiving without
the need for a discrete optical module.

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Figure2. FPGA with Optical Interface [10]
The FPGA in Figure 2 is integrated with optics, such as a transmitter optical sub-assembly (TOSA) and receiver optical sub-assembly (ROSA), providing direct optical signal transmitting and receiving without the need for a discrete optical module. Designers can replace chip-to- module link systems with an optical interface FPGA to capture significant power, resource, and cost reductions, as well as an increase in port density. It is easy to imagine that FPGAs with optical interface technology will be widely used in future data communications and telecom systems, data center, data transporting, and military network systems, as well as test and measurement, medical and broadcasting systems due to power, cost, density, and form-factor, weight, and EMI and crosstalk resilience benefits. This technology forever changes how future internet, network, data center, test and measurement, medical, and broadcast ecosystems will be designed and built [3], [4].
V. ACKNOWLEDGMENT
I would like to appreciate Prof. Zipf for his invaluable feedback and comments that helped me to improve my work.
VI. REFERENCES
[1] FPGAs at http://www.altera.com/products/fpga.html
[2] http://www.xilinx.com/support/documentation/ data_sheets/ds031.pdf
[8] http://www.xilinx.com/support/documentation/ data_sheets/ds180_7Series_Overview.pdf
[9] FPGA Architecture: Survey and Challenges - www.eecg.toronto.edu/~jayar/pubs/kuon/foundtrend08.pdf
[10] Overcome Copper Limits with Optical Interfaces - Altera www.altera.com/literature/wp/wp-01161- optical-fpga.pdf
[11] http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/products/virtex/techtopic/lvds.htm

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