A Security Analysis of Circuit Clock Obfuscation
- 1. A Security Analysis of Circuit Clock Obfuscation Cryptography 2022, 6(3) Authors: Rajesh Datta , Guangwei Zhao, Kanad Basu and Kaveh Shamsi
- 2. Outline Introduction Preliminaries Clock based obfuscation Clock based deobfuscation Experiments Conclusion
- 3. Introduction Key-based circuit obfuscation or logic-locking is a technique that can be used to hide the full design of an integrated circuit from an untrusted foundry or end-user. The technique is based on creating ambiguity in the original circuit by inserting “key” input bits into the circuit such that the circuit is unintelligible absent a correct secret key. Clock signals have traditionally been avoided in locking in order to not corrupt the timing behavior of the locked circuit. In this work, we explored the case where the clock signal itself may be obfuscated by ambiguating its frequency or pattern. We present the ways to do the clock obfuscation and deobfuscate the circuit. We compared the security of the clock obfuscation with the traditional logic locking.
- 4. Circuit Locking Transforming an original circuit c_o ( i ) : I → O where I and O are the input and output space respectively, to a locked/obfuscated circuit c_e ( i, k ) : I × K → O with l added key inputs and key space K.
- 5. Oracle-Guided (OG) Attack In an oracle-guided (OG) attack (or attack model), the attacker, in addition to access to the structure of the obfuscated circuit c_e , has access to a black-box that implements the original circuit c_o , which is called the oracle. The attacker can query this oracle adaptively on chosen points to help identify a correct key for c_e .
- 6. Sequential Oracle-Guided (SOG) Attacks In the case of a sequential obfuscated circuit, if the attacker has an original functional circuit (oracle), but he for any reason cannot control or observe all the internal state elements (flip-flops or latches) of the oracle this we refer to as the sequential oracle- guided attack model. The attacker only controls primary inputs and observes primary outputs and has a way to reset the oracle to its known reset state. An unknown reset state of s bits here can be modeled by s extra (virtual) key inputs, an extra flip-flop, and some multiplexer logic.
- 7. Clock Domain If a circuit has state elements such as latches or flip-flops then it may have one or more clock signals (see Figures 1 and 2). The input and output of the circuit are related to the incoming sequence of the clock signal. The elements of the circuit, which are dependent on a particular clock signal, are in the domain of that clock. Hence a circuit with multiple clock signals will typically have multiple clock domains.
- 8. SAT Attack 1. Combinational Sat Attack 2. Sequential SAT attack 1. Combinational Sat Attack 2. Sequential SAT attack : The sequential attack can proceed by unrolling the obfuscated sequential circuit c_e up to a given clock cycle bound ‘u’. From this we get ‘ce_u’ which takes ‘u’ inputs and produces ‘u’ outputs. Since such an unrolled circuit is going to be combinational, it can be directly passed to a combinational SAT attack.
- 9. Clock Obfuscation External Clock Sources Internal Key-Programmable Clock Sources. Frequency Fractions: Integer Multiples of a Single Base Period Integer Multiples of Multiple Base Periods Rational Multiples of a Single Base Period
- 11. Dummy (Constant-Clock) State Elements
- 12. Example
- 13. Clock Deobfuscation Sequential circuits are considered to be harder than the combinational circuit in the deobfuscation process. As mentioned in preliminaries, the deobfuscation of sequential circuits is possible with the sequential oracle-guided attack with bounded model checking. Here we show that it is possible to adapt these attacks to the case of deobfuscating clock-ambiguous circuits.We use a common technique used in multi-rate model-checking . The idea here is to try to model the multi-rate semantics with a single-rate model with the same functionality that can then simply be passed to a traditional single-rate model-checking attack.
- 14. Clock Deobfuscation case with Known Integer Multiples of a Base Period
- 15. Unknown multiples of the base period. For a DFF that may be running at an unknown multiple period , we go ahead and slowdown the next-state signal of the DFF by inserting a_max number of slow-down DFFs. Using key-controlled MUX gates we allow the circuit to pick any of the slowed down signals . If we now set a_max to an integer value that is higher than the maximum expected period multiplier in the attacker’s hypothesis, we will effectively end up modeling clocks that can be arbitrarily slower than the base clock within some reasonable range. The attacker can bound the value of a_max by studying the clock source. For instance, if the clock is driven by an n-bit digital clock-divider that can divide the base frequency by up to 2n , then a_max will have to be greater than 2n . If an on-chip LC oscillator is used, the attacker may be able to use the LC variables limit in the given technology or the digital bits used to program them to get an idea of how slow of a signal they can produce.
- 17. Non-Integer Multiples of a Base Period The clock period choices can be non-integer multiples of a base period, e.g., 1.2T, 2.4T, . . .. be. We do not directly attack this case. Instead, such cases have to be converted to an integer multiple period equivalent model. This can be done by trying to find the smallest period T_b , which can be used to describe all the non-integer periods in the circuit. First, we consider the case where the non-integer periods are known. i.e., 1.2T, 2.4T. We can first multiply both numbers by a decimal factor to turn them into integers 12T = 10 × 1.2T, 24T = 10 × 2.4T. We can then take the greatest-common-divisor of 12T and 24T which will be 12T here. We then reverse our early transform by dividing 12T by 10 obtaining 1.2T. We now take T_b = 1.2T, which allows us to express the other periods 1.2T = T b , and 2.4T = 2T b . This returns us to the known integer multiple case and allows for applying the previous deobfuscation routines. If the non-integer multiples are unknown, similar to the case of integer multiples we pick an a_max that represents the maximum multiple of the base period that could occur in the circuit and allow for a choice between all slowed down versions of using virtual key bits and MUX gates. As for identifying a _max one can follow the same procedure as before. If the clock is generated by a digital clock divider, the maximum a_max is visible. If the clock is sourced via a fine-grained oscillator, the smallest step in the oscillator frequency range can still be taken as T_b and the attack can proceed.
- 18. Finding the Base Period For a clock-ambiguous circuit the attacker, not knowing the base period of the clock, will not know precisely how to attribute the different outputs observed on the oracle to the unrolling of the different frames in the model-checking attack. If the locked circuit has an external master clock and there are no frequency boosters in the circuit, the attacker can assume that the fastest clock in the circuit is the external clock. If however, the fastest clock in the circuit is generated internally, the attacker may not directly observe this fast clock’s period T. Instead, the only manifestation of T will be that at rates of ‘aT’ where ‘a’ may be unknown, the output of the circuit may change. The attacker can hence try to measure the time it takes for an output to exhibit change while the inputs are kept the same to identify aT.
- 19. Experiments
- 22. Conclusion In this paper, we presented a security analysis of clock-based obfuscation in sequential circuits. We discussed some ways that clock ambiguity can be introduced into circuits and how this relates to formal notions of functional secrecy. To the best of our knowledge, this is the first time clock obfuscation and deobfuscation have been studied in hardware security research. We presented experimental data on our (de)obfuscation approach on ISCAS benchmarks. We observed that the security level is not wildly different than traditional XOR/XNOR insertion.
- 23. References Datta, R.; Zhao, G.; Basu, K.; Shamsi, K. A Security Analysis of Circuit Clock Obfuscation. Cryptography 2022, 6, 43. https://doi.org/10.3390/cryptography6030043