![Processor Block Diagram
NVIC
Cortex M3 or
Cortex-M4(F)
Core
I D
INTISR[n*-1:0]
MPU
ETMSLEEPING
SLEEPDEEP
INTNMI
Interrupts
Sleep
Debug
Integration Level
Cortex-M3/M4 Processor
Trigger
n*- configurable
18
AAME TechCon 2013
TC006v02
18
Bus
matrix
Serial Wire
or JTAG
DWT ITM
APB i/f
FPB
AHB-APSWJ-DP
TPIU
ROM
table
I-Code
D-Code
System
External
Private
Peripheral Bus
Trace Bus
Single Wire or
Multi-pin
Internal Private Peripheral Bus
n*- configurable
number of interrupt
lines](https://image.slidesharecdn.com/aametc2013006v02-implementationdiversity-141125195614-conversion-gate01/85/AAME-ARM-Techcon2013-006v02-Implementation-Diversity-18-320.jpg)
AAME ARM Techcon2013 006v02 Implementation Diversity
- 1. Cortex-M Series Processor Implementation Diversity
- 2. Agenda ARM Cortex®-M0 processor ARM Cortex-M0+ processor 2 AAME TechCon 2013 TC006v02 2 ARM Cortex-M3 processor ARM Cortex-M4 processor
- 3. ARM Cortex-M0 Processor ARMv6-M architecture Von-Neumann architecture 32-bit architecture Thumb® technology Nested Vector Interrupt Debug WICInterface NVIC Processor Core Debug Breakpoint and Watchpoint Unit 3 AAME TechCon 2013 TC006v02 3 Nested Vector Interrupt Controller (NVIC) AMBA® AHB-Lite Master Interface Optional CoreSight™-compliant debug Ultra-low power support RTL is configurable Synthesizable Gate count 12 ~ 25K WICInterface Clocks/Resets Debugger Interface Configuration/ Status AHB-Lite Master Interface Bus Matrix
- 4. Processor Configuration Options The following configuration options are set during the chip implementation design flow Parameter Value ACG 0 or 1 BE 0 or 1 NUMIRQ 1 - 32 SYST 0 or 1 4 AAME TechCon 2013 TC006v02 4 SYST 0 or 1 SMUL 0 or 1 WIC 0 or 1 WICLINES 2-34 DBG 0 or 1 BKPT 0, 1, 2, 3 or 4 WPT 0, 1 or 2 AHBSLV 0 or 1 RAR 0 or 1
- 5. Hardware Multiplier There are two different 32x32 hardware multiplier versions – Implementation option Fast Multiplier – Optimized for speed 5 AAME TechCon 2013 TC006v02 5 – Optimized for speed – Takes 1 cycle to calculate result Small Multiplier – Optimized for area – Takes 32 cycles to calculate result
- 6. RTL Configuration Options Processor Core Number of IRQs (1 - 32) Data endianness Hardware multiplier (1 cycle / 32 cycle) SysTick timer 6 AAME TechCon 2013 TC006v02 6 Debug Options Number of watchpoints and breakpoints Debug slave interface protocol Power Management Options Architectural clock gates WIC interface
- 7. Debug Extensions Optional CoreSight-compliant debug Support for halting debug Single stepping support Debugger has access to all memory and registers Profiling support to help to optimize code Breakpoints for instruction comparison 7 AAME TechCon 2013 TC006v02 7 Breakpoints for instruction comparison Maximum of 4 instruction comparators are supported Data Watchpoints for data comparison Up to 2 hardware comparators are supported
- 8. Agenda ARM Cortex®-M0 processor ARM Cortex-M0+ processor 8 AAME TechCon 2013 TC006v02 8 ARM Cortex-M3 processor ARM Cortex-M4 processor
- 9. Cortex-M0+ Processor Synthesizable ARMv6-M architecture Thumb technology 2-stage core pipeline Optional user/privileged support Optional MPU Nested Vector Interrupt Controller (NVIC) NVIC Processor Core Debug Debugger Interface Breakpoint and Watchpoint Unit Debug Interrupts& WICInterface Execution Trace Interface 9 AAME TechCon 2013 TC006v02 9 (NVIC) AMBA AHB-Lite master interface Optional single cycle IO Port Optional halfword instruction fetch Optional CoreSight-compliant debug Ultra-low Power support Configurable RTL AHB-Lite Master Interface Bus Matrix MPU Configuration/S tatus Clock/Reset Low Latency IO Port
- 10. Cortex-M0+ vs Cortex-M0 Processors Feature Cortex-M0+ Cortex-M0 Architecture ARMv6-M ARMv6-M Pipeline 2-stage 3-stage Dynamic Power (180nm)* 53uW/MHz 78uW/MHz Area (gate count)* 11.5K 11.5K Bus Interface AHB-Lite I/O Port AHB-Lite 10 AAME TechCon 2013 TC006v02 10* 180nm uLL process using Artisan SC7 libraries, typical, 1.8v, 25C Data access (cycles) 2 1 2 MPU Option Yes No Relocatable vector table Yes No Multidrop debug support Yes No Trace support Micro Trace Buffer No Instruction fetch activity (Relative for Dhrystone) 0.85 1 Performance (DMIPS/MHz) 0.95 0.90
- 11. RTL Configuration Options The following options can be configured at implementation time Processor Core Number of IRQs, data endianness, type of hardware multiplier, relocatable vector table MPU User/privileged support SysTick timer 11 AAME TechCon 2013 TC006v02 11 SysTick timer IO Port Halfword-only Instruction fetch Debug options Number of watchpoints and breakpoints Debug slave interface protocol Power Management Options Architectural clock gates WIC interface
- 12. System Timer Extension Optional support for a system timer – SysTick 24-bit timer Timer can be used in multiple ways 12 AAME TechCon 2013 TC006v02 12 Timer can be used in multiple ways – OS tick timer – SysTick interrupt – Simple counter for the application
- 13. Debug Extensions Optional CoreSight-compliant debug Support for invasive debug Single stepping support Debugger has access to all memory and registers Breakpoints 13 AAME TechCon 2013 TC006v02 13 Breakpoints Up to 4 instruction address comparators Data Watchpoints Up to 2 data or instruction address comparators Non-invasive PC sampling Profiling support to help to optimize code
- 14. Trace - MTB (Micro Trace Buffer) The MTB provides a very simple execution trace capability No support for load/store data trace or any other trace information MTB records changes in program flow and stores into a configurable region of the SRAM Debugger can extract the trace information via the AHB-Lite interface, to 14 AAME TechCon 2013 TC006v02 14 Debugger can extract the trace information via the AHB-Lite interface, to reconstruct an instruction flow trace The MTB can also operate as a simple AHB-Lite SRAM controller The MTB is optional and licensed separately
- 15. RTL Configuration Options The processor needs to be configured at implementation time Processor Core Number of IRQs, Data Endianness, Type of Hardware Multiplier, Relocatable Vector Table MPU User/Privileged support SysTick timer 15 AAME TechCon 2013 TC006v02 15 SysTick timer IO Port Halfword-only Instruction fetch Debug Options Number of Watchpoints and Breakpoints Debug Slave interface protocol Power Management Options Architectural Clock Gates WIC interface
- 16. Integration Example Full working integration example provided Integration example contains: Cortex-M0+ Processor Cortex-M0+ Debug Access Port (DAP) Wake-up Interrupt Controller (WIC) 16 AAME TechCon 2013 TC006v02 16 Example MCU provided Reset & power controller Used as a starting point for development Cortex-M0+ core and DAP cannot be modified
- 17. Agenda ARM Cortex®-M0 processor ARM Cortex-M0+ processor 17 AAME TechCon 2013 TC006v02 17 ARM Cortex-M3 processor ARM Cortex-M4 processor
- 18. Processor Block Diagram NVIC Cortex M3 or Cortex-M4(F) Core I D INTISR[n*-1:0] MPU ETMSLEEPING SLEEPDEEP INTNMI Interrupts Sleep Debug Integration Level Cortex-M3/M4 Processor Trigger n*- configurable 18 AAME TechCon 2013 TC006v02 18 Bus matrix Serial Wire or JTAG DWT ITM APB i/f FPB AHB-APSWJ-DP TPIU ROM table I-Code D-Code System External Private Peripheral Bus Trace Bus Single Wire or Multi-pin Internal Private Peripheral Bus n*- configurable number of interrupt lines
- 19. Configuration Options - I There are a number of configuration options available to the user Number of interrupts – The Cortex-M3 can be configured to have between 1 and 240 external interrupts Number of bits of interrupt priority – Can have between 3 and 8 bits of interrupt priority, giving 8 to 256 level of priority 19 AAME TechCon 2013 TC006v02 19 MPU – Implementing the MPU is optional for the Cortex-M3 ETM – Implemented with or without ETM – Note the ETM for Cortex-M3 only supports instruction tracing
- 20. Configuration - II JTAG-DP/SW-DP – Can be implemented with standard five pin JTAG, SW-DP or both The Cortex-M3 supports two levels of clock-gating – Use of RTL clock-gating is optional and requires a tool such as Synopsys Power Compiler to infer clock gates from the RTL – Architectural clock-gating is implemented at the Cortex-M3Integration and CortexM3 20 AAME TechCon 2013 TC006v02 20 – Architectural clock-gating is implemented at the Cortex-M3Integration and CortexM3 level of hierarchy and instantiates an integrated clock-gating cell from the technology library ROM table – The ROM table is a register file 4KB in size and identifies the system components available for debug – If the debug components are modified, the ROM table must also be modified to reflect this
- 21. Agenda ARM Cortex®-M0 processor ARM Cortex-M0+ processor 21 AAME TechCon 2013 TC006v02 21 ARM Cortex-M3 processor ARM Cortex-M4 processor
- 22. Cortex-M4 Processor Identical to Cortex-M3 processor with some additions – Extensive DSP Instructions – Optional Single-Precision Floating Point Unit Cortex-M3 and Cortex-M4 processors derived from same database 22 AAME TechCon 2013 TC006v02 22 Cortex-M3 processor comes With example system Cortex-M4 processor comes with integration kit
- 23. Cortex-M4 Floating Point Unit The Cortex-M4 processor includes a tightly integrated hardware floating point unit – Implements the FPv4-SP architecture – Separate register file with 16 double-precision registers (32 single-precision registers) – IEEE-754 compliant Hardware implements single-precision arithmetic – Double-precision handled through software Functions supported in hardware 23 AAME TechCon 2013 TC006v02 23 Functions supported in hardware – Multiply, add, subtract, multiply-accumulate – Comparison and format conversion – Divide and square root Other operations (e.g. vectoring) require support code The FPU is disabled at reset – Must be enabled and configured by initialization code – Must be done before the C library initialization – Sample code available in chapter 7 of the Cortex-M4 TRM
- 24. Memory Protection Unit (MPU) Provides access control for various memory regions Zero Latency Memory Protection – 8 register-stored regions – Minimum region size 32 bytes (max 4GB) – No address translation or page tables 24 AAME TechCon 2013 TC006v02 24 Configured via memory-mapped control registers MPU is optional
- 25. Implementation Options Number of Interrupts (1 - 240) Number of Priority bits (3 - 8) Optional Blocks – MPU – Memory Protection Unit – ETM – Embedded Trace Macrocell – DWT – Data Watchpoint and Trace – FPB – Flash Patch and Breakpoint Unit 25 AAME TechCon 2013 TC006v02 25 – FPB – Flash Patch and Breakpoint Unit – ITM – Instrumentation Trace Module Cut-down versions for reduced gatecount – DWT, FPB Debug can be modified for use in a full-CoreSight multi-processor system – SWJ-DP removed and TPIU replaced with full-CoreSight alternative Wake-up Interrupt Controller Optional FPU on Cortex-M4 processor
- 26. Cortex-M Series Processor Implementation Diversity