Adder Presentation
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The document discusses different types of single-bit adders and multi-bit adders built from them. It describes half adders, full adders, ripple carry adders and their delay properties. It then discusses different advanced adder circuits like carry lookahead adders, carry skip adders, carry select adders and carry save adders to reduce the delay. Verilog code examples are provided for full adders, ripple carry adders, carry lookahead adders and carry skip adders.
![ module fulladd(a,b,carryin,sum,carryout);
input a, b, carryin; /* add these bits*/
output sum, carryout; /* results */
assign {carryout, sum} = a + b + carryin;
/* compute the sum and carry */
endmodule
module nbitfulladd(a,b,carryin,sum,carryout);
input[7:0] a, b; /* add these bits */
input carryin; /* carry in*/
output [7:0] sum; /* result */
output carryout;
wire [7:1] carry; /* transfers the carry between bits */
fulladd a0(a[0],b[0],carryin,sum[0],carry[1]);
fulladd a1(a[1],b[1],carry[1],sum[1],carry[2]);
fulladd a2(a[2],b[2],carry[2],sum[2],carry[3]);
fulladd a3(a[3],b[3],carry[3],sum[3],carryout);
endmodule](https://image.slidesharecdn.com/presentation-13420353638813-phpapp01-120711143630-phpapp01/85/Adder-Presentation-5-320.jpg)
![ module sum(a,b,carryin,result);
input a, b, carryin; /* add these bits*/
output result; /* sum */
assign result = a ^ b ^ carryin;
/* compute the sum */
endmodule
module carry_block(a,b,carryin,carry);
input [3:0] a, b; /* add these bits*/
input carryin; /* carry into the block */
output [3:0] carry; /* carries for each bit in the block */
wire [3:0] g, p; /* generate and propagate */
assign g[0] = a[0] & b[0]; /* generate 0 */
assign p[0] = a[0] ^ b[0]; /* propagate 0 */
assign g[1] = a[1] & b[1]; /* generate 1 */
assign p[1] = a[1] ^ b[1]; /* propagate 1 */
assign g[2] = a[2] & b[2]; /* generate 2 */
assign p[2] = a[2] ^ b[2]; /* propagate 2 */
assign g[3] = a[3] & b[3]; /* generate 3 */
assign p[3] = a[3] ^ b[3]; /* propagate 3 */
assign carry[0] = g[0] | (p[0] & carryin);
assign carry[1] = g[1] | p[1] & (g[0] | (p[0] & carryin));
assign carry[2] = g[2] | p[2] &
(g[1] | p[1] & (g[0] | (p[0] & carryin)));
assign carry[3] = g[3] | p[3] &
(g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin))));
endmodule](https://image.slidesharecdn.com/presentation-13420353638813-phpapp01-120711143630-phpapp01/85/Adder-Presentation-13-320.jpg)
![ module carry_lookahead_adder(a,b,carryin,sum,carryout);
input [3:0] a, b; /* add these together */
input carryin;
output [3:0] sum; /* result */
output carryout;
wire [4:1] carry; /* intermediate carries */
/* build the carry-lookahead units */
carry_block b0(a[3:0],b[3:0],carryin,carry[4:1]);
/* build the sum */
sum a0(a[0],b[0],carryin,sum[0]);
sum a1(a[1],b[1],carry[1],sum[1]);
sum a2(a[2],b[2],carry[2],sum[2]);
sum a3(a[3],b[3],carry[3],sum[3]);
endmodule](https://image.slidesharecdn.com/presentation-13420353638813-phpapp01-120711143630-phpapp01/85/Adder-Presentation-14-320.jpg)
![ module fulladd_p(a,b,carryin,sum,carryout,p);
input a, b, carryin; /* add these bits*/
output sum, carryout, p; /* results including propagate */
assign {carryout, sum} = a + b + carryin;
/* compute the sum and carry */
assign p = a | b;
endmodule
module carryskip(a,b,carryin,sum,carryout);
input [7:0] a, b; /* add these bits */
input carryin; /* carry in*/
output [7:0] sum; /* result */
output carryout;
wire [8:1] carry; /* transfers the carry between bits */
wire [7:0] p; /* propagate for each bit */
wire cs4; /* final carry for first group */
](https://image.slidesharecdn.com/presentation-13420353638813-phpapp01-120711143630-phpapp01/85/Adder-Presentation-18-320.jpg)
![ fulladd_p a0(a[0],b[0],carryin,sum[0],carry[1],p[0]);
fulladd_p a1(a[1],b[1],carry[1],sum[1],carry[2],p[1]);
fulladd_p a2(a[2],b[2],carry[2],sum[2],carry[3],p[2]);
fulladd_p a3(a[3],b[3],carry[3],sum[3],carry[4],p[3]);
assign cs4 = carry[4] | (p[0] & p[1] & p[2] & p[3] & carryin);
fulladd_p a4(a[4],b[4],cs4, sum[4],carry[5],p[4]);
fulladd_p a5(a[5],b[5],cs4, sum[5],carry[6],p[5]);
fulladd_p a6(a[6],b[6],cs4, sum[6],carry[7],p[6]);
fulladd_p a7(a[7],b[7],cs4, sum[7],carry[8],p[7]);
assign carryout = carry[8] | (p[4] & p[5] & p[6] & p[7] &
cs4);
endmodule](https://image.slidesharecdn.com/presentation-13420353638813-phpapp01-120711143630-phpapp01/85/Adder-Presentation-19-320.jpg)
Adder Presentation
- 2. Single bit adders Half Adder Full Adder
- 3. Full Adder Computes one-bit sum, carry si = ai XOR bi XOR ci ci+1 = aibi + aici + bici Adder delay is dominated by carry chain Ripple-carry adder: n-bit adder built from full adders. Delay of ripple-carry adder goes through all carry bits
- 4. 4-bit Ripple carry adder T adder=(N-1)*Tcarry+ Tsum
- 5. module fulladd(a,b,carryin,sum,carryout); input a, b, carryin; /* add these bits*/ output sum, carryout; /* results */ assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */ endmodule module nbitfulladd(a,b,carryin,sum,carryout); input[7:0] a, b; /* add these bits */ input carryin; /* carry in*/ output [7:0] sum; /* result */ output carryout; wire [7:1] carry; /* transfers the carry between bits */ fulladd a0(a[0],b[0],carryin,sum[0],carry[1]); fulladd a1(a[1],b[1],carry[1],sum[1],carry[2]); fulladd a2(a[2],b[2],carry[2],sum[2],carry[3]); fulladd a3(a[3],b[3],carry[3],sum[3],carryout); endmodule
- 7. Substractor
- 9. Static adder Circuit Co= AB+BCi+ACi S= ABCi+Co’(A+B+Ci)
- 10. Manchester carry chain adder (a)Without pass transistors, (b)with pass transistors
- 11. Carry Look Ahead Adder
- 12. Carry Look Ahead Adder
- 13. module sum(a,b,carryin,result); input a, b, carryin; /* add these bits*/ output result; /* sum */ assign result = a ^ b ^ carryin; /* compute the sum */ endmodule module carry_block(a,b,carryin,carry); input [3:0] a, b; /* add these bits*/ input carryin; /* carry into the block */ output [3:0] carry; /* carries for each bit in the block */ wire [3:0] g, p; /* generate and propagate */ assign g[0] = a[0] & b[0]; /* generate 0 */ assign p[0] = a[0] ^ b[0]; /* propagate 0 */ assign g[1] = a[1] & b[1]; /* generate 1 */ assign p[1] = a[1] ^ b[1]; /* propagate 1 */ assign g[2] = a[2] & b[2]; /* generate 2 */ assign p[2] = a[2] ^ b[2]; /* propagate 2 */ assign g[3] = a[3] & b[3]; /* generate 3 */ assign p[3] = a[3] ^ b[3]; /* propagate 3 */ assign carry[0] = g[0] | (p[0] & carryin); assign carry[1] = g[1] | p[1] & (g[0] | (p[0] & carryin)); assign carry[2] = g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin))); assign carry[3] = g[3] | p[3] & (g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin)))); endmodule
- 14. module carry_lookahead_adder(a,b,carryin,sum,carryout); input [3:0] a, b; /* add these together */ input carryin; output [3:0] sum; /* result */ output carryout; wire [4:1] carry; /* intermediate carries */ /* build the carry-lookahead units */ carry_block b0(a[3:0],b[3:0],carryin,carry[4:1]); /* build the sum */ sum a0(a[0],b[0],carryin,sum[0]); sum a1(a[1],b[1],carry[1],sum[1]); sum a2(a[2],b[2],carry[2],sum[2]); sum a3(a[3],b[3],carry[3],sum[3]); endmodule
- 16. Carry skip adder Tp=Tsetup+(M-1)*tcarry+(N/M-1)*Tbypass+ (M-1)*tcarry+Tsum
- 17. Manchester carry chain implementation of carry skip adder
- 18. module fulladd_p(a,b,carryin,sum,carryout,p); input a, b, carryin; /* add these bits*/ output sum, carryout, p; /* results including propagate */ assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */ assign p = a | b; endmodule module carryskip(a,b,carryin,sum,carryout); input [7:0] a, b; /* add these bits */ input carryin; /* carry in*/ output [7:0] sum; /* result */ output carryout; wire [8:1] carry; /* transfers the carry between bits */ wire [7:0] p; /* propagate for each bit */ wire cs4; /* final carry for first group */
- 19. fulladd_p a0(a[0],b[0],carryin,sum[0],carry[1],p[0]); fulladd_p a1(a[1],b[1],carry[1],sum[1],carry[2],p[1]); fulladd_p a2(a[2],b[2],carry[2],sum[2],carry[3],p[2]); fulladd_p a3(a[3],b[3],carry[3],sum[3],carry[4],p[3]); assign cs4 = carry[4] | (p[0] & p[1] & p[2] & p[3] & carryin); fulladd_p a4(a[4],b[4],cs4, sum[4],carry[5],p[4]); fulladd_p a5(a[5],b[5],cs4, sum[5],carry[6],p[5]); fulladd_p a6(a[6],b[6],cs4, sum[6],carry[7],p[6]); fulladd_p a7(a[7],b[7],cs4, sum[7],carry[8],p[7]); assign carryout = carry[8] | (p[4] & p[5] & p[6] & p[7] & cs4); endmodule
- 21. Carry select adder Tadd=Tsetup+M*tcarry+(N/M)*Tmux+Tsum
- 22. Carry save adder
- 23. Thank You
Editor's Notes
- #4: Ripple carry adder delay is propotional to no of stages, in worst case it goes to thru all the stages.
- #12: A clacan reduce the delay. In principle the delay can be reduced so that it is proportional to logn, but for large numbers this is no longer the case, because even when carry look-ahead is implemented, the distances that signals have to travel on the chip increase in proportion to n, and propagation delays increase at the same rate .
- #23: If the adder is required to add two numbers and produce a result, carry-save addition is useless, since the result still has to be converted back into binary and this still means that carries have to propagate from right to left. But in large-integer arithmetic, addition is a very rare operation, and adders are mostly used to accumulate partial sums in a multiplication. 0 or 1, from the number we are adding.0 if the digit in our store is 0 or 2, or 1 if it is 1 or 3.0 if the digit to its right is 0 or 1, or 1 if it is 2 or 3.