SlideShare a Scribd company logo
Additionneur complet 4 bits AC4
library ieee;
use ieee.std_logic_1164.all;
entity AC4 is
port( A,B: in std_logic_vector(3 downto 0);
som : out std_logic_vector(3 downto 0);
Ret: out std_logic
);
end AC4;
architecture arch of AC4 is

component da is
port ( A,B : in std_logic;
sigma, R : out std_logic
);

end component;

component ac1 is
port ( a,b,r: in std_logic;
S, Ro: out std_logic
);

end component;
signal x:std_logic_vector (3 downto 0);

begin
objet1: da port map ( A(0),B(0),som(0),x(0));
objet2: ac1 port map ( A(1),B(1),x(0),som(1),x(1));
objet3: ac1 port map ( A(2),B(2),x(1),som(2),x(2));
objet4: ac1 port map ( A(3),B(3),x(2),som(3),x(3));

Ret<=x(3);
end arch;

More Related Content

DOCX
PPT
Eecs 317 20010209
DOCX
Dsd prac1
PDF
Verilog full adder in dataflow & gate level modelling style.
PDF
Verilog lab manual (ECAD and VLSI Lab)
DOCX
Non- recusive
PDF
Lec14-CS110 Computational Engineering
Eecs 317 20010209
Dsd prac1
Verilog full adder in dataflow & gate level modelling style.
Verilog lab manual (ECAD and VLSI Lab)
Non- recusive
Lec14-CS110 Computational Engineering

What's hot (20)

PDF
Carry save adder Type 2
DOCX
Computer Architecture and Organization lab with matlab
PPTX
Linked list2
PDF
Carry save adder vhdl
DOC
All VLSI programs
PDF
Chapter 5
PPSX
Vhd lhigh2003
PPTX
PDF
Gpus graal
PDF
VHDL Programs
PDF
Efficient SIMD Vectorization for Hashing in OpenCL
PDF
ECAD lab manual
DOCX
Compiler Design Lab File
PDF
Roots of a quadratic equation1
PPTX
Stack using Array
PDF
Digital System Design Lab Report - VHDL ECE
PPTX
Stack using Linked List
PPT
Doublylinklist
PPTX
Programming in c function
Carry save adder Type 2
Computer Architecture and Organization lab with matlab
Linked list2
Carry save adder vhdl
All VLSI programs
Chapter 5
Vhd lhigh2003
Gpus graal
VHDL Programs
Efficient SIMD Vectorization for Hashing in OpenCL
ECAD lab manual
Compiler Design Lab File
Roots of a quadratic equation1
Stack using Array
Digital System Design Lab Report - VHDL ECE
Stack using Linked List
Doublylinklist
Programming in c function
Ad

Programme en C: Additionneur complet 4 bits ac4

  • 1. Additionneur complet 4 bits AC4 library ieee; use ieee.std_logic_1164.all; entity AC4 is port( A,B: in std_logic_vector(3 downto 0); som : out std_logic_vector(3 downto 0); Ret: out std_logic ); end AC4; architecture arch of AC4 is component da is port ( A,B : in std_logic; sigma, R : out std_logic ); end component; component ac1 is port ( a,b,r: in std_logic; S, Ro: out std_logic ); end component;
  • 2. signal x:std_logic_vector (3 downto 0); begin objet1: da port map ( A(0),B(0),som(0),x(0)); objet2: ac1 port map ( A(1),B(1),x(0),som(1),x(1)); objet3: ac1 port map ( A(2),B(2),x(1),som(2),x(2)); objet4: ac1 port map ( A(3),B(3),x(2),som(3),x(3)); Ret<=x(3); end arch;