Dsd prac1

Practical No 1
AND GATE (Data flow)
Source code
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entitydatafolwand is
port(A,B : in bit;Z : out bit);
enddatafolwand;
architecturedatafolwand of datafolwand is
begin
Z <= A and B;
enddatafolwand;
Wave form

OR GATE(Data flow)
Source code
library IEEE;
entity dataflow-or is
end dataflow-or;
architecture dataflow-or of dataflow-or is
begin
Z<= A or B;
end dataflow-or;
Wave Form

NOT GATE(Data flow)
Source code
library IEEE;
entity dataflow not gate is
port(A : in bit;Z : out bit);
end dataflow not gate;
architecture dataflow not gate of dataflow not gate is
begin
Z <= not A;
Wave Form

XOR GATE(Data flow)
Source code
library IEEE;
entity dataflow not gate is
architecture dataflow not gate of dataflow not gate is
begin
Z <= Axor B;
Wave Form

XNOR GATE (Data flow)
Source code
library IEEE;
entity xnor gate is
end xnor gate;
architecture xnorgate of xnor gate is
begin
Z<= Axnor B;
end xnor gate;
Wave Form

AND GATE (Behavirol)
Source code
library IEEE;
entitybheavand is
endbheavand;
architecture and of bheavand is
begin
process(A,B);
Z <= A and B;
end process;
endbheavand;
Wave Form

OR GATE (Behavirol)
Source code
library IEEE;
entity behavirol-or is
end behavirol-or;
architecture behavirol-or of behavirol-or is
begin
process(A,B)
begin
Z<= A or B;
end process;
end dataflow-or;
Wave Form

NOT GATE (Behavirol)
Source code
library IEEE;
entity not gate is
port(A : in bit;Z : out bit);
end not gate;
architecture not gate of not gate is
begin
process(A)
begin
Z <= not A;
end process;
end not gate;
Wave Form

XOR GATE (Behavirol)
Source code
library IEEE;
entity xor gate is
end xor gate;
architecture xorgate of xor gate is
begin
process(A,B)
begin
Z <= Axor B;
end process;
end xor gate;
Wave Form

XNOR GATE (Behavirol)
Source code
library IEEE;
entity xnor gate is
end xnor gate;
architecture xnorgate of xnor gate is
begin
process(A,B)
begin
Z <= Axnor B;
end process;
end xnor gate;
Wave Form

Practical No 2
HALF ADDER (Data flow)
Source code
library IEEE;
entity dataflow-half adder is
port(A,B : in bit;S,C : out bit);
end dataflow-half adder;
architecture dataflow-half adder of dataflow-half adder is
begin
S <= A xor B; -- sum
C <= A and B; -- carry
end dataflow-half adder;
Wave form

HALF ADDER (Behavirol)
Source code
library IEEE;
entity half adder is
port(A,B : in bit;S,C : out bit);
end half adder;
architecture half adder of half adder is
begin
process(A,B)
begin
S <= A xor B; -- sum
C <= A and B; -- carry
end process;
end half adder;
Wave form

HALF ADDER (Structural)
Source code
half Adder
library IEEE;
entity adder is
port(A,B :in bit ;S,C :out bit);
end adder;
architecture adder of adder is
component XOR1
port(ao,bo :in bit ;do :out bit);
end component;
component and1
port(a1,b1 :in bit ;d1 :out bit);
end component;
begin
xo: XOR1 port map(A,B,S);
A3: and1 port map(A,B,C);
end adder;
-- For component xor1
ibrary IEEE;
entity xor1 is
port(ao,bo :in bit ;do :out bit);
end xor1;
architecture xor1 of xor1 is
begin
do<=l aoxorbo;
end xor1;
-- For component and1
library IEEE;
entity and1 is
port(a1,b1 :in bit ;d1 :out bit);
end and1;
architecture and1 of and1 is
begin
d1<= a1 and b1;
end and1;

Practical No 4
MULTIPLEXER 4:1 (Data flow)
Source code
library IEEE;
entity mux is
port(A,B,C,D,S0,S1: in bit; Y: out bit);
end mux;
architecture mux of mux is
begin
Y <= A when S0='0' and S1='0' else
B when S0='0' and S1='1' else
C when S0='1'and S1='0' else
D;
end mux;
Wave Form

MULTIPLEXER 4:1 (Behavirol)
Source code
library IEEE;
entity mux is
port(I0,I1,I2,I3,S0,S1 : in bit;Y :out bit);
end mux;
architecturemux_b of mux is
begin
process(I0,I1,I2,I3,S0,S1)
begin
if (S0='0' and S1 ='0') then
y<= I0;
elsif (S0='0' and S1='1') then
y<= I1;
y<= I2;
y<= I3;
end if;
end process;
endmux_b;
Wave Form

Practical No 3
FULL ADDER(Data flow)
Source code
library IEEE;
entity Full_adder1 is
PORT(A,B,E : IN BIT; S,C : OUT BIT);
end Full_adder1;
architecture Full_adder1 of Full_adder1 is
begin
S <= A XOR B XOR E;
C <= ((A AND B) OR (A AND E) OR (B AND E));
end Full_adder1;
Wave Form

FULL ADDER (Behavirol)
Source code
library IEEE;
entity Full_adder1 is
PORT(A,B,E : IN BIT; S,C : OUT BIT);
end Full_adder1;
architecture Full_adder1 of Full_adder1 is
begin
process (A,B,E)
begin
S <= A XOR B XOR E;
C <= ((A AND B) OR (A AND E) OR (B AND E));
end PROCESS;
end Full_adder1;
Wave Form

Practical No 5
D-MULIPLEXER (Data flow)
Source code
library IEEE;
entitydemux is
port(so,s1:in bit;A :out bit_vector(0 to 3));
enddemux;
architecturedmux_d of demux is
begin
A<= "1000" when so='0' and s1='0' else
"0100" when so='0' and s1='1' else
"0010" when so='1' and s1='0' else
"0001" when so='1' and s1='1';
enddmux_d;
Wave Form

Practical No 6
1-BIT COMPARATOR (Data flow)
Source code
library IEEE;
entity comparator is
port(A,B:inbit;Y: out bit_vector(0 to 2));
end comparator;
architecturecomparator_data of comparator is
begin
Y<= "010" when A=B else
"100" when A<B else
"001" when A>B;
endcomparator_data;
Wave Form

Practical No 7
4-BIT COMPARATOR (Behavioral)
Source code
library IEEE;
entity comparator_4 is
port(A,B : in bit_vector(0 to 3);Y : out bit_vector(0 to 2));
end comparator_4;
architecture comp-bhev of comparator_4 is
begin
process(A,B)
begin
if (A>B) then Y<="100";
elsif (A=B) then Y<="010";
elsif (A<B) then Y<="001";
end if;
end process;
end comp-bhev;
Wave Form

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