Vhdl
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The VHDL code implements a 4-input priority encoder with one hot encoding. It uses an if-else conditional statement to assign a 2-bit binary code to the output y based on the highest priority input bit set in w. It also assigns z to 0 if no inputs are set in w, and 1 otherwise.
Vhdl
- 1. 1 Refer to VHDL code and identify the logic LIBRARYieee; USE ieee.std_logic_1164.all; ENTITYpriority IS PORT( w : INSTD_LOGIC_VECTOR(3DOWNTO0); y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); z : OUT STD_LOGIC); END priority; ARCHITECTUREBehavior OF priority IS BEGIN PROCESS ( w ) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) ='1' THEN y <= "10" ; ELSIF w(1) ='1' THEN y <= "01" ; ELSE y <= "00" ; END IF ; END PROCESS ; z <= '0' WHEN w = "0000" ELSE'1'; END Behavior ; 2-bitpriorityencoder 2 Among the VHDL features, which language statements are executed at the same time in parallel flow? a. Concurrent b. Sequential c. Net-list d. Test-bench concurrent 3 In Net-list language, the net-list is generated _______synthesizing VHDL code. a. Before b. At the time of (during)
- 2. c. After d. None of the above After 4 Which data type in VHDL is non synthesizable & allows the designer to model the objects of dynamic nature? a. Scalar b. Access c. Composite d. File access 5 In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator? a. Compilation b. Elaboration c. Initialization d. Execution Elaboration 6 Hold time is defined as the time required for the data to ________ after the triggering edge of clock. a. Increase b. Decrease c. Remain stable d. All of the above remainstable 7 An Antifuse programming technology is predominantly associated with _____. a. SPLDs b. FPGAs c. CPLDs d. All of the above FPGAs 8 In fusible link technologies, the undesired fuses are removed by the pulse application of _____voltage & current to device input. a. Low b. Moderate
- 3. c. High d. All of the above High 9 The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________. a. Waveform Editor b. Waveform Estimator c. Waveform Simulator d. Waveform Evaluator waveformeditor 10 State box without decision and conditional box is A. ASM block B. defined block C. simple block D. both a and b Simple block 11 Table that is not a part of asynchronous analysis procedure is a. transition table b. state table c. flow table d. excitation table d