Introduction VHDL.ppt

VHDL - Introduction
1
Presented By
Y. Sravan Kumar, M.Tech, (Ph.D.)
Assistant Professor

Introduction
•Hardware description languages (HDL)
•Language to describe hardware
•Two popular languages
• VHDL: Very High Speed Integrated Circuits Hardware Description Language
• Developed by DOD from 1983
• IEEE Standard 1076-1987/1993/200x
• Based on the ADA language
• Verilog
• IEEE Standard 1364-1995/2001/2005
• Based on the C language

Applications of HDL
• Model and document digital systems
• Different levels of abstraction
• Behavioral, structural, etc.
• Verify design
• Synthesize circuits
• Convert from higher abstraction levels to lower abstraction levels
3

Input-Output specification of circuit
4
my_ckt
A
B
S
X
Y
 Example: my_ckt
 Inputs: A, B, C
 Outputs: X, Y
 VHDL description:
entity my_ckt is
port (
A: in bit;
B: in bit;
S: in bit;
X: out bit;
Y: out bit);
end my_ckt ;

VHDL entity
• entity my_ckt is
port (
A: in bit;
B: in bit;
S: in bit;
X: out bit;
Y: out bit
);
end my_ckt;
5
my_ckt
A
B
S
X
Y
 Name of the circuit
 User-defined
 Filename same as circuit
name
 Example.
 Circuit name: my_ckt
 Filename: my_ckt.vhd
Port names or
Signal names
 Name of the circuit
 User-defined
 Filename same as circuit
name recommended
 Example:
 Circuit name: my_ckt
 Filename: my_ckt.vhd
Datatypes:
 In-built
 User-defined
Direction of port
3 main types:
 in: Input
 out: Output
 inout: Bidirectional
Note the absence of semicolon
“;” at the end of the last signal
and the presence at the end of
the closing bracket

Built-in Datatypes
• Scalar (single valued) signal types:
• bit
• boolean
• integer
• Examples:
• A: in bit;
• G: out boolean;
• K: out integer range -2**4 to 2**4-1;
• Aggregate (collection) signal types:
• bit_vector: array of bits representing binary numbers
• signed: array of bits representing signed binary numbers
• Examples:
• D: in bit_vector(0 to 7);
• E: in bit_vector(7 downto 0);
• M: in signed (4 downto 0);
--signed 5 bit_vector binary number
6

User-defined datatype
• Construct datatypes arbitrarily or using built-in datatypes
• Examples:
• type temperature is (high, medium, low);
• type byte is array(0 to 7) of bit;
7

Functional specification
• Example:
• Behavior for output X:
• When S = 0
X <= A
• When S = 1
X <= B
• Behavior for output Y:
• When X = 0 and S =0
Y <= ‘1’
• Else
Y <= ‘0’
8
my_ckt
A
B
S
X
Y

VHDL Architecture
• VHDL description (sequential behavior):
architecture arch_name of my_ckt is
begin
p1: process (A,B,S)
• begin
if (S=‘0’) then
X <= A;
else
X <= B;
end if;
if ((X = ‘0’) and (S = ‘0’)) then
Y <= ‘1’;
else
Y <= ‘0’;
end if;
end process p1;
end;
9
Error: Signals defined as
output ports can only be
driven and not read

VHDL Architecture
architecture behav_seq of my_ckt is
signal Xtmp: bit;
begin
p1: process (A,B,S,Xtmp)
begin
if (S=‘0’) then
Xtmp <= A;
else
Xtmp <= B;
end if;
if ((Xtmp = ‘0’) and (S = ‘0’)) then
Y <= ‘1’;
else
Y <= ‘0’;
end if;
X <= Xtmp;
end process p1;
end;
10
Signals can only be
defined in this
place before the
begin keyword
General rule: Include all signals in
the sensitivity list of the process
which either appear in relational
comparisons or on the right side of
the assignment operator inside the
process construct.
In our example:
Xtmp and S occur in relational
comparisons
A, B and Xtmp occur on the right side of
the assignment operators

VHDL Architecture
• VHDL description (concurrent behavior):
architecture behav_conc of my_ckt is
signal Xtmp: bit;
begin
Xtmp <= A when (S=‘0’) else
B;
Y <= ‘1’ when ((Xtmp = ‘0’) and (S = ‘0’)) else
‘0’;
X <= Xtmp;
end ;
11

Signals vs Variables
• Signals
• Signals follow the notion of ‘event scheduling’
• An event is characterized by a (time,value) pair
• Signal assignment example:
X <= Xtmp; means
Schedule the assignment of the value of signal Xtmp to signal
X at (Current time + delta)
where delta: infinitesimal time unit used by simulator for
processing the signals
12

Signals vs Variables
• Variables
• Variables do not have notion of ‘events’
• Variables can be defined and used only inside the process block and
some other special blocks.
• Variable declaration and assignment example:
process (…)
variable K : bit;
begin
…
-- Assign the value of signal L to var. K immediately
K := L;
…
end process;
13
Variables can only
be defined and used
inside the process
construct and can
be defined only in
this place

Simulation
• Simulation is modeling the output response of
a circuit to given input stimuli
• For our example circuit:
• Given the values of A, B and S
• Determine the values of X and Y
• Many types of simulators used
• Event driven simulator is used popularly
• Simulation tool we shall use: ModelSim
14
my_ckt
A
B
S
X
Y

Simulation
architecture behav_seq of my_ckt is
signal Xtmp: bit;
begin
p1: process (A,B,S,Xtmp)
variable XtmpVar: bit;
begin
if (S=‘0’) then
Xtmp <= A;
else
Xtmp <= B;
end if;
if ((Xtmp = ‘0’) and (S = ‘0’)) then
Y <= ‘1’;
else
Y <= ‘0’;
end if;
X <= Xtmp;
XtmpVar := Xtmp;
end process p1;
end;
Time
‘T’
A B S Xtmp Y XtmpVar X
0- U U U ‘X’ ‘X’ ‘X’ ‘X’
0 0 1 0 ‘X’ ‘X’ ‘X’ ‘X’
0+d 0 1 0 0 0 0 ‘X’
0+2d 0 1 0 0 1 0 0
1 0 1 1 0 1 0 0
1+d 0 1 1 1 0 0 0
1+2d 0 1 1 1 0 0 1
ELEC2200-002 Lecture 7 (updated) 15
Scheduled events
list:
Xtmp = (0,0+d)
Y = (0,0+d)
X = (‘X’,0+d)
Assignments executed:
XtmpVar = ‘X’
Scheduled events
executed:
Xtmp = 0
Y = 0
X = ‘X’
Assignments executed:
XtmpVar = 0
Scheduled events
list:
Xtmp = (0,0+2d)
Y = (1,0+2d)
X = (‘0’,0+2d)
Scheduled events
executed:
Xtmp = 0
Y = 1
X = 0
Scheduled events
list:
(empty)

Synthesis
• Synthesis:
Conversion of behavioral level description to structural
level netlist
• Abstract behavioral description maps to concrete logic-level
implementation
• For ex. Integers at behavioral level mapped to bits at structural
level
• Structural level netlist
• Implementation of behavioral description
• Describes interconnection of gates
• Synthesis tool we shall use:
Leonardo Spectrum
16

Structural level netlist
• Behavior of our example circuit:
• Behavior for output X:
• When S = 0
X <= A
• When S = 1
X <= B
• Behavior for output Y:
• When X = 0 and S =0
Y <= 1
• Else
Y <= 0
17
my_ckt
A
B
S
X
Y
 Logic functions
 Sbar = ~ S
 Xbar = ~ X
 X = A*(Sbar) + B*S
 Y = (Xbar)*(Sbar)

Structural level netlist
architecture behav_conc of my_ckt is
-- component declarations
signal Sbar, Xbar, W1, W2: bit;
begin
G1: not port map(Sbar,S);
G2: and port map(W1,A,Sbar);
G3: and port map(W2,B,S);
G4: or port map(X,W1,W2);
G5: not port map(Xbar,X);
G6: and port map(Y,Xbar,Sbar);
end ;
18
 Gate level VHDL
descriptions
(and, or, etc) are
described separately
 Design in which other
design descriptions are
included is called a
“hierarchical design”
 A VHDL design is
included in current
design using port map
statement

Introduction VHDL.ppt

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