Introduction to VHDL language VHDL_Intro.ppt

VHDL
• VHDL Is an International IEEE Standard
Specification Language (IEEE 1076-2001)
for Describing Digital Hardware Used by
Industry Worldwide
–VHDL is an acronym for VHSIC (Very High
Speed Integrated Circuit) Hardware
Description Language

A Brief History of VHDL
• Very High Speed Integrated Circuit
(VHSIC) Program
–Launched in 1980
–Object was to achieve significant gains in
VLSI technology by shortening the time
from concept to implementation (18 months
to 6 months)
–There was a well known need for a common
descriptive and simulation language

• Woods Hole Workshop
– Held in June 1981 in Massachusetts
– Discussion of VHSIC goals
– Comprised of members of industry,
government, and academia

• July 1983: contract awarded to develop
VHDL
–Intermetrics
–IBM
–Texas Instruments
• August 1985: VHDL Version 7.2 released

• December 1987: VHDL became IEEE
Standard 1076-1987 and in 1988 an ANSI
standard
• September 1993: VHDL was
restandardized to clarify and enhance the
language
• 1998: Standard committee convened to
update VHDL-93
• 2001: Revised IEEE VHDL Standard

Languages Other Than VHDL
• VHDL: VHSIC (Very High Speed
Integrated Circuit) Hardware Description
Language
– Not the only hardware description language
– Some HDLs are proprietary
– Capabilities and uses of HDLs vary

VHDL for Specification
VHDL for Simulation
VHDL for Synthesis

Levels of design description
Algorithmic level
Register Transfer Level
Logic (gate) level
Circuit (transistor) level
Physical (layout) level
Level of description
most suitable for synthesis

Register Transfer Logic (RTL)
Design Description
Combinational
Logic
Combinational
Logic
Registers
Today’s Topic

Design Entity
Design Entity - most basic
building block of a design.
One entity can have
many different architectures.
entity declaration
architecture 1
architecture 2
architecture 3
design entity

Entity Declaration
• Entity Declaration describes the interface of the
component, i.e. input and output ports.
entity AND2_OP is
port(
A, B: in std_logic;
Z : out std_logic
);
end AND2_OP;
Reserved words
Entity name
Port names Port type
Semicolon
No Semicolon
Port modes (data flow directions)

Architecture Declaration
• Describes an implementation of a design
entity.
• Architecture declaration example:
architecture MODEL of AND2_OP is
begin
Z <= A and B;
end MODEL;

Entity Declaration & Architecture
use IEEE;
use IEEE.std_logic_1164.all;
entity AND2_OP is
port(
A, B: in std_logic;
Z : out std_logic);
end AND2_OP;
begin
Z <= A and B;
end MODEL;

Std_logic
use IEEE;
use IEEE.std_logic_1164.all;
entity AND2_OP is
port(
A, B: in std_logic;
Z : out std_logic);
end AND2_OP;
begin
Z <= A and B;
end MODEL;
Include these packages all the time!
What is std_logic you ask?

std_logic type Demystified
Value Meaning
‘U’ Not Initialized
‘X’ Forcing (Strong driven) Unknown
‘0’ Forcing (Strong driven) 0
‘1’ Forcing (Strong driven) 1
‘Z’ High Impedance
‘W’ Weak (Weakly driven) Unknown
‘L’
Weak (Weakly driven) 0.
Models a pull down.
‘H’
Weak (Weakly driven) 1.
Models a pull up.
‘-’ Don't Care

VHDL Design Styles
Components and
interconnects
structural
VHDL Design
Styles
dataflow
Concurrent
statements
behavioral
• Registers
• State machines
• Test benches
Sequential statements
Subset most suitable for synthesis

Dataflow Description
• Describes how data moves through the system
and the various processing steps.
• Data Flow uses series of concurrent statements
to realize logic. Concurrent statements are
evaluated at the same time; thus, order of these
statements doesn’t matter.
• Data Flow is most useful style when series of
Boolean equations can represent a logic.

Structural Description
• Structural design is the simplest to understand.
This style is the closest to schematic capture and
utilizes simple building blocks to compose logic
functions.
• Components are interconnected in a hierarchical
manner.
• Structural descriptions may connect simple gates
or complex, abstract components.
• Structural style is useful when expressing a
design that is naturally composed of sub-blocks.

Behavioral Description
• It accurately models what happens on the inputs
and outputs of the black box (no matter what is
inside and how it works).
• This style uses Process statements in VHDL.

Entity (XOR3 Gate)
entity XOR3 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
RESULT : out STD_LOGIC
);
end XOR3;

Dataflow Architecture (XOR3
Gate)
architecture XOR3_DATAFLOW of XOR3 is
signal U1_OUT: STD_LOGIC;
begin
U1_OUT<=A xor B;
RESULT<=U1_OUT xor C;
end XOR3_DATAFLOW;
U1_out
XOR3

Describing
Combinational Logic
Using Dataflow Design Style

Data-flow VHDL
• concurrent signal assignment ()
• conditional concurrent signal assignment
(when-else)
• selected concurrent signal assignment
(with-select-when)
• generate scheme for equations
(for-generate)
Major instructions
Concurrent statements

Data-flow VHDL: Example
0
0
0
1
0
1
1
1
c i 1
+
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
c i
x i
y i
00 01 11 10
0
1
x i
y i
c i
1
1
1
1
si
x i
y i
c i
 
=
00 01 11 10
0
1
x i
y i
c i
1
1 1 1
c i 1
+
x i
y i
x i
c i
y i
c i
+ +
=
c i
x i
y i si
c i 1
+
(a) Truth table
(b) Karnaugh maps
(c) Circuit
0
1
1
0
1
0
0
1
si

Operators
and or nand nor xor not xnor
= /= < <= > >=
•Logic operators
Relational operators

Wanted: Y = ab + cd
Incorrect
Y <= a and b or c and d
equivalent to
Y <= ((a and b) or c) and d
equivalent to
Y = (ab + c)d
Correct
Y <= (a and b) or (c and d)
No Implied Precedence

compare a = bc
Incorrect
… when a = b and c else …
equivalent to
… when (a = b) and c else …
Correct
… when a = (b and c) else …
Priority of logic and relational
operators

Vectors and Concatenation
signal A: STD_LOGIC_VECTOR(3 downto 0);
signal B: STD_LOGIC_VECTOR(3 downto 0);
signal C, D, E: STD_LOGIC_VECTOR(7 downto 0);
A <= ”0000”;
B <= ”1111”;
C <= A & B; -- C = ”00001111”
D <= ‘0’ & ”0001111”; -- D <= ”00001111”
E <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
‘1’ & ‘1’;
-- E <= ”00001111”

Data Flow Instructions (1)
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
When - Else
.…
Value N
Value N-1
Condition N-1
Condition 2
Condition 1
Value 2
Value 1
Target Signal
…

with choice_expression select
target_signal <= expression1 when choices1,
expression2 when choices2,
. . .
expressionN when choicesN;
With - Select
choices1
choices2
choicesN
expression1
target_signal
choice expression
expression2
expressionN

VHDL provides mechanism to produce well
patterned structures from instances (Adders,
Registers, RAMs). Any VHDL concurrent statement
may be included in a generate statement
including another generate statement. Component
instantiations can be made with generate
statement.
For Generate
name: for parameter_specification generate
[Declaration Statements
begin
{Concurrent Statements}
end generate name;

Remember: Miscellaneous
– VHDL is not case sensitive (end = END = EnD)
– All instructions and declarations end with a
semicolon
• Exception is the last port and generic
declaration
– Comments start after double dash “- -” and end at
the end of line
– Order within an architecture is unimportant
(Concurrency)
– Order within process is important (More on this
later)

Remember: Naming and
Labeling
– All names must start with an alphabet
character
– Use only alphabet characters, digits and
underscores
– Do not use any punctuation characters in a
name
– Do not use consecutive underscores
– All names and labels in a given entity and
architecture must be unique

Readability standards
Selected issues :
• Consistent Writing Style
• Consistent Naming Conventions
• Consistent Indentation
• Consistent Commenting Style
• Recommended File Headers
• File naming and contents
• Number of statements/declarations per line
• Ordering of port and signal declarations

Signals
signal A : std_logic;
signal B : std_logic_vector(7 downto 0);
wire
A
bus
B
1
8

Standard Logic Vectors
signal A: STD_LOGIC;
signal B: STD_LOGIC_VECTOR(3 downto 0);
signal C: STD_LOGIC_VECTOR(3 downto 0);
signal D: STD_LOGIC_VECTOR(7 downto 0);
signal E: STD_LOGIC_VECTOR(15 downto 0);
signal F: STD_LOGIC_VECTOR(8 downto 0);
……….
A <= ‘1’;
B <= ”0000”; -- Binary base assumed by default
C <= B”0000”; -- Binary base explicitly specified
D <= ”0110_0111”; -- You can use ‘_’ to increase readability
E <= X”AF67”; -- Hexadecimal base
F <= O”723”; -- Octal base

Describing
Combinational Logic
Using
Dataflow Design Style

target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
When - Else
.…
Value N
alue N-1
Condition N-1
Condition 2
Condition 1
Value 2
Value 1
Target Signal
…

Operators
• Relational operators
• Logic and relational operators precedence
= /= < <= > >=
not
= /= < <= > >=
and or nand nor xor xnor
Highest
Lowest

MLU: Block Diagram
B
A
NEG_A
NEG_B
IN0
IN1
IN2
IN3 OUTPUT
SEL1
SEL0
MUX_4_1
L0
L1
NEG_Y
Y
Y1
A1
B1
MUX_0
MUX_1
MUX_2
MUX_3

MLU: Entity Declaration
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MLU is
port(
NEG_A : in STD_LOGIC;
NEG_B : in STD_LOGIC;
NEG_Y : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
L1 : in STD_LOGIC;
L0 : in STD_LOGIC;
Y : out STD_LOGIC
);
end MLU;

MLU: Architecture Declarative
Section
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0:STD_LOGIC;
signal L: STD_LOGIC_VECTOR(1 downto 0);

MLU - Architecture Body
begin
A1<= not A when (NEG_A='1') else
A;
B1<= not B when (NEG_B='1') else
B;
Y <= not Y1 when (NEG_Y='1') else
Y1;
MUX_0 <= A1 and B1;
MUX_1 <= A1 or B1;
MUX_2 <= A1 xor B1;
MUX_3 <= A1 xnor B1;
L<=L1 & L0;
with (L) select
Y1 <= MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;

For Generate Statement
For Generate
name: for parameter_specification generate
[Declaration Statements]
begin
{Concurrent Statements}
end generate name;

PARITY: Entity Declaration
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity PARITY is
port(
Parity_in : in STD_LOGIC_VECTOR(7 downto 0);
Parity_out : out STD_LOGIC
);
end PARITY;

PARITY: Block Diagram
Xor_out(1)
Xor_out(2)
Xor_out(3)
Xor_out(4)
Xor_out(5) Xor_out(6)
Xor_out(7)

PARITY: Architecture
architecture PARITY_DATAFLOW of PARITY is
signal Xor_out: std_logic_vector (7 downto 1);
begin
Xor_out(1) <= Parity_in(0) xor Parity_in(1);
G2: for i in 1 to 6 generate
Xor_out(i+1) <= Xor_out(i) xor Parity_in(i+1);
end generate G2;
Parity_out <= Xor_out(7);
end PARITY_DATAFLOW;

Verifying the operation
of the circuit using
testbenches

Testbench Block Diagram
Testbench
Processes
Generating
Stimuli
Design Under
Test (DUT)
Observed Outputs

Testbench Defined
• Testbench applies stimuli (drives the inputs) to
the Design Under Test (DUT) and (optionally)
verifies expected outputs.
• The results can be viewed in a waveform window
or written to a file.
• Since Testbench is written in VHDL, it is not
restricted to a single simulation tool (portability).
• The same Testbench can be easily adapted to
test different implementations (i.e. different
architectures) of the same design.

Testbench Anatomy
Entity TB is
--TB entity has no ports
End TB;
Architecture arch_TB of TB is
--Local signals and constants
component TestComp --All Design Under Test component declarations
port ( );
end component;
-----------------------------------------------------
for DUT:TestComp use entity work.TestComp(archName)--Specify entity/arch pair
-- (OPTIONAL)
begin
testSequence: Process
--Main test process
end process;
DUT:TestComp port map( --Port map all the DUTs
);
End arch_TB;

Testbench For XOR3
library ieee;
use ieee.std_logic_1164.all;
entity XOR3_TB is
end XOR3_TB;
architecture XOR3_TB_ARCHITECTURE of XOR3_TB is
-- Component declaration of the tested unit
component xor3
port(
A : in std_logic;
B : in std_logic;
C : in std_logic;
RESULT : out std_logic );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal TEST_VECTOR:STD_LOGIC_VECTOR(2 downto 0);
signal TEST_RESULT: STD_LOGIC;

Testbench For XOR Gate(2)
begin
UUT : xor3
port map (
A => TEST_VECTOR(0),
B => TEST_VECTOR(1),
C => TEST_VECTOR(2),
RESULT => TEST_RESULT);
);
TESTING: process
begin
TEST_VECTOR<="000";
wait for 10 ns;
TEST_VECTOR<="001";
wait for 10 ns;
TEST_VECTOR<="010";
wait for 10 ns;
TEST_VECTOR<="011";
wait for 10 ns;
TEST_VECTOR<="100";
wait for 10 ns;
TEST_VECTOR<="101";
wait for 10 ns;
TEST_VECTOR<="110";
wait for 10 ns;
TEST_VECTOR<="111";
wait for 10 ns;
end process TESTING;
end XOR3_TB_ARCHITECTURE;

Execution of statements in a
PROCESS
• The execution of statements
continues sequentially till the
last statement in the process.
• After execution of the last
statement, the control is again
passed to the beginning of the
process.
TESTING: process
begin
TEST_VECTOR<=“00”;
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
Order
of
execution
Program control is passed to the
first statement after BEGIN

PROCESS with a WAIT
Statement
• The last statement in the
PROCESS is a WAIT instead
of WAIT FOR 10 ns.
• This will cause the PROCESS
to suspend indefinitely when
the WAIT statement is
executed.
• This form of WAIT can be used
in a process included in a
testbench when all possible
combinations of inputs have
been tested or a non-periodical
signal has to be generated.
TESTING: process
begin
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
wait;
Program execution stops here
Order
of
execution

Wait for vs. Wait
Wait for: waveform will keep repeating itself
forever
Wait : waveform will keep its state after the
last wait instruction.
0 1 2 3
…
0 1 2 3 …

Sequential Statements (3)
• Loop Statement
• Repeats a Section of VHDL Code
• Example: process every element in an array
in the same way
for i in range loop
statements
end loop;

TEST_DATA_GENERATOR: process
begin
TEST_AB<="00";
TEST_SEL<="00";
for I in 0 to 3 loop
for J in 0 to 3 loop
wait for 10 ns;
TEST_AB<=TEST_AB+"01";
end loop;
TEST_SEL<=TEST_SEL+"01";
end loop;
end process;
Loop Statement - Example

Structural VHDL
• component instantiation (port map)
• generate scheme for component instantiations
(for-generate)
• component instantiation with generic
(generic map, port map)
Major instructions

Structural Example:
Component NAND2 Instantiated Four Time
in1
in2
nand_out

Iterative circuits: 8-bit comparator
A(7) B(7)
CMP_IN(1)
CMP_IN(0)
A(6) B(6) A(0) B(0)
CMP_OUT(1)
CMP_OUT(0)
entity COMPARE8 is
port(
A, B: in STD_LOGIC_VECTOR(7 downto 0);
CMP_IN: in STD_LOGIC_VECTOR(1 downto 0);
CMP_OUT: out STD_LOGIC_VECTOR(1 downto 0));
end COMPARE8;
COMPARE8

8-bit comparator: Truth Table
CMP_IN CMP_OUT
00 00 if A=B
10 if A>B
01 if A<B
10 10 independently of A and B
11 (invalid inputs) --

A B
X_OUT
Y_OUT
BIT_COMPARE
entity BIT_COMPARE is
port(A, B, X_IN, Y_IN: in STD_LOGIC;
X_OUT, Y_OUT: out STD_LOGIC);
end BIT_COMPARE;
X_IN
Y_IN
Basic building block

X_IN & Y_IN X_OUT & Y_OUT
00 00 if A=B
10 if A=‘1’ and B=‘0’
01 if A=‘0’ and B=‘1’
11 (invalid inputs) --
Basic building block – Truth
Table

8-bit comparator - Architecture
A(7) B(7)
CMP_IN(1)
CMP_IN(0)
A(6) B(6) A(0) B(0)
CMP_OUT(1)
CMP_OUT(0)
INT_X(7) INT_X(1)
INT_Y(7) INT_Y(1)
INT_X(6)
INT_Y(6)

architecture STRUCTURE of COMPARE8 is
component BIT_COMPARE
end component;
signal INT_X, INT_Y: STD_LOGIC_VECTOR(7 downto 1);
begin
C7: BIT_COMPARE port map(A(7), B(7), CMP_IN(1), CMP_IN(0),
INT_X(7), INT_Y(7));
C6: BIT_COMPARE port map(A(6), B(6), INT_X(7), INT_Y(7),
INT_X(6), INT_Y(6));
. . .
C0: BIT_COMPARE port map(A(0), B(0), INT_X(1), INT_Y(1),
CMP_OUT(0), CMP_OUT(1));
end STRUCTURE;
Architecture without for-generate

8-bit comparator - Architecture
A(7) B(7)
CMP_IN(1)
CMP_IN(0)
A(6) B(6) A(0) B(0)
CMP_OUT(1)
CMP_OUT(0)
INT_X(7) INT_X(1)
INT_Y(7) INT_Y(1)
INT_X(8)
INT_Y(8)
INT_X(0)
INT_Y(0)

architecture STRUCTURE of COMPARE8 is
end component;
signal INT_X, INT_Y: STD_LOGIC_VECTOR(8 downto 0);
begin
INT_X(8) <= CMP_IN(1);
INT_Y(8) <= CMP_IN(0);
CASCADE: for I in 7 downto 0 generate
C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1),
INT_X(I), INT_Y(I));
end generate;
CMP_OUT(1) <= INT_X(0);
CMP_OUT(0) <= INT_Y(0);
end STRUCTURE;
Architecture with for-generate

N-bit Comparator – Entity
declaration
entity COMPAREN is
generic(N: positive); -- N – width of operands
port(
A, B: in BIT_VECTOR(N-1 downto 0);
CMP_IN: in BIT_VECTOR(1 downto 0);
CMP_OUT: out BIT_VECTOR(1 downto 0));
end COMPAREN;

architecture STRUCTURE of COMPAREN is
end component;
signal INT_X, INT_Y: STD_LOGIC_VECTOR(N downto 0);
begin
INT_X(N) <= CMP_IN(1);
INT_Y(N) <= CMP_IN(0);
CASCADE: for I in N-1 downto 0 generate
C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1),
INT_X(I), INT_Y(I));
end generate;
CMP_OUT(1) <= INT_X(0);
CMP_OUT(0) <= INT_Y(0);
end STRUCTURE;
N-bit Comparator – Architecture

component COMPAREN
generic(N: positive); -- N – width of operands
port(
A, B: in STD_LOGIC_VECTOR(N downto 0);
CMP_IN: in STD_LOGIC_VECTOR(1 downto 0);
CMP_OUT: out STD_LOGIC_VECTOR(1 downto 0));
end component;
………
CMP8: COMPAREN
generic map(N => 16)
port map(A => P1,
B => P2,
CMP_IN => SIG_IN,
CMP_OUT => SIG_OUT
);
N-bit Comparator – Instantiation

Introduction to VHDL language VHDL_Intro.ppt

VHDL statements terminated with a semicolon.

The approach used in C
• Name the function interface
you plan on writing (Function
declaration
• Code what the function will do
(the function body)
• Let the program know it exists
and is available to be called
(the proto-type)
• Call the function from the main
portion of code
The approach used in VHDL
• Name the module you plan to
decide (entity)
• Describe what the module will
do (architecture)
• Let the program know the
module exists and can be used
(component declaration)
• Use the module in your code
(component instantiation or
mapping)

Implement the discrete version of the circuit
The approach of this solution is to model each of the discrete gates as
individual systems
They are actually simple gates but the interfacing requirements of the VHDL
structural approach are the same regardless of whether the circuit elements
are simple gates or complex digital subsystems

Discrete gate implementation of 3-bit comparator
• The dashed line represents the boundary of the VHDL entity (signals that
cross this boundary must appear in the entity declaration
• Each of the internal signals that do not cross the dashed entity boundary)
have been given names
• This is a requirement for VHDL structural implementations as these signals
must be assigned to the various submodules on the interior of the design

Entity and Architecture Definitions for Discrete Gates
The first part of the solution is to provide entity and architecture implementations
for individual gates

The procedures for implementing a structural VHDLdesign
• Step 1: The first step is identical to the standard approach used
for implementing the circuits i.e. the entity
• The entity declaration can be directly derived from the dashed
box

• Step 2: Declare the two separate design units used in the circuit i.e.
XNOR and 3-input AND gate
• There are two factors involed in declaraing a design unit 1) how to do
it 2) where to place it.
• A component declaration can be viewed as a modification of the
associated entity declaration
• The word entity is replaced with the word components and the word
component must follow the word end to terminate the instantiation

Comparison of Entity and Component Declaration

Step 3: Declare internal signals used by your design. The required internal
signals for this design are the signals that are not intersected by the dashed
line
• These signals provide an interface between various design units that are
instantiated in the final design
• Three signals are required, used as the output of the XNOR gate and input
to the AND gate
Step 4: The final step is to create instances of the required modules and
map these instances of various components in the architecture body

Alternative architecture using implied mapping: Connections between
external signals from the design units are associated with the signals in
the higher level design by order of their appearance in the mapping
statement

Introduction to VHDL language VHDL_Intro.ppt

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