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VHDL 360©by: Mohamed Samy        Samer El-Saadany
CopyrightsCopyright © 2010 to authors. All rights reservedAll content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners.VHDL 360 ©2
Course PrerequisitesDigital/Logic designSystem architectureComputer architecture (is a plus)Software programming (is a plus)3VHDL 360 ©
Module 0Introduction to VHDL
ObjectiveOverview on VHDLSkills gained:VHDL History and usageVHDL design flowUnderstand concurrencyVHDL 360 ©5
6VHDL StandardSynthesizable VHDLWhat is VHDL?VHDL isA High level modeling languageA model that will be either used to synthesize H/W or just used as a simulation modelOnly a subset of the language can be used for synthesisVHDL 360 ©
VHDL history Very high speed integrated circuit Hardware Description LanguageEarly 1980s: Developed by U.S. Department of Defense1987: IEEE Standard 1076 - 87 1993: IEEE Standard 1076 – 93 (New features)1999: Analog Mixed Signal extension (VHDL-AMS)2008: IEEE Std 1076 – 2008 (New features)7VHDL 360 ©
Uses of VHDLDesign representationusing different abstraction levelsDesign documentationDesign simulationDesign synthesisDesign verification8VHDL 360 ©
Basic Design Flow9DesignEntryPlace and RouteVHDL 360 ©Behavioral SimulationfailedPost Place & Route SimulationfailedSucceededSynthesisSucceededStart ProductionPost Synthesis SimulationfailedSucceeded
Let’s have a quick look at the following model & try to understand the main sections in the code--LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY model1 ISPORT( a :INstd_logic;  b :INstd_logic;		  c :INstd_logic;		  d :INstd_logic; e :OUTstd_logic);END model1 ;ARCHITECTURErtlOF model1 IS-- This is a commentSIGNAL x :std_logic;SIGNAL y :std_logic;BEGIN	-- This is another comment	 x <= a AND b;	 y <= c AND d;	 e <= x OR y;  -- end of line commentENDrtl;VHDL 360 ©Libraries & Packages headersInterface definition(input/output ports)Functional/behavioral Implementation10
A closer look at the code: “Entity”--LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY model1 ISPORT( a :INstd_logic;  b :INstd_logic;		  c :INstd_logic;		  d :INstd_logic; e :OUTstd_logic);END model1 ;VHDL 360 ©Reusing Library componentsPackages defining data types& Functions to be used in our codeDefining a model with name “model1”Defining the interface ports, 				            	their types &						their directionmodel111
A closer look at the code:  “Architecture”ARCHITECTURErtlOF model1 IS -- This is a commentSIGNAL x :std_logic;SIGNAL y :std_logic;BEGIN	 -- This is another comment	 x <= a AND b;	 y <= c AND d;	 e <= x OR y;-- end of line commentENDrtl;VHDL 360 ©Comments start with --       	Internal declarations, for example 						signals used for connectionsComments start with --Assignments relating				   	outputs to inputs12
ConcurrencyBEGIN	 x <= a AND b;	 y <= c AND d;	 e <= x OR y;ENDrtl;VHDL 360 ©Think Hardware:In real life, the value @ x is always the result of a AND b, whenever a/b changes x will change accordinglySimilarly the value @ y will always change whenever c/d changesIt might happen that the value @ x changes at the same time the value @ y changes  Both changes happen concurrently								These assignment statements are concurrent,								they can be written in any orderVHDL is concurrent by nature13
Simple Exercise:Deduce the logic of the below model--LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY exercise1 ISPORT( a :INstd_logic;		 b :INstd_logic;		 c :OUTstd_logic;		 s :OUTstd_logic);END exercise1 ;ARCHITECTUREbehavOF exercise1 ISBEGIN	c <= a AND b;	s <= a XOR b;ENDbehav;VHDL 360 ©14
Simple Exercise:Deduce the logic of the below model--LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY exercise1 ISPORT( a :INstd_logic;		 b :INstd_logic;		 c :OUTstd_logic;		 s :OUTstd_logic);END exercise1 ;ARCHITECTUREbehavOF exercise1 ISBEGIN	c <= a AND b;	s <= a XOR b;ENDbehav;VHDL 360 ©I got it!!This is a Half adder Model15
Basic Concepts of Digital DesignPlease revise the following:Logic values

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Introduction to VHDL

  • 1. VHDL 360©by: Mohamed Samy Samer El-Saadany
  • 2. CopyrightsCopyright © 2010 to authors. All rights reservedAll content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners.VHDL 360 ©2
  • 3. Course PrerequisitesDigital/Logic designSystem architectureComputer architecture (is a plus)Software programming (is a plus)3VHDL 360 ©
  • 5. ObjectiveOverview on VHDLSkills gained:VHDL History and usageVHDL design flowUnderstand concurrencyVHDL 360 ©5
  • 6. 6VHDL StandardSynthesizable VHDLWhat is VHDL?VHDL isA High level modeling languageA model that will be either used to synthesize H/W or just used as a simulation modelOnly a subset of the language can be used for synthesisVHDL 360 ©
  • 7. VHDL history Very high speed integrated circuit Hardware Description LanguageEarly 1980s: Developed by U.S. Department of Defense1987: IEEE Standard 1076 - 87 1993: IEEE Standard 1076 – 93 (New features)1999: Analog Mixed Signal extension (VHDL-AMS)2008: IEEE Std 1076 – 2008 (New features)7VHDL 360 ©
  • 8. Uses of VHDLDesign representationusing different abstraction levelsDesign documentationDesign simulationDesign synthesisDesign verification8VHDL 360 ©
  • 9. Basic Design Flow9DesignEntryPlace and RouteVHDL 360 ©Behavioral SimulationfailedPost Place & Route SimulationfailedSucceededSynthesisSucceededStart ProductionPost Synthesis SimulationfailedSucceeded
  • 10. Let’s have a quick look at the following model & try to understand the main sections in the code--LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY model1 ISPORT( a :INstd_logic; b :INstd_logic; c :INstd_logic; d :INstd_logic; e :OUTstd_logic);END model1 ;ARCHITECTURErtlOF model1 IS-- This is a commentSIGNAL x :std_logic;SIGNAL y :std_logic;BEGIN -- This is another comment x <= a AND b; y <= c AND d; e <= x OR y; -- end of line commentENDrtl;VHDL 360 ©Libraries & Packages headersInterface definition(input/output ports)Functional/behavioral Implementation10
  • 11. A closer look at the code: “Entity”--LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY model1 ISPORT( a :INstd_logic; b :INstd_logic; c :INstd_logic; d :INstd_logic; e :OUTstd_logic);END model1 ;VHDL 360 ©Reusing Library componentsPackages defining data types& Functions to be used in our codeDefining a model with name “model1”Defining the interface ports, their types & their directionmodel111
  • 12. A closer look at the code: “Architecture”ARCHITECTURErtlOF model1 IS -- This is a commentSIGNAL x :std_logic;SIGNAL y :std_logic;BEGIN -- This is another comment x <= a AND b; y <= c AND d; e <= x OR y;-- end of line commentENDrtl;VHDL 360 ©Comments start with -- Internal declarations, for example signals used for connectionsComments start with --Assignments relating outputs to inputs12
  • 13. ConcurrencyBEGIN x <= a AND b; y <= c AND d; e <= x OR y;ENDrtl;VHDL 360 ©Think Hardware:In real life, the value @ x is always the result of a AND b, whenever a/b changes x will change accordinglySimilarly the value @ y will always change whenever c/d changesIt might happen that the value @ x changes at the same time the value @ y changes  Both changes happen concurrently These assignment statements are concurrent, they can be written in any orderVHDL is concurrent by nature13
  • 14. Simple Exercise:Deduce the logic of the below model--LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY exercise1 ISPORT( a :INstd_logic; b :INstd_logic; c :OUTstd_logic; s :OUTstd_logic);END exercise1 ;ARCHITECTUREbehavOF exercise1 ISBEGIN c <= a AND b; s <= a XOR b;ENDbehav;VHDL 360 ©14
  • 15. Simple Exercise:Deduce the logic of the below model--LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY exercise1 ISPORT( a :INstd_logic; b :INstd_logic; c :OUTstd_logic; s :OUTstd_logic);END exercise1 ;ARCHITECTUREbehavOF exercise1 ISBEGIN c <= a AND b; s <= a XOR b;ENDbehav;VHDL 360 ©I got it!!This is a Half adder Model15
  • 16. Basic Concepts of Digital DesignPlease revise the following:Logic values
  • 18. Level vs. Edge triggered
  • 22. Please revise the following (Logic gates, multiplexers, decoders, counters, adders, multipliers, shift registers, all types of flip flops)16VHDL 360 ©