VHDL

Introduction to VHDL M. Balakrishnan Dept of Computer Science & Engg. I.I.T. Delhi

Domains of Description : Gajski’s Y-Chart Behavioral domain Structural domain Physical domain Level of abstraction VHDL models

VHDL Development US DoD initiated in 80’s V ery H igh Speed ASIC D escription L anguage Initial objective was modeling only and thus only a simulator was envisaged Subsequently tools for VHDL synthesis were developed

HDL Requirements Abstraction Modularity Concurrency Hierarchy

Abstraction VHDL supports description of components as well as systems at various levels of abstraction Gate and component delays Clock cycles Abstract behavior without any notion of delays

Modularity Every component in VHDL is referred to as an entity and has a clear interface The interface is called an entity declaration The “internals” of the component are referred to as the architecture declaration There can be multiple architectures at even different levels of abstraction associated with the same entity

VHDL Description: AND gate entity AND2 is port (a, b: in bit ; c : out bit); end AND2; architecture beh of AND2 is begin c <= a and b; end beh;

Concurrency in VHDL Descriptions signals process 1 process 2 process n signals

Concurrent and Sequential Computations Processes are concurrent Sequential activity within each process Nesting of statements : Concurrent statements in a concurrent statement Sequential statements in a concurrent statement Sequential statements in a sequential statement

Modeling Styles in VHDL M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi

Modeling Styles Semantic model of VHDL Structural description Data Flow description Algorithmic description RTL description

Modeling Choices in VHDL Behavioral and Structural Domains Several Levels of Abstraction Multiple Styles of Behavioral Description: Data Flow Style (concurrent) Procedural Style (sequential) Combinations, variations and special cases of these, e.g., special case of data flow style - FSM described using guarded blocks special case of procedural style - FSM described using case statement in a process

Structural Description Carries same information as a NET LIST Net List = (Component instances) + (Nets) Structural Description in VHDL = (Signals) + (Component instances + Port maps) Many sophisticated features in VHDL to make it more versatile: * Variety of signal types * Generic components * Generate statements for creating arrays of component instances * Flexibility in binding components to design entities and architectures

Behavioral Description Procedural (textual order => execution order) Sequential statements Control constructs alter normal sequential flow Called Behavioral description in VHDL Non-procedural (textual order NOT => execution order) Concurrent statements Data flow (or rather data dependency restricts concurrency) Called Data flow description in VHDL

Concurrent Statements in VHDL process statement -- behavior concurrent procedure call -- behavior concurrent signal assign. -- data flow component instantiation -- structure generate statement -- structure block statement -- nesting concurrent assertion stmt -- error check

Example: 1-bit Full Adder entity FullAdder is port (X, Y, Cin: in bit; -- Inputs Cout, Sum: out bit); -- Outputs end FullAdder; X Y Cin Sum Cout FullAdder

Example: 1-bit Full Adder (contd.) Architecture Equations of FullAdder is begin -- Concurrent Assignment Sum <= X xor Y xor Cin after 10 ns; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 15 ns; end Equations;

Example: 4-bit Adder entity Adder4 is port (A, B: in bit_vector(3 downto 0); Ci: in bit; -- Inputs S: out bit_vector(3 downto 0); Co: out bit); -- Outputs end Adder4;

Example: 4-bit Adder (contd.) Architecture Structure of Adder4 is Component FullAdder port (X, Y, Cin: in bit; Cout, Sum: out bit); signal C: bit_vector (3 downto 1); begin -- Instantiations FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0)); FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1)); FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2)); FA3: FullAdder port map (A(3), B(3), C(3), Co, S(3)); end Structure;

Example: 4-bit Comparator entity nibble_comparator is port (a, b: in bit_vector (3 downto 0); gt,eq,lt : in bit; a_gt_b, a_eq_b, a_lt_b : out bit); end nibble_comparator;

Structural Description (contd.) architecture iterative of nibble_comparator is component comp1 port (a, b, gt,eq,lt : in bit; a_gt_b, a_eq_b, a_lt_b : out bit); end component ; for all : comp1 use entity work.bit_comparator(gate_level); signal im: bit_vector (0 to 8); begin c0:comp1 port map (a(0),b(0), gt, eq, lt, im(0), im(1), im(2)); c1toc2: for i in 1 to 2 generate c:comp1 port map (a(i),b(i),im(i*3-3),im(i*3-2),im(i*3-1), im(i*3+0),im(i*3+1),im(i*3+2)); end generate ; c3: comp1 port map (a(3),b(3),im(6),im(7),im(8), a_gt_b, a_eq_b, a_lt_b); end nibble_comparator;

Example: 1-bit Comparator (data flow) entity comp1 is port (a, b, gt,eq,lt : in bit; a_gt_b, a_eq_b, a_lt_b : out bit); end comp1; architecture dataflow of comp1 is signal s : bit; begin s <= (a and b) or (not a and not b); a_gt_b <= (gt and s) or (a and not b); a_lt_b <= (lt and s) or (not a and b); a_eq_b <= eq and s; end dataflow;

References Digital Systems Design Using VHDL Charles H. Roth, Jr., PWS Publishing Co. Chapter 2 (pp. 44 to 84) The Designer’s Guide to VHDL Peter J. Ashenden, Morgon Kaufmann

Behavioral Description in VHDL M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi

Example: D Flip-Flop entity DFF is port (D, CLK: in bit; Q: out bit; QN: out bit := ‘1’) ; end DFF; D CLK Q QN DFF

Example: DFF (contd.) Architecture Beh of DFF is begin process (CLK) begin if (CLK = ‘1’ then Q <= D after 10 ns; QN <= not D after 10 ns; endif; endprocess; end Beh;

Concurrent Conditional Assignment: 4 to 1 Multiplexer y <= x0 when sel = 0 else x1 when sel = 1 else x2 when sel = 2 else x3 when sel = 3 x0 x1 x2 x3 sel y

CASE Statement: 4 to 1 Multiplexer Case sel is when 0 => y <= x0 when 1 => y <= x1 when 2 => y <= x2 when 3 => y <= x3 end case x0 x1 x2 x3 y

Variables And Signals Architecture var of dummy is signal trigger, sum: integer := 0; begin process variable var1: integer:= 1; variable var3, var2: integer:= 2; begin wait on trigger; var3 := var1 + var2; var1 := var3; sum <= var1; end process; end var;

Variables And Signals Architecture sig of dummy is signal trigger, sum: integer := 0; signal sig1: integer:= 1; signal sig3, sig2: integer:= 2; begin process begin wait on trigger; sig3 <= sig1 + sig2; sig1 <= sig3; sum <= sig1; end process; end sig;

VHDL

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