Logic Synthesis
- 1. Logic Synthesis Prof. Vandana Pagar MIT ACSC
- 2. Logic Synthesis logic synthesis is the process of converting a high-level description of the design into an optimized gate-level representation, given a standard cell library and certain design constraints.
- 3. Designers mind as Logic Synthesis Tool:
- 4. Basic Computer aided logic Synthesis
- 5. Automated Logic Synthesis Automated logic synthesis has significantly reduced time for conversion from high-level design representation to gates. This has allowed designers to spend more time on designing at a higher level of representation, because less time is required for converting the design to gates.
- 6. Verilog HDL Synthesis ➢ For the purpose of logic synthesis, designs are currently written in an HDL at a register transfer level (XTL). ➢ The term RTL is used for an HDL description style that utilizes a combination of data flow and behavioral constructs. ➢ Logic synthesis tools take the register transfer-level HDL description and convert it to an optimized gate-level netlist
- 7. Verilog Constructs : A list of constructs that are typically accepted by logic synthesis tools is given in Table
- 10. Synthesis Design Flow RTL description:The designer describes the design at a high level by using RTL constructs Translation: The RTL description is converted by the logic synthesis tool to an unoptimized, intermediate, internal representation. This process is called translation. Unoptimized intermediate representation: The translation process yields an unoptimized intermediate representation of the design. The design is represented internally by the logic synthesis tool in terms of internal data structures.
- 11. Logic optimization: The logic is now optimized to remove redundant logic. Various technology independent boolean logic optimization techniques are used. This process is called logic optimization. Technology mapping and optimization:Until this step, the design description is independent of a specific targef technology. In this step, the synthesis tool takes the internal representation and implements the representation in gates, using the cells provided in the technology library. In other words, the design is mapped to the desired target technology. Technology library : The technology library contains library cells provided by ABC Inc. The term standard cell library used earlier in the chapter and the term technology library are identical and are used interchangeably.
- 12. Finally, the each cell is described in a format that is understood by the synthesis tool. The cell description contains information about the following: ❖ Functionality of the cell ❖ Area of the cell layout ❖ Timing information about the cell ❖ Power information about the cell A collection of these cells is called the technology library
- 13. Design Constraints: ● Timing-The circuit must meet certain timing requirements. An internal ● static timing analyzer checks timing. ● Area-The area of the final layout must not exceed a limit. ● Power-The power dissipation in the circuit must not exceed a threshold
- 14. Optimized gate-level description Optimized gate-level description After the technology mapping is complete, an optimized gate-level netlist described in terms of target technology components is produced. If this netlist meets the required constraints, it is handed to the ABC Inc. for final layout. Otherwise, the designer modifies the RTL or constraints the design to achieve the desired results. This process is iterated until the netlist meets the required constraints.
- 15. An Example of RTL-to-Gates: 4 Bit magnitude Comparator Design specification A magnitude comparator checks if one number is greater than, equal to, or less than another number. Design a 4-bit magnitude comparator IC chip that has the following specifications: ➢ Name of the design is magnitude-comparator ➢ Inputs A and B are 4-bit inputs. No X or z values will appear on A and B Inputs ➢ Output A>B is true if A is greater than B ➢ Output A<B is true if A is less than B ➢ Output A-eq-B is true if A is equal to B ➢ Magnitude comparator circuit must be as fast as possible. ➢ Area can be compromised for speed.
- 16. RTL description This is a technology-independent description.
- 17. Technology library We decide to use the 0.65 micron CMOS process called abc-100 used by ABC Inc. to make our IC chip. ABC Inc. supplies a technology library for synthesis. The library contains the following library cells. The library cells are defined in a format understood by the synthesis tool.
- 18. Design constraints According to the specification, the design should be as fast as possible for the target technology, abc-100. There are no area constraints. Thus, there is only one design constraint. Optimize the final circuit for fastest timing. Logic synthesis The RTL description of the magnitude comparator is read by the logic synthesis tool. The design constraints and technology library for abc-100 are provided to the logic synthesis tool. The logic synthesis tool performs the necessary optimizations and produces a gate-level description optimized for abc-100 technology.
- 19. Final, Optimized, Gate-Level Description The logic synthesis tool produces a final, gate-level description. The schematic for the gate-level circuit is shown in Figure
- 20. The gate-level Verilog description produced by the logic synthesis tool for the circuit is shown below. Ports are connected by name.
- 21. Verification of Gate-Level Netlist The optimized gate-level netlist produced by the logic synthesis tool must be verified for functionality. Also, the synthesis tool may not always be able to meet both timing and area requirements if they are too stringent. ~h&,a separate timing verification can be done on the gate-level netlist.
- 22. Functional Verification Identical stimulus is run with the original RTL and synthesized gate-level descriptions of the design. The output is compared to find any mismatches. For the magnitude comparator, a sample stimulus file is shown below.
- 24. Timing verification The gate-level netlist is typically checked for timing by use of timing simulation or by a static timing verifier. If any timing constraints are violated, the designer must either redesign part of the RTL or make trade-offs in design constraints for logic synthesis.
- 25. References Verilog HDL A guide to Digital Design and Synthesis by Samir Palnitkar
- 26. Thank You