VHDL summer training (ppt)
- 1. SUMMER TRAINNING ON VHDL JAY SHARMA 15EBKEC015
- 2. Content • What is HDL • Why HDL • What is VHDL • History of VHDL • Capabilities of VHDL • VHDL VS C • Design flow • VHDL simulation cycle • Design units in VHDL • Type of modelling
- 3. What Is HDL • HDL stands for Hardware Description Language • It use describe functionality of digital circuit Hardware Description Language
- 4. Why HDL? • In digital more complex circuit we can not draw because it consume lot of time and also not scalable mean we can not drawing bigger and bigger circuit , so we need a language who help the describe the circuit. • It is used to describe the structure and behavior of electronic circuit and digital logic circuits. • It use for simplicity and save time.
- 5. VHDL • What is VHDL? VHSIC very high speed integrated circuit Hardware Description Language
- 6. History Of VHDL • To provide single platform for information interchange in 1981 DOD give task to different companies to make common language for digital design. • In 1983 Texas Instrument ,IBM and Intermetrics develop version of VHDL. • Version 7.2 of VHDL was publically released in 1985. • VHDL was standardization by IEEE in 1987.
- 7. Capabilities Of VHDL • Ability of verify timing of design • Technology independent • Support large design • Flexible with cad tool • Can be implement on PLD • Use to generate GLN
- 8. VHDL VS C Language • VHDL is concurrent language while C is sequential language. • VHDL is synthesizable while C is not. • VHDL describe functionality of hardware while C describe functionality of software.
- 9. Design Flow
- 10. Simulation Cycle Simulation start End simulation Update signal Evaluate phase Increment Event
- 11. Design units in VHDL • Entity declaration • Architecture body • Configuration declaration • Package
- 12. Entity • Entity is the building block of VHDL program. • It is used to declare input and output ports. Example:- entity abcd is port(a: in std_logic; b: in std_logic; c: out std_logic); end abcd;
- 13. Architecture • It contain the internal description of the entity. Example :- architecture myabcd of abcd is begin output <= input1 and input2; end myabcd; Note :- One entity has ‘n’ of architectures.
- 14. • Configuration declaration :- it is used to associate architecture to an entity. Example:- configuration config of abcd is for myabcd end for; end config; • Package:- It provides a mechanism to store items that can be shared across many VHDL models. these items are function , components, procedure etc.
- 15. Type Of modeling • Structural style of modeling • Dataflow style of modeling • Behavioral style of modeling • Mixed style of modeling
- 16. Structural style • As a set of interconnected components(to represent structure) library ieee; use ieee.std_logic_1164.all; entity andgate is port(a, b: in bit; z: out bit); end andgate; architecture e1 of andgate is begin z <= a and b; end e1; entity xorgate is port(a, b: in bit; z: out bit); end xorgate; architecture e2 of xorgate is begin z <= a xor b; end e2; entity halfadder1 is port(a, b: in bit; s, c: out bit); end halfadder1; architecture structural of halfadder1 is component andgate port(a, b: in bit; z: out bit); end component; component xorgate port(a, b: in bit; z: out bit); end component; begin u1 : andgate port map(a,b,c); u2 : xorgate port map(a,b,s); end structural;
- 17. Data flow • Progamming based flow of signal from input to output port. library IEEE; use IEEE.std_logic_1164.all; entity and_gate is port( A: in std_logic; B: in std_logic; Y: out std_logic); end and_gate; architecture df of and_gate is begin Y <= A and B; end df;
- 18. Behavioral style • As a set of sequential assignment statements (to represent behavior) library ieee; use ieee.std_logic_1164.all; entity halfadder2 is port(a, b : in bit; s, c : out bit); end halfadder2; architecture behavioral of halfadder2 is begin p1: process(a,b) begin if a & b = "00" then s <= '0'; c <= '0'; elsif a & b = "01" or a & b = "10" then s <= '1'; c <= '0'; else s <= '0'; c <= '1'; end if; end process; end behavioral;
- 19. Thank you