BEC302_DSDV Lab Manual 3rd sem(1) (1) (2).docx

Digital System and Design using Verilog
Subject Code: BEC302
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
Lab Incharge
Prof. Subiya Fatima
1

Sl.
No
TOPIC
PAGE
NO
1. Introduction to Lab 3
2. Experiments
PART-A
1 To simplify the given Boolean expressions and realize using Verilog
program
16
2 To realize Adder/ Subtractor (Full/half) circuits using Verilog dataflow
description
18
3 To realize 4-bit ALU using Verilog program. 24
4
To realize the following Code converters using Verilog Behavioral
description
a)Gray to binary and vice versa b)Binary to excess3 and vice versa
25
5 To realize using Verilog Behavioral description:8:1mux,8:3encoder,
Priority encoder
30
6 To realize using Verilog Behavioraldescription:1:8Demux,3:8
decoder,2–bitComparator
36
7 To realize usingVerilog Behavioral description:
Flip-flops: a) JKtype b)SRtype c)Ttype and d)D type
43
8 To realize Counters-up/down(BCD andbinary)using Verilog
Behavioral description
48
2

Introduction:
In electronics, a hardware description language or HDL is any language from a class of Computer
languages for formal description of electronic circuits. It can describe the circuit's operation, its design and
organization, and tests to verify its operation by means of simulation
HDLs are standard text-based expressions of the spatial, temporal structure and behavior of electronic
systems. In contrast to a software programming language, HDL syntax, semantics include explicit notations
for expressing time and concurrency, which are the attributes of hardware.Languageswhoseonlycharacteristic
is to express circuit connectivity between hierarchies of blocks are properly classified as net list languages.
HDLs are used to write executable specifications of some piece of hardware. A simulation program,
designed to implement the underlying semantics of the language statements, coupled with simulating the
progress of time ,provides the hardware designer with the ability to model a piece of hardware before it is
created physically. It is this executes ability that gives HDLs the illusion of being programming languages.
Simulators capable of supporting discrete-event and continuous-time(Analog)modeling exist, and HDLs
targeted for each are available.
It is certainly possible to represent hardware semantics using traditional programming languages such
as C++, although to function such programs must be augmented with extensive and unwieldy class libraries.
Primarily, however, software programming languages function as a hardware description language
1. VHDL (VHSICHDL)
2. Verilog
1.VHDL (Very High Speed Integrated Circuit Hardware Description Language) is commonly used as
a design-entry language for field-programmable gate arrays and application-specific integrated circuits in
electronic design automation of digital circuits.
VHDL is a fairly general-purpose language, and it doesn’t require a simulatoron which to run the
code. There are a lot of VHDL compilers, which build executable binaries. It can read and write files on the
host computer, so a VHDL program can be written that generates another VHDL program to be incorporated
in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a
test bench that verifies with the user, and compares results with those expected. This is similar to the
capabilities of the Verilog language
VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as Xilinx or
Quartus) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be
verified using simulation software (such as Model Sim) which shows the waveforms of inputs and outputs of
the circuit after generating the appropriate test bench. To generate an appropriate test bench for a particular
3

circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a
4

Loop processor an iterative statement is required.
2. Verilog is a hardware description language (HDL) used to model electronic systems. The language
supports the design, verification, and implementation of analog, digital, and mixed -signal circuits at various
levels of abstraction
The designers of Verilog wanted a language with syntax similar to the C programming language so
that it would be familiar to engineers and readily accepted. The language is case-sensitive, has a preprocessor
like C, and the major control flow keywords, such as "if" and "while", are similar. The formatting mechanism
in the printing routines and language operator sand their precedence are also similar
The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to
define a block of code. The concept of time, so important to a HDL won't be found in C The language differs
from a conventional programming language in that the execution of statements is not strictly sequential. A
Verilog design consists of a hierarchy of modules are defined with a set of input, output, and bidirectional
ports. Internally, a module contains a list of wires and registers. Concurrent and sequential statements define
the behavior of the module by defining the relationships between the ports, wires, and registers Sequential
statements are placed inside a begin/end block and executed in sequential order within the block. But all
concurrent statements and all begin/end blocks in the design are executed in parallel, qualifying Verilog as a
Dataflow language. A module can also contain one or more instances of another module to define sub-
behavior.
A subset of statements in the language is synthesizable. If the modules in a design contains a net list
that describes the basic components and connections to be implemented in hardware only synthesizable
statements, software can be used to transform or synthesize the design into the net list may then be
transformed into, for example, a form describing the standard cells of an integrated circuit (e.g. ASIC) or a
bit stream for a programmable logic device (e.g. FPGA).
5

Introduction to Xilinx ISE
Xilinx ISE means Xilinx ® Integrated Software Environment (ISE), i.e programmable logic design
tool in electronics industry. This Xilinx ® design software suite allows taking design from design entry through
Xilinx device programming. The ISE Project Navigator manages and processes design through several steps in
the ISE design flow. These steps are Design Entry, Synthesis, Implementation, Simulation/Verification, and
Device Configuration. Xilinx is one of most popular software tool used to synthesize VHDL code.
Steps for HDL programs :
1. Double click on Xilinx ISE Design Suite 14.7
2. Go to file in that select newproject.
3. In the 2nd
window provide the name for the project, click on next.
4. In this window click next
6

5. The below window will open as shown
6. Click on finish.
7. Then select project,new source
7

8. Select Verilog module and provide the file name then click on next.
9. Now provide the input and output, click on next
8

Below window appears, then click on finish.
9

10. In displayed window write the program.
11. Go to file select the save option and save the program.
10

Right click on behavioral check syntax and run it,
11

Right click on simulation and run it,
Verify your truthtable with waveforms.
12

NORGate-Truth Table XORGate-Truth Table XNORGate-Truth Table:
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
0
0
0
Y
B
A
Y
B
A
NOTGateTruthTable:
Simulation using all the modeling styles and Synthesis of all the logic gates using Verilog HDL
Logic gates:
A logic gate is an idealized or physical device implementing a Boolean function; that is, it performs a
logical operation on one or more binary inputs, and produces a single binary output
AND Gate-Block Diagram: OR Gate Block Diagram NAND Gate-Block Diagram:
AND gate-Truth Table OR gate-Truth Table NAND Gate –Truth Table
A B Y A B Y A B Y
0 0 0 0 0 0 0 0 1
0 1 0 0 1 1 0 1 1
1 0 0 1 0 1 1 0 1
1 1 1 1 1 1 1 1 0
NOR Gate Block Diagram: XOR Gate Block Diagram XNOR Block Diagram:
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
NOT GateBlock Diagram:
13

Verilog ProgramforANDGate: Verilog ProgramforORGate:
moduleandgate(a,b,y); moduleorgate(a,b,y);
inputa,b; inputa,b;
outputy; outputy;
assigny=a&b; assigny=a|b;
endmodule endmodule
OutputWaveforms:
VerilogProgramforNANDGate: VerilogProgramforNORGate:
modulenandgate(a,b,y); modulenorgate(a,b,y);
inputa,b; inputa,b;
outputy; outputy;
assigny=~(a&b); assigny=~(a|b);
endmodule endmodule
OutputWaveforms:
15

Verilog ProgramforXORGate: Verilog ProgramforXNORGate:
modulexorgate(a,b,y); modulexnorgate(a,b,y);
inputa,b; inputa,b;
outputy; outputy;
assigny=a^b; assigny=~(a^b);
endmodule endmodule
OutputWaveforms:
Verilog Program for NOT Gate:
modulenotgate(a,y);
input a;
output y;
assigny=~a;
endmodule
Output Waveform:
16

Verilog Program:
moduleLogic_Gates(c,d,e,f,g,h,i,a,b); input
a, b;
outputc,d,e,f,g,h,i;
assign c = a
&b;assign d= ~ (a
&b); assign e= (a |
b);assign f= ~ (a |b);
assign g= a ^ b;
assignh=~(a^b);
assign i=~a;
endmodule
OutputWaveform:
Result: Verified and observe the output of all basicgates
17

ExptNo.1: To simplify the given Boolean expressions and realize using Verilog program
Theory: Boolean expression is an expression used in programming languages that produces a Boolean
value when evaluated. A logical statement that results in a Boolean value, either be True or False, is a
Boolean expression. Sometimes, synonyms are used to express the statement such as 'Yes' for 'True' and
'No' for 'False'. Also, 1 and 0 are used for digital circuits for True and False, respectively.
TruthTable:
Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
18

VerilogCode:
moduleBooleanexp(a,b,c,d,y);
input a,b,c,d;
output y;
assigny=a&b|c&d;
endmodule
OutputWaveform:
Result:VerifiedandobservetheoutputofgivenBoolean expression
19

HalfAdder
Expt.No.2: To realize Adder/Subtractor (Full/half) circuits using Verilog data flow
description. Half Adder:
A digital electronic circuit that functions to perform the addition on the binary numbers is defined as Half
Adder. The process of addition is denary the sole difference is then under system chosen. There exists
only 0 and 1 in the binary numbering system.
a Sum
b Carry
Fig. a. Block Diagram
Fig.b. Logic Diagram
TruthTable:
Inputs Outputs
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
VerilogProgram:
modulehalfadder(s,c,a,b); input
a, b;
output s, c;
assigns=a^b;
assignc=a&b;
endmodule
20

Full Adder
OutputWaveform:
Full Adder:
Theory: Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are
A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the
normal output is designated as S which is SUM. The C-OUT is also known as the majority 1’s detector,
whose output goes high when more than one input is high.
a Sum
b
Cin Carry
Fig.c.Block Diagram
Fig.d. LogicDiagram
21

TruthTable:
Inputs Outputs
a b Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
VerilogProgram:
modulefulladder(s,c,a,b,cin)
input a, b, cin;
output s, c;
assigns=a^b^ cin;
assignc=(a&b)|(b&cin)|(cin&a);
endmodule
OutputWaveform:
22

Half Subtractor:
Theory: An half subtractor is a digital logic circuit that performs binary subtraction of two single-bit
binary numbers. It has two inputs, A and B, and two outputs, DIFFERENCE and BORROW. The
DIFFERENCE output is the difference between the two input bits, while the BORROW output indicates
whether borrowing was necessary during the subtraction.
Fig.Block Diagram
TruthTable:
Inputs Outputs
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
VerilogCode:
modulehalfsub(a,b,diff,borrow);
input a,b;
outputdiff,borrow;
assign diff=a^b;
assignborrow=(~a)&&b;
endmodule
OutputWaveform:
23

Full Subtractor:
Theory: A full subtractor is a combinational circuit that performs subtraction of two bits, one is minuend
and other is subtrahend, taking into account borrow of the previous adjacent lower minuend bit. This circuit has
three inputs and two outputs. The three inputs A, B and Bin, denote the minuend, subtrahend, and previous
borrow, respectively.
Fig.Block Diagram
TruthTable:
Verilogcode:
modulefullsub(a,b,c,diff,borrow);
input a,b,c;
output diff,borrow;
assigndiff=(a^b)^c;
assignborrow=((~a)&b)|(b&c)|((~a)&c);
endmodule
24

OutputWaveform:
Result:VerifiedandobservetheoutputofAdder/Subtractor (Full/Half)
25

Expt.No:3: To realize n 4-bit ALU using Verilog program
Theory: Arithmetic Logic Unit is a common operational unit with number of storage registers connected to it, using which it
performs microoperations. To perform a microoperation, the contents of specified registers are placed in the inputs of the
common ALU. The ALU performs an operation and the result of the operation is then transferred to a destination register. The
ALU is a combinational circuit so that the entire registers transfer operation from the source register through the ALU and the
destination register can be performed during one clock pulse period.
VerilogCode:
modulealu(a,b,opcode,y);
input [3:0] a;
input[3:0]b;
input[2:0]opcode;
output[3:0]y;
reg[3:0] y;
always@(a,b,opcode) begin if
(en==1)
case (opcode)
3'b000:y=a+b;
3'b001:y=a-b;
3'b010:y=~a;
3'b011:y=a*b;
3'b100:y= a&b;
3'b101:y=a|b;
3'b110:y=~(a&b);
3'b111:y=a^b;
default:begin
end
endcase
end
endmodule
OutputWaveform:
26

BinarytoGray
Expt.No.4: Aim: To realize the following Code converters using Verilog Behavioral description
a) Gray to binary and viceversa b) Binary to excess3 and vice versa.
Design of 4 bit binary to gray converter
Theory: Binary to Gray converter:
The logical circuit which converts binary code to equivalent gray code is known as binary to gray code
converter. The gray code is a non-weighted code. The successive gray code differs in one bit position only
that means it is a unit distance code. It is also referred as cyclic code. It is not suitable for arithmetic
operations. It is the most popular of the unit distance codes. It is also are flective code. Ann-bit Gray code
can be obtained by reflecting an n-1 bit code about an axis after 2n-1
rows, and putting the MSB of 0 above
the axis and the MSB of 1 below the axis. Reflection of Gray code shown below. The 4 bits binary to gray
code conversion table is given below,
BlockDiagram:
b(0) g(0)
b(1) g(1)
b(2)
b(3)
g(2)
g(3)
TruthTable:
DecimalNumber 4-bitBinaryCode 4-bitGrayCode
B3B2B1B0 G3G2G1G0
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
27

CircuitDiagram:BinarytoGray Converter
4-bitbinarytogray converter
VerilogCode:
modulebintogray_4_bit(g,b);
input[3:0] b;
input[3:0] g;
assigng[3]=b[3];
assigng[2]=b[3]^b[2];
endmodule
OutputWaveform:
28

Design ofGray toBinary Code converter:
Theory:
Gray Code system is a binary number system in which every successive pair of numbers differs in only one bit.
It is used in applications in which the normal sequence of binary numbers generated by the hardware may
produce an error or ambiguity during the transition from one number to the next
Block Diagram:
TruthTable:
29

VerilogCode:
modulegtob(input[3:0]g,output[3:0]b); assign
b[3] = g[3];
assignb[2]=g[3]^g[2];
assignb[1]=g[2]^g[1];
assignb[0]=g[1]^g[0]; endmodule
OutputWaveform:
BCDtoExcess-3CodeConverter:
Theory:
The Excess-3 code can be calculated by adding 3, i.e., 0011 to each four-digit BCD code. Below is the
truth table for the conversion of BCD to Excess-3 code. In the below table, the variables A, B, C, and D
represent the bits of the binary numbers. The variable 'D' represents the LSB, and the variable 'A'
representstheMSB.In thesameway, thevariables w, x,y, andzrepresent thebits oftheExcess-3code.
30

Excess-3toBCDConverter:
Theory: It’s quite simple. Suppose our input is 4 bit excess-3 code which we have to convert in 4 bit BCD
code. Keep in mind BCD to Excess-3 conversion and we just have to reverse it’s process like subtracting by 3.
As 4 bit excess-3 code start from 3 and end at 12 (input 0,1,2,13,14,15 not possible for obvious reason). Now
subtract 3 from our excess-3 code. for impossible inputs of 4 bit Excess-3 code we use output as Don’t care
conditions.
32

VerilogCode:
moduleex3_to_bcd(
input w,x,y,z
outputa,b,c,d);
assigna=((w&x)|(w&y&z));
assignb=(((~x)&(~y))|((~x)&(~z))|(x&y&z)); assign c =
(((~y) & z) | (y & (~z)));
assignd=~z;
endmodule
OutputWaveform:
Result:Verified and observe the output of Gray to Binary and Binary to
Gray and Binary to Excess-3 Code converters.
33

8:1 MUX
Expt.No.5: Aim: To realize using Verilog Behavioral description:8:1mux,8:3encoder,Priorityencoder
Apparatus required: - Electronics Design Automation Tools used
 Xilinx14.7 ISE designsuiteSimulatortool
Theory:
An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input selectlines S2 through S0 and
a single output line Y. Depending on the select lines combinations, multiplexer decodes the inputs.
Thebelowfigureshowstheblockdiagramofan8-to-1multiplexerwithenableinputthatenableor disable
the multiplexer. Since the number data bits given to the MUX are eight then 3 bits (23=8) are needed to
select one of the eight data bits.
The truth table for an 8-to1 multiplexer is given below with eight combinations of inputs to
generate each output corresponds to input.
I(0)
I(1)
I(2)
I(3) Y
I(4)
I(5)
I(6)
I(7)
S(2)S(1)S(0)
Fig.a.Block Diagram
S(2) S(1) S(0) Y
0 0 0 I(0)
0 0 1 I(1)
0 1 0 I(2)
0 1 1 I(3)
1 0 0 I(4)
1 0 1 I(5)
1 1 0 I(6)
1 1 1 I(7)
Fig.b.TruthTable
Forexample,ifS2=0,S1=1andS0=0thenthedataoutputYisequalto I2.Similarlythedataoutputsi0 to i7 will be
selected through the combinations of S2, S1 and S0 as shown in above figure.
34

8to 1multiplexerusingcasestatement
VerilogCode:
modulemux8_1(i,sel,y);
input [7:0] i;
input[2:0]sel;
output y;
reg y;
always@(i,sel)
begin
case (sel)
3'b000:y=i[0];
3'b001:y=i[1];
3'b010:y=i[2];
3'b011:y=i[3];
3'b100:y=i[4];
3'b101:y=i[5];
3'b110:y=i[6];
3'b111:y=i[7];
default:y=3'b000
endcase
endmodule
OutputWaveform:
35

8:3EncoderWithout Priority:
THEORY:
An encoder is a combinational logic circuit that essentially performs a“ reverse” of decoder functions. An
encoder has 2^N input lines and N output lines. In encoder the output lines generate the binary code
corresponding to input value. An encoder accepts an active level on one of its inputs, representing digit, such
as a decimal or octal digits, and converts it to a coded output such as BCD or binary. Encoders can also be
devisedtoencodevarioussymbolsandalphabeticcharacters.Theprocessofconvertingfromfamiliarsymbols or
numbers to a coded format is called encoding. An encoder has a number of input lines, only one of which
input is activated at a given time and produces an N-bit output code, depending on which input is activated.
For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2
are: Y0 = I1 + I3 + I5 + I7
Y1=I2+I3+I6+
I7Y2 = I4 + I5 +
I6 +I7
BlockdiagramandTruthTable:
Fig.a.BlockDiagram
En I(7) I(6) I(5) I(4) I(3) I(2) I(1) I(0) Y(2) Y(1) Y(0)
0 x x x x X x x x 0 0 0
1 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1 0 0 0 1
1 0 0 0 0 0 1 0 0 0 1 0
1 0 0 0 0 1 0 0 0 0 1 1
1 0 0 0 1 0 0 0 0 1 0 0
1 0 0 1 0 0 0 0 0 1 0 1
1 0 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 0 1 1 1
Fig.b.TruthTable
8to3 encoder without priority (behaviouralmodel) Verilog
Code:
moduleencoder(input[7:0]a,inputen,outputreg[2:0]y);
always@(en,a)
if(en==1)
case(a)
36

8'b10000000:y=3'b111;
8'b01000000:y=3'b110;
8'b00100000:y=3'b101;
8'b00010000:y=3'b100;
8'b00001000:y=3'b011;
8'b00000100:y=3'b010;
8'b00000010:y=3'b001;
8'b00000001:y=3'b000;
default:y=3'bxxx; endcase
else
y=3'bzzz;
endmodule
Output Waveform:
37

8to3encoderwith priority(behavioural model)
Fig.a.Block Diagram
En I(7) I(6) I(5) I(4) I(3) I(2) I(1) I(0) Y(2) Y(1) Y(0)
0 x x x X x x x x 0 0 0
1 x x x X x x x 1 0 0 0
1 x x x X x x 1 0 0 0 1
1 X x x X x 1 0 0 0 1 0
1 x x x X 1 0 0 0 0 1 1
1 x x x 1 0 0 0 0 1 0 0
1 x x 1 0 0 0 0 0 1 0 1
1 x 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 0 1 1 1
Fig.b.TruthTable
VerilogCode:
moduleencwithpriority(input[7:0]a, input
en,
outputreg[2:0]y);
always@(en,a)
if(en==1)
casex(a)
8'b1xxxxxxx:y=3'b111;
8'b01xxxxxx:y=3'b110;
8'b001xxxxx:y=3'b101;
8'b0001xxxx:y=3'b100;
8'b00001xxx:y=3'b011;
8'b000001xx:y=3'b010;
8'b0000001x:y=3'b001;
8'b00000001:y=3'b000;
default:y=3'bxxx;
endcase
else
y=3'bzzz;
endmodule
38

OutputWaveform:
Result: Verified the output of8:1MUX,8:3 Encoder andPriority encoder.
39

Expt.N0.6
Aim: To realize using behavioral description 1:8Demux, 3:8Decoder, 2-bitComparator
1:8 Demux
Theory: A 1 to 8 demultiplexer consists of one input line, 8 output lines and 3 select lines. Let the
input be D, S1andS2 are two select lines and eight outputs from Y0 toY7.It is also called as 3to8
demux because of the 3 selection lines. Below is the block diagram of 1 to 8 demux.
Fig.Block Diagram
TruthTable:
VerilogCode:
moduledemux(y,s,d);
input d;
input [2:0]s;
outputreg[7:0]y;
always @(d,s)
begin
40

case(s)
3'b000: y[0]=d;
3'b001: y[1]=d;
3'b010: y[2]=d;
3'b011: y[3]=d;
3'b100: y[4]=d;
3'b101: y[5]=d;
3'b110: y[6]=d;
3'b111: y[7]=d;
endcase
end
endmodule
OutputWaveform:
3:8 Decoder
Theory: Decoder is a combinational logic circuit that is used to change the code into a set of signals. It is
the reverse process of an encoder. A decoder circuit takes multiple inputs and gives multiple outputs. A decoder
circuit takes binary data of ‘n’ inputs into ‘2^n’ unique output. In addition to input pins, the decoder has a
enable pin.This enables the pin when negated, to make the circuit inactive in this article, we discuss 3 to 8 line
Decoder and demultiplexer.
41

Fig.3:8DecoderBlock Diagram
TruthTable:
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Verilog Code:
moduledecoder3_to_8(y,d);
input [2:0] d;
outputreg[7:0]y;
always@(d)
begin
y=0;
case(d)
3'b000: y[0]=1'b1;
3'b001: y[1]=1'b1;
3'b010: y[2]=1'b1;
3'b011: y[3]=1'b1;
3'b100: y[4]=1'b1;
3'b101: y[5]=1'b1;
3'b110: y[6]=1'b1;
3'b111: y[7]=1'b1;
default:y=8'b0;
endcase
end
endmodule
42

OutputWaveform:
2-Bit Comparator:
Theory:2-bit Comparator is a combinational circuit used to compare two binary number consist input
of two bits. When two binary numbers A & B are compared the output can be any of these three cases
i.e. A > B, A = B and A < B.
VerilogCode:
moduletwobit(agb,aeb,alb,a,b);
input [1:0] a,b;
outputregagb,aeb,alb;
always @(a or b)begin
agb=0;
aeb=0;
alb=0;
if(a==b)
aeb=1;
elseif(a>b)
agb=1;else
alb=1;
end
endmodule
43

OutputWaveform:
Result: Verified and observe the output of1:8Demux, 3:8Decoder and 2-Bit Comparator.
44

SR Flipflop
Expt.No.7
Aim: Write Verilog code for SR,D and JK and verify the flip flop.
Theory: flip-flop(FF) is predominately controlled by a clock and its output state is determined by its
excitation input signals. Note that if the clock is replaced by a gated control signal, the flip-flop
becomes a gated latch.
SR Flipflop:
The major problem of RS latch is its susceptibility to voltage noise which could change the output
states of the FF. With the clocked RSFF, the problem is remedied. With the clock held low,[S]&[R]
held low, the output remains unchanged. With the clock held high, the output follows R & S.
set
clk
R
S Q
Qbar
clr
Fig.a.BlockDiagram
TruthTable:
Inputs Outputs
clk Clr Set S R Q Qbar
X X X X NC
1 X X X 0 1
0 1 X X 1 0
0 0 0 0 NC
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 Not Defined
VerilogCode:
modulesrff(q,qbar,set,clr,s,r,clk);
input set,clr,s,r,clk;
outputq,qbar;
reg q,qbar;
45

always@ (posedgeclk,posedgeset,posedgeclr)
46

begin
if (clr)
q=1’b0;
elseif(set)
q=1’b1;
else
begin
case({s,r)}
2’b00:q=q;
2’b01:q=0;
2’b10:q=1;
2’b11:q=1’bz;
endcase
end
qbar=~q;
end
endmodule
OutputWaveform:
47

DFlip-Flop
DFlip-Flop:
The D-type FF remedies the indeterminate state problem that exists when both inputs to a clocked
RSFF are high. The schematic is identical to a RSFFexcept that an inverter is used to produce a pair
of complementary input.
D Q
Clk Qbar
Fig.a Block Diagram
TruthTable:
Clk D Q Qbar
0 0 No Change No Change
0 0 1
1 1 0
VerilogCode:
moduledff(q,qbar,set,clr,d,clk);
input set,clr,d,clk;
outputq,qbar;
reg q,qbar;
always@(posedgeclk,posedgeset,posedgeclr)
begin
if (clr)
q=1’b0;
elseif(set)
q=1’b1;
elsebegin
case({d)}
2’b00:q=q;
2’b01:q=0;
2’b10:q=1;
48

2’b11:q=1’bz;
endcase
end
qbar=~q;
end
endmodule
OutputWaveform:
JKFlip-Flop:
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or
invalid output condition that can occur when both inputs S and R are equal to logiclevel“1”.Due to this additional clocked
input, a JKflip-flop has four possibleinput combinations, “logic 1”,“logic0”, “no change” and “toggle”. The symbol for a
JK flip flop is similar to that of an SR Bistable Latchas seen in the previous tutorial except for the addition of a clock
input.
49

VerilogCode:
modulejkff(q,qbar,set,clr,j,k,clk);
input set,clr,j,k,clk;
outputq,qbar;
reg q,qbar;
always@(posedgeclk,posedgeset,posedgeclr)
begin
if (clr)
q=1’b0;
elseif(set)
q=1’b1;
else
begin
case({j,k)}
2’b00:q=q;
2’b01:q=0;
2’b10:q=1;
2’b11:q=1’bz;
endcase
end
qbar=~q;
end
endmodule
OutputWaveform:
50

BCDCounter
Aim: To realize counters Up/Down (BCD and Binary) using Verilog behavioral description.
Apparatus required:-ElectronicsDesignAutomationToolsused:-XilinxISE14.7Simulatortool
Theory:
The counters which use clock signal to change the transition are called“Synchronouscounters”.This
means the synchronous counters depends on the clock input to changes values. In synchronous counters, all
flip flops are connected to the same clock signal and all flip flops will trigger at the same time. Synchronous
counters are also known as ‘Simultaneous counters ’.There is no propagation delay and no ripple effect in
synchronous counters.
Logic Symbol:
Clk
q
Clr
TruthTable:
Clk Clr Q
1 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
51

0 1001
VerilogCode:
BCDUp counter
modulebcdcounter(bcddigit,clk,rst);
input clk, rst;
outputreg[3:0]bcddigit=0;
always @(posedge clk)
begin
if((rst==1)|(bcddigit==4'b1001))
begin
bcddigit=4'b0000;
end
else
bcddigit=bcddigit+1;
end
endmodule
OutputWaveform:
52

BCDDown Counter:
VerilogCode:
modulebcdcounter(bcddigit,clk,rst);
input clk, rst;
outputreg[3:0]bcddigit=4'b1001; always
@(posedge clk)
begin if((rst==1)|
(bcddigit==4'b0)) begin
bcddigit=4'b1001;
end
else
bcddigit=bcddigit-1;
end
endmodule
OutputWaveform:
BinaryUPCounter:
modulebinarycounter1(binarydigit,clk,rst);
input clk, rst;
outputreg[3:0]binarydigit=4'b0000;
begin if((rst==1)|
(binarydigit==4'b1111)) begin
binarydigit=4'b0000;
end
else
binarydigit=binarydigit+1;
53

end
endmodule
OutputWaveforms:
BinaryDown Counter:
modulebinarycounter1(binarydigit,clk,rst);
input clk, rst;
outputreg[3:0]binarydigit=4'b1111;
begin if((rst==1)|
(binarydigit==4'b0000)) begin
binarydigit=4'b1111;
end
else
binarydigit=binarydigit-1;
end
endmodule
54

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