VLSI
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Tevatron Technologies is a private company focused on VLSI design, FPGA-based design, and embedded systems. Their vision is to be an end-to-end provider for electronics system design and manufacturing. The company hosted an industrial training seminar on RTL design, Verilog, and FPGA design. The seminar covered topics like VHDL vs. Verilog, Verilog coding styles, data types, constructs, RTL coding guidelines, and FPGA architecture. VLSI allows integrating millions of electronic components on a small chip area and is used for applications like processors, memory, and specialized chips.
VLSI
- 1. TEVATRON TECHNOLOGIES PVT LTD Submitted by: Mayank Kumar(00614802813) 7E1 Kumar Chandan(00814802813) 7E1 A Industrial Training Seminar on RTL Design, Verilog and FPGA design at
- 2. Tevatron Technologies(A registered private limited company under Ministry of Corporate Affairs, Govt. of India) is a Design and Product Company focused on VLSI Design, FPGA Based Design & Embedded Systems and nurturing the ecosystem for the same. Company Vision n Tevatron Technologies Vision is to be an end-to-end provider of ESDM( Electronics Systems Design and Manufacturing) and IoT including concept to prototype; prototype to product development, in the process also transforming the technology delivery landscape and the ecosystem.
- 3. Unique PS2 Based Approach:
- 4. VLSI introduction : Objectives introduction : AVLSI (Very Large Scale Integration) system integrates millions of “electronic components” in a small area (few mm2 few cm2). Objectives: design “efficient”VLSI systems that has: • Circuit Speed (high ) • Power consumption ( low ) • Design Area ( low )
- 5. Vlsi design flow 1. idea (need) 2. specifications 3. design architecture 4. RTL coding 5. RTLVerification6. Synthesis7.Foundry8.IC Chip
- 6. VHDL VERILOG Not case sensitive. Difficult to learn. Based on pascal & ada. Case sensitive. Easy to learn. Based on c. HDL – Hardware Description Language ƒ A programming language that can describe the functionality and timing of the hardware. Types of HDL • VHDL (VHSIC Hardware Description Language) • VERILOG • SYSTEMVERILOG Difference
- 7. Style of modeling 1.Data flow -if designer is concern about flow of data in design, concurrent statement is used here. 2.Behavioral - if designer is not concern about h/w and flow of data rather concerned about the functionality of designing 3.gate -if designer is concerned about h/w. 4. Switch level - it is transistor level of modeling used in analog mixed signal(AMS)’ Basic Verilog HDL Code
- 8. Data types in Verilog 1.Register: can store value 1. Reg 2.Integer 3.Real 4.Time 2. Net: can’t store value 1. wire 2. wand 3. wor 4. triac
- 9. Construct Types 1. Synthesizable 1. Can get h/w here 2. Non synthesizable Can’t get h/w *for verification purpose, synthesizable or non synthesizable both can be used.
- 10. Verilog Methods 1. Task: a) specific job again and again over certain period b)May or may not have any input argument c)May contain delay, waiting or event control statement. 2. Function: a) specific job again and again over any period b)Should have atleast one input argument c)Should not contain delay, waiting or event control statement *Task and function are synthesizable construct.
- 11. RTL coding guidelines Always use non-blocking assignment statement to model sequential logic. Always use blocking assignment statement to model combinational logic. Use NBA statement to model latches. For mixing of combinational and sequential use NBA. Use separate always block for for different signals. Use $strobe to check final value of signal.
- 12. Dual port ram
- 13. Serial in serial out register
- 14. counter
- 15. System Task System tasks are available to handle simple I/O and various design measurement functions during simulation. All system tasks are prefixed with $ to distinguish them from user tasks and functions. $display - Print to screen a line followed by an automatic newline. $write - Write to screen a line without the newline. $swrite - Print to variable a line without the newline. $sscanf - Read from variable a format-specified string. (*Verilog-2001) $fopen - Open a handle to a file (read or write) $fdisplay - Write to file a line followed by an automatic newline. $fwrite - Write to file a line without the newline. $fscanf - Read from file a format-specified string. (*Verilog-2001) $fclose - Close and release an open file handle.
- 16. F0RK/JOIN The fork/join pair are used by Verilog to create parallel processes. All statements (or blocks) between a fork/join pair begin execution simultaneously upon execution flow hitting the fork. Execution continues after the join upon completion of the longest running statement or block between the fork and join.
- 17. VLSI Applications VLSI is an implementation technology for electronic circuitry - analogue or digital It is concerned with forming a pattern of interconnected switches and gates on the surface of a crystal of semiconductor Microprocessors personal computers microcontrollers Memory - DRAM / SRAM Special Purpose Processors - ASICS (CD players, DSP applications) Optical Switches Has made highly sophisticated control systems mass-producable and therefore cheap
- 18. BlockRAMs BlockRAMs Configurable Logic Blocks I/O Blocks What is an FPGA? Block RAMs The FPGA is an integrated circuit that contains many (64 to over 10,000) identical logic cells that can be viewed as standard components. Each logic cell can independently take on any one of a limited set of personalities. The individual cells are interconnected by a matrix of wires and programmable switches. A user's design is implemented by specifying the simple logic function for each cell and selectively closing the switches in the interconnect matrix. The array of logic cells and interconnect form a fabric of basic building blocks for logic circuits. Complex designs are created by combining these basic blocks to create the desired circuit. A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), FPGAs can be used to implement any logical function that an ASIC could perform. Implementation includes many phases Translate : Merge multiple design files into a single netlist Map : Group Logical symbols from the netlist (Gates) into physical components (CLB s and IOBs ) Place & Route : Place components onto the chip, connect them and extracts timing data into reports Timing (Sim) : Generate a back annotated netlist for timing simulation tools Configure : Generate a bit stream for device configuration
- 19. Vlsi is suitabale for fabrication of larger number of components on a single chip. VHDL/VERILOG is used for digital circuit designing and to validate the design and check the design specification. CONCLUSION