Embedded system

What is an Embedded System An Embedded System is a microprocessor based system that is embedded as a subsystem, in a larger system (which may or may not be a computer system).OI

Application areasAutomotive electronicsAircraft electronicsTrainsTelecommunication

Design challenge optimizing design metricsObvious design goal:Construct an implementation with desired functionalityKey design challenge:Simultaneously optimize numerous design metricsDesign metric A measurable feature of a system’s implementationOptimizing design metrics is a key challenge

Common metricsUnit cost: the monetary cost of manufacturing each copy of the system, excluding NRE costNRE cost (Non-Recurring Engineering cost): The one-time monetary cost of designing the systemSize: the physical space required by the systemPerformance: the execution time or throughput of the systemPower: the amount of power consumed by the systemFlexibility: the ability to change the functionality of the system without incurring heavy NRE costDesign challenge optimizing design metrics

IC technologyThree types of IC technologiesFull-custom/VLSISemi-custom ASIC (gate array and standard cell)PLD (Programmable Logic Device)

Full-custom/VLSIAll layers are optimized for an embedded system’s particular digital implementationPlacing transistorsSizing transistorsRouting wiresBenefitsExcellent performance, small size, low powerDrawbacksHigh NRE cost (e.g., $300k), long time-to-market

Semi-customLower layers are fully or partially builtDesigners are left with routing of wires and maybe placing some blocksBenefitsGood performance, good size, less NRE cost than a full-custom implementation (perhaps $10k to $100k)DrawbacksStill require weeks to months to develop

PLD (Programmable Logic Device)All layers already existDesigners can purchase an ICConnections on the IC are either created or destroyed to implement desired functionalityField-Programmable Gate Array (FPGA) very popularBenefitsLow NRE costs, almost instant IC availabilityDrawbacksBigger, expensive (perhaps $30 per unit), power hungry, slower

FPGAOTP One time ProgrammedMTP Multi-Time Programmed

CMOS transistor on siliconsourcegateConductsif gate=1drain1gateoxideIC packageIC sourcechanneldrainSilicon substrateTransistorThe basic electrical component in digital systemsActs as an on/off switchVoltage at “gate” controls whether current flows from source to drainDon’t confuse this “gate” with a logic gate

CMOS transistor implementationssourcesourcegateConductsif gate=0gateConductsif gate=1draindrainpMOSnMOS111xxyxF = x'yF = (xy)'xF = (x+y)'y0xy00NOR gateinverterNAND gateComplementary Metal Oxide SemiconductorWe refer to logic levelsTypically 0 is 0V, 1 is 5VTwo basic CMOS typesnMOS conducts if gate=1pMOS conducts if gate=0Hence “complementary”Basic gatesInverter, NAND, NOR

Basic logic gatesxxFFxxFxFyxFxyxyxyxyxyxyFFFFFFy0001Fy0000000000010010011110010011011010011010100101101100101100111111110111110110xxxFxFFFyyyF = x yXNORF = x yANDF = x  yXORF = xDriverF = x + yORF = (x y)’NANDF = x’InverterF = (x+y)’NOR

What is VHDL?A very verbose, complex, and powerful language for design, simulation, verification and synthesis of digital systemsSupports many levels of abstraction, ranging from algorithm level to gate levelCan model concurrentand sequential behaviors of digital systemsSupports design hierarchy as interconnections of componentsCan explicitly model the timing of digital systems

What is VHDL?Just as high-level programming languages allow complex design concepts to be expressed as computer programs, VHDL allows the behavior of complex electronic circuits to be captured into a design system for automatic circuit synthesis or for system simulation. Like Pascal, C and C++, VHDL includes features useful for structured design techniques, and offers a rich set of control and data representation features. Unlike these other programming languages, VHDL provides features allowing concurrent events to be described. This is important because the hardware described using VHDL is inherently concurrent in its operation.

History of VHDL 1980: The USA department of defense (DOD) wanted to make circuit design self documenting. 1983: The development of VHDL began with a joint effort by IBM, Texas Instruments and Inter-metrics. 1987: The institute of Electrical and Electronics Engineers (IEEE) was presented with a proposal to standardize the language. The resulting standard, IEEE 1076-1987, is the basis for virtually every simulation and synthesis product sold today. 1993: The VHDL language was revised to IEEE 1076-1993 1996: A VHDL package for use with synthesis tools become part of the IEEE 1076 standard, specifically it is 1076.3. This greatly improved the portability of designs between different synthesis vendor tools. Another part of the standard, IEEE 1076.4 (VITAL), has been completed and sets a new standard for modeling ASIC and FPGA libraries in VHDL. This made life considerably easier for ASIC, FPGA and EDA tools vendors.

VerilogVerilog was introduced first before VHDL, thus established itself as the de facto standard language for ASIC simulation libraries; Verilog has some advantage in availability of simulation models. Another important feature that is defined in Verilog is a programming language interface PLI. The PLI makes it possible for simluation model writers to go outside of Verilog when necessary to create faster simulation models, or to create functions (using the C language) that would be difficult or inefficient to implement directly in Verilog.

History of Verilog1981: A CAE (Computer Aided Engineering) software company called Gateway Design Automation was founded by PrabhuGoel. 1983: Gateway released the Verilog hardware description language known as “Verilog HDL” together with a Verilog simulator. 1985: The language and simulator has enhanced; the new version of the simulator was called “Verilog-XL”. 1987: Verilog-XL was becoming very popular and has been used by many ASIC vendors. Another start-up company, Synopsys, began to use the proprietary Verilog behavioral language as an input to their synthesis product. 1989: Cadence bought Gateway. 1995: The Verilog language was reviewed and adopted by IEEE as IEEE standard 1364.

VHDLVHDL is a programming language that allows one to model and develop complex digital systems in a dynamic environment.3 ways to DO IT -- the VHDL wayGeometricFunctional (Behavioral)Structural

Let’s Write a VHDL Model ...ENTITY full_adder ISPORT ( A, B, Cin : IN BIT; Sum, Cout : OUT BIT );END full_adder;Can we build the Full Adder’s architecture using these gates?

Full Adder Architecturefor Cout (I.e. Carry Out):Cin (I.e. Carry In)A B010 0000 1011 1111 001for Sum:Cin (I.e. Carry In):SUMA B01CIN0 0010 110ACOUT1 1011 010B

Two Full Adder ProcessesSummation:PROCESS( A, B, Cin)BEGIN Sum <= A XOR B XOR Cin;END PROCESS Summation;Carry:PROCESS( A, B, Cin)BEGIN Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin);END PROCESS Carry;

Full AdderCINentityFull_Adderisport (A, B,CIN: in BIT; SUM, COUT: out BIT);endFull_Adder;architectureFull_AdderofFull_Adderisbegin SUM <= A xor B xor CIN after 15ns; COUT <= (A and B) or (B and CIN) or (CIN and A) after 10ns;endFull_Adder;SUMFull_AdderABCOUT

Basic Design MethodologyRequirementsSimulateRTL ModelSynthesizeGate-levelModelSimulateTest BenchASIC or FPGAPlace & RouteTimingModelSimulate

Design FlowReading preliminary Specs. From CustomerDefine the full definition of the problemDetailed specification and architecture of the design.Detailed test structure for Specs. And Architecture.Design S.W. to prove the idea “C, Matlab, …” (Emulation)Top-Down Design “HDL, FSM, Flowchart,…”Functional simulationLogic synthesis: analysisPlace and routeReal timing optimizationDownload design on the FPGAHardware testing.

Embedded system

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Embedded system