![Conti…
• Input Declaration
• Scalar
• input list of input identifiers;
• Example: input A, B, C_in;
• Vector
• input[range] list of input identifiers;
• Example: input[15:0] A, B, data;
• Output Declaration
• Scalar Example: output c_out, OV, MINUS;
• Vector Example: output[7:0] ACC, REG_IN,
data_out](https://image.slidesharecdn.com/verilog-150323145657-conversion-gate01/85/Verilog-14-320.jpg)
Verilog
- 1. VERILOG -Presented by Name-Devanshu Jaiswal Ajay Kumar Garg Engineering College
- 2. Contents • Introduction • Design process • HDL • History • Verilog • Elements of verilog • Design representation -Multiplexer -Adder
- 3. Introduction • Integrated circuits are the combination of millions of transistor embedded on a silicon chip. • Designing of these circuits are very complex. • Designing is divided into various abstraction levels. • Abstraction levels are -Silicon level -Transistor level -Gate level
- 4. -Architectural level -System level Silicon level Gate level Architectural level System level
- 5. Design process Required product Define specifications Initial design Simulation Design correct Redesign no yes Prototype implementation
- 6. What is HDL? • Hardware Description Language describes the hardware of digital systems in textual form. • One can design any hardware at any level. • Simulation of designs before fabrication. • With the advent of VLSI, it is not possible to verify a complex design with millions of gates on a breadboard, HDLs came into existence to verify the functionality of these circuits.
- 7. • Have special hardware related constructs. • Currently models digital system and limited analog system, and in future can model complete mixed signal systems also . • It is used to build models for simulation, synthesis and test. • Unlike a program executes serial, HDL executes concurrently that is parallelism is followed. • It has special construct for modelling delays.
- 8. HDL History • 1970s: First HDLs • Late 1970s: VHDL – VHDL = VHSIC HDL = Very High Speed Integrated Circuit HDL – VHDL inspired by programming languages of the day (Ada) • 1980s: – Verilog first introduced – Verilog inspired by the C programming language – VHDL standardized • 1990s: – Verilog standardized (Verilog-1995 standard) • 2000s: – Continued evolution (Verilog-2001 standard) • Both VHDL and Verilog evolving, still in use today
- 9. What is Verilog ? • Verilog is a hardware description language. • Verilog HDL is commonly used in the US industry. Major digital design companies in Pakistan use Verilog HDL as their primary choice. • Most commonly used in the design, verification, and implementation of digital logic chips.
- 10. Verilog simulator There are many logic simulators used for Verilog HDL. Most common are: –Xilinx –Veriwell –Model Sim For Beginners Veriwell is good choice and is very user friendly. Xilinx and ModelSim are widely used.
- 11. Elements of verilog- data type • Nets – Nets are physical connections between devices – Many types of nets, but all we care about is wire. • Registers – Implicit storage-holds its value until a new value is assigned to it. – Register type is denoted by reg. • Parameters are not variables, they are constants.
- 12. keywords • Note : All keywords are defined in lower case • Examples : • module, endmodule • input, output, inout • reg, integer, real, time • not, and, nand, or, nor, xor • parameter • begin, end • fork, join • specify, endspecify
- 13. Keyword description • module – fundamental building block for Verilog designs • Used to construct design hierarchy • Cannot be nested • endmodule – ends a module – not a statement => no “;” • Module Declaration • module module_name (module_port, module_port, …); • Example: module full_adder (A, B, c_in, c_out, S);
- 14. Conti… • Input Declaration • Scalar • input list of input identifiers; • Example: input A, B, C_in; • Vector • input[range] list of input identifiers; • Example: input[15:0] A, B, data; • Output Declaration • Scalar Example: output c_out, OV, MINUS; • Vector Example: output[7:0] ACC, REG_IN, data_out
- 15. Design representation • Example-1:Multiplexer Multiplexer: Choose one of the two inputs based on a control input. Sel: Select line is a control input. A,B: Data inputs. Out: Multiplexer output. MUX A B Sel Out
- 16. Verilog description module multiplexer(A, B, S, Out); input A,B,S; output Out; wire tmp0,tmp1; and (tmp1,B,S); not (selbar,S); and (tmp0,A,selbar); or (Out,tmp0,tmp1); Tmp1 tmp0 selbar Out
- 17. Example 2: Half Adder module half_adder(S, C, A, B); output (S, C); input (A, B); wire (S, C, A, B); xor (S,A,B); And (A,B); endmodule
- 18. Thank you!