15. Where is the problem?
• System specification is behavioral
• Manual Translation of design in Boolean
equations
• Handling of large Complex Designs
• Can we still use SPICE for simulating Digital
circuits?
18. History:
• Need: a simple, intuitive and effective way of
describing digital circuits for modeling,
simulation and analysis.
• Developed in 1984-85 by Philip Moorby
• In 1990 Cadence opened the language to the
public
• Standardization of language by IEEE in 1995
22. Definition of Module
• Interface: port and
parameter declaration
• Body: Internal part of
module
• Add-ons (optional)
23. Some points to remember
• The name of Module
• Comments in Verilog
– One line comment (// ………….)
– Block Comment (/*…………….*/)
• Description of Module (optional but
suggested)
39. Test Bench
module main;
reg a, b, c;
wire sum, carry;
fulladder add(a,b,c,sum,carry);
initial
begin
a = 0; b = 0; c = 0;
#5
a = 0; b = 1; c = 0;
#5
a = 1; b = 0; c = 1;
#5
a = 1; b = 1; c = 1;
#5
end
endmodule
40. Memory Operation
reg [31:0] register_file [0:7];
wire [31:0] rf_bus;
wire r2b4;
assign rf_bus = register_file [2];
assign r2b4 = rf_bus[4];
Can’t use register_file[2][4] for assigning value to
variable r2b4
41. Some main points to remember
• Verilog is concurrent
• Think while writing your program.
• Blocking and Non-blocking Code
![Memory Operation
reg [31:0] register_file [0:7];
wire [31:0] rf_bus;
wire r2b4;
assign rf_bus = register_file [2];
assign r2b4 = rf_bus[4];
Can’t use register_file[2][4] for assigning value to
variable r2b4](https://image.slidesharecdn.com/fpaavlsi-250707092208-4d911cb7/85/System-specification-is-behavioral-Manual-Translation-of-design-in-Boolean-equations-FPAA-vlsi-ppt-40-320.jpg)
