Verilog codes and testbench codes for basic digital electronic circuits.

1.Fulladder
----------------------------------------------
`timescale 1ns/1ps
module fulladder(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
//wire w1,w2,w3,w4;
//xor(w1,a,b);
//xor(s,w1,cin);
//and(w2,a,b);
//and(w3,b,cin);
//and(w4,cin,a);
//or(cout,w1,w2,w3);
wire w1,w2,w3;
xor(s,a,b,cin);
and(w1,a,b);
and(w2,b,cin);
and(w3,cin,a);
or(cout,w1,w2,w3);
endmodule
--------------------------
testbench code:-
-----------------------------------------
`timescale 1ns/1ps
module test_fulladder();
reg a,b,cin;
wire s,cout;
fulladder DUT(.a(a),.b(b),.cin(cin),.s(s),.cout(cou
t));
initial begin
$monitor("a=%b b=%b cin=%b s=%b cout=%b",a,b,c
in,s,cout);
end
initial begin
a=1'b0;
b=1'b0;
cin=1'b0;
#6
a=1'b1;
b=1'b0;

cin=1'b0;
#6
a=1'b0;
b=1'b1;
cin=1'b1;
#6
a=1'b0;
b=1'b1;
cin=1'b0;
#6
a=1'b1;
b=1'b1;
cin=1'b1;
end
endmodule
---------------------------------------
2.Fulladder using half adders:
------------------------------
`timescale 1ns/1ps
module ha(a,b,s,c);
input a,b;
output reg s,c;
always@(*)
begin
s=a^b;
c=a&b;
end
endmodule
module fulladd(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire s1,c1,c2;
ha h1(a,b,s1,c1);
ha h2(s1,cin,s,c2);
or(cout,c2,c1);
endmodule

test bench code:
----------------------
`timescale 1ns/1ps
module test();
reg a,b,cin;
wire s,cout;
fulladd h(a,b,cin,s,cout);
initial begin
$monitor("a=%b b=%b cin=%b s=%b cout=%b ",a,b,cin,
s,cout);
end
initial begin
a=1'b0;
b=1'b0;
cin=1'b1;
#5
a=1'b1;
b=1'b0;
cin=1'b1;
#5
a=1'b1;
b=1'b1;
cin=1'b1;
end
endmodule
-------------------------------
3.Ripple Carry Adder:-
---------------------------------------------------
-----
`timescale 1ns/1ps
module fa(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
reg s,cout;
always@(a or b or cin)
begin
s=(a^b)^cin;
cout=(a&b)+(b&cin)+(a&cin);

end
endmodule
module rca(x,y,cin,s,cout);
input cin;
input[3:0]x,y;
output [3:0]s;
output cout;
wire[3:1]c;
fa stage0(x[0],y[0],cin,s[0],c[1]);
fa stage1(x[1],y[1],c[1],s[1],c[2]);
fa stage2(x[2],y[2],c[2],s[2],c[3]);
fa stage3(x[3],y[3],c[3],s[3],cout);
endmodule
~
---------------------------------------------------
---
testbench code:
`timescale 1ns/1ps
module test_rca();
reg cin;
reg[3:0]x,y;
wire cout;
wire[3:0]s;
rca pujari(x,y,cin,s,cout);
initial begin
$display("THE INPUT AND OUTPUTS ARE:");
$monitor("x=%b y=%b s=%b cout=%b",x,y,cin,s,cout
);
end
initial begin
cin=1'b0;
x=4'b0000;
y=4'b1010;
#5
x=4'b1111;
y=4'b1010;
#5
x=4'b0011;
y=4'b1110;

#5
x=4'b0001;
y=4'b0011;
end
endmodule
---------------------------------------------------
-------------
4.16x1 MUX using 4x1 MUX
-------------------------------------
`timescale 1ns/1ps
module mux16(w,s16,f);
input[0:15]w;
input[3:0]s16;
output f;
reg f;
always@(w or s16)
case(s16[3:2])
0:mux4(w[0:3],s16[1:0],f);
1:mux4(w[4:7],s16[1:0],f);
2:mux4(w[8:11],s16[1:0],f);
3:mux4(w[12:15],s16[1:0],f);
endcase
task mux4;
input [0:3]x;
input [1:0]s4;
output g;
reg g;
case(s4)
0:g=x[0];
1:g=x[1];
2:g=x[2];
3:g=x[3];
endcase
endtask
endmodule
---------------------------------------------------
----------

Test_bench code:
`timescale 1ns/1ps
module test();
reg [0:15]w;
reg[3:0]s16;
wire f;
mux16 shobhan(w,s16,f);
initial begin
$monitor("w=%b s16=%b f=%b",w,s16,f);
end
initial begin
w=16'b1011111110110001;
s16=4'b1100;
#9
w=16'b1010110110110001;
s16=4'b1101;
#9
w=16'b111110110110001;
s16=4'b0011;
#9
w=16'b101010110110111;
s16=4'b1111;
end
endmodule
---------------------------------------------
5.Ripple Carry Adder:-
---------------------------------------------------
-----
`timescale 1ns/1ps
module fa(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
reg s,cout;
always@(a or b or cin)
begin
s=(a^b)^cin;
cout=(a&b)+(b&cin)+(a&cin);

#5
x=4'b0001;
y=4'b0011;
end
endmodule
---------------------------------------------------
-------------
6.1).decoder:-
`timescale 1ns/1ps
module encoder(w,en,y);
input[1:0]w;
input en;
output [3:0]y;
wire p0,p1;
reg [3:0]y;
not(p0,w[0]);
not(p1,w[1]);
always@(w or en)
begin
if(en)
case(w)
2’b00: y<= 4’b1110;
2’b01: y<= 4’b1101;
2’b10: y<= 4’b1011;
2’b11: y<= 4’b0111;
endcase;
else
y=0;
end
endmodule
---------------------------------------------------

----------------
test bench:-
`timescale 1ns/1ps
module test();
reg [0:1]w;
reg en;
wire [0:3]y;
encoder shobhan(w,en,y);
initial begin
$monitor("w=%b en=%b y=%b",w,en,y);
end
initial begin
w=2'b00;
en=1'b1;
#5
w=2'b01;
en=1'b1;
#5
w=2'b10;
en=1'b1;
#5
w=2'b11;
en=1'b1;
#5
w=2'b10;
en=1'b0;
#5
w=2'b11;
en=1'b0;
end
endmodule
---------------------------------------------------
--------------
2).4x1 mux using 2x1
---------------------------------------------------
--------------
`timescale 1ns/1ps
module mux2(c,s,z);
input[0:3]c;
input[1:0]s;

output z;
reg z;
always@(c or s)
case(s[1])
0:mux(c[0:1],s[0],z);
1:mux(c[2:3],s[0],z);
endcase
task mux;
input[0:1]x;
input l;
output g;
reg g;
case(l)
0:g=x[0];
1:g=x[1];
endcase
endtask
endmodule
---------------------------------------------------
--------------
testbench code:-
`timescale 1ns/1ps
module test();
reg [0:3]i;
reg [1:0]s;
wire y;
mux2 shobhan(i,s,y);
initial begin
$monitor("i=%b s=%b y=%b",i,s,y);
end
initial begin
i=4'b1000;
s=2'b10;
#5
i=4'b1011;
s=2'b00;
#5

i=4'b1111;
s=2'b01;
#5
i=4'b1010;
s=2'b11;
end
endmodule
---------------------------------------------------
----------
8.Mealy State Machine:-
---------------------------------------------------
--------
`timescale 1ns/1ps
module mealy(i,z,clk,rst);
input i,clk,rst;
output z;
reg z;
reg[1:0]state,nextstate;
parameter s0=2'b00;
parameter s1=2'b01;
parameter s2=2'b10;
always@(posedge clk,posedge rst)
if(rst)
begin
state=s0;
z=0;
end
else begin
state=nextstate;
z=0;
end
always@(*)
case(state)
2'b00:
begin
if(i)
begin nextstate=s0;z=0;end
else

begin nextstate=s1;z=0;end
end
2'b01:begin
if(i) begin nextstate=s2;z=0;end
else begin nextstate=s1;z=0;end
end
2'b10:begin
if(i) begin nextstate=s0;z=0;end
else begin nextstate=s1;z=1;end
end
default :begin nextstate=s0;z=0;end
endcase
endmodule
-------------------------------------------------
`timescale 1ns/1ps
module test();
reg clk, rst, i;
wire z;
reg[15:0] seq;
integer j;
moore shobhan(i,z,clk,rst);
initial
begin`
clk = 0;
rst = 1;
seq = 16'b0101_1101_1101_0010;
#5 rst = 0;
for( j = 0; j <= 15; j = j + 1)
begin
i = seq[j];
#2 clk = 1;
#2 clk = 0;
$display("State =",shobhan.state,"Input = ",i,",Out
put= ", z);
end
test2;
end
task test2;
for( j = 0; j <= 15; j = j + 1)
begin
i = $random % 2;

#2 clk = 1;
#2 clk = 0;
$display("State =",shobhan.state,"Input =",i,",Out
put= ",z);
end
endtask
endmodule
---------------------------------------------------
--
9.Counter
---------------------------------------------------
--
module counter(
input clk,rst,enable,
output reg [3:0]counter_output
);
always@ (posedge clk)
begin
if( rst | counter_output==4'b1001)
counter_output <= 4'b0000;
else if(enable)
counter_output <= counter_output + 1;
else
counter_output <= 0;
end
endmodule
always
#50 clk= ~ clk;
initial begin
clk=0;
// Initialize Inputs
rst = 0;
enable = 0;
#100;
rst=0;
enable=1;
#100;

rst=0;
enable=1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

Verilog codes and testbench codes for basic digital electronic circuits.

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Verilog codes and testbench codes for basic digital electronic circuits.