Introduction to VHDL
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This document provides an introduction to VHDL (VHSIC Hardware Description Language). It discusses the history of VHDL and how it is based on ADA. It describes some key elements of VHDL including entities, architectures, components, and instantiation. Entities define the interface, architectures provide the implementation, and components allow for modular hierarchical design. The document also discusses structural modeling in VHDL using components, with examples of how to declare components and instantiate them by mapping ports.
Introduction to VHDL
- 1. Computer Hardware Introduction to VHDL Parham Alvani Amirhossein Sohrabbeig VHDL, Why ? How ? Amirkabir University of Technology Computer & InformationTechnology Engineering Department
- 2. RTL • Data/Control • Data • Control Outline VHDL • History • Elements
- 3. RTL
- 4. Control/Data Partitioning • First step in RT level design. • Data part consists of data components and the bussing structure of the design • Control part is a usually a state machine generating control signals • Control signals control the flow of data in the data part
- 6. Data Part • Interconnection of data components – Registers – Combinational logic units – Register files – Busses (that interconnect them)
- 7. Control Part • Takes control inputs from the data part and external control inputs • Makes decisions as to when and what control signals to issues • Consists of one or more state machines that keep the state of circuit • Makes decisions based on – Current data + current status (Mealy) – Current status (Moore)
- 8. VHDL
- 9. History of VHDL • VHSIC Hardware Description Language • VHSIC (Very High Speed Integrated Circuit) was a 1980s U.S. government program. • Based on ADA
- 10. How to use VHDL ? • ModelSim – Closed Source ☹ – https://www.mentor.com/products/fpga/model/ • GHDL – Open Source ☺ – http://ghdl.free.fr/ – https://github.com/tgingold/ghdl
- 11. VHDL Structural Elements • Entity – Interface • Architecture – Implementation, behavior • Configuration – Structure, hierarchy • Process – Sequential Execution • Package – Components (Modular design), Utilities (data types, constants, subprograms) • Library – Group of compiled units, object code
- 12. Entity • Interface description • No behavior/implementation definition • Linking via port signals – data types – signal width – signal direction entity HALFADDER is port( A,B: in bit; SUM, CARRY: out bit ); end entity HALFADDER; entity ADDER is port( A,B: in integer range 15 to 0; SUM: out integer range 15 to 0; CARRY: out bit ); end ADDER;
- 13. Entity Port Modes • in – signal values are read-only • out – signal values are write-only – multiple drivers • buffer: – similar to out – signal values may be read from inside – only 1 driver • inout: – bidirectional port • Output port modes have to match
- 14. Architecture • Implementation of the design • Always connected with a specific entity – one entity can have several architectures – entity ports are available as signals within the architecture • Contains concurrent statements entity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit ); end HALFADDER; architecture RTL of HALFADDER is begin SUM <= A xor B; CARRY <= A and B; end architecture RTL;
- 15. Structural Model
- 16. Component Declaration • In declarative part of architecture – Can use any name for the components • but better to use the same as entity name
- 17. Component Declaration entity FULLADDER is port (A,B, CARRY_IN: in bit; SUM, CARRY: out bit); end FULLADDER; architecture STRUCT of FULLADDER is component HALFADDER port (X, Y : in bit; SUM, CARRY : out bit); end component; component ORGATE port (X, Y : in bit; RES : out bit); end component; signal W_SUM, W_CARRY1, W_CARRY2 : bit; begin . . . entity HALFADDER is port(X, Y: in bit; SUM, CARRY: out bit); end entity HALFADDER; entity ORGATE is port(X, Y: in bit; RES: out bit); end entity ORGATE;
- 18. Component Instantiation • May need many of each • Instantiation in statement part of architecture (after 'begin') • Wires signals together: – default: positional association
- 19. Component Instantiation architecture STRUCT of FULLADDER is component HALFADDER port (X, Y : in bit; SUM, CARRY : out bit); end component; component ORGATE port (X, Y : in bit; RES : out bit); end component; signal W_SUM, W_CARRY1, W_CARRY2: bit; begin MODULE1: HALFADDER port map( A, B, W_SUM, W_CARRY1 ); MODULE2: HALFADDER port map ( W_SUM, CARRY_IN, SUM, W_CARRY2 ); MODULE3: ORGATE port map ( W_CARRY2, W_CARRY1, CARRY ); end STRUCT;
- 20. Component Instantiation • Named association: – left side: "formals" (port names from component declaration) – right side: "actuals" (architecture signals) • Independent of order in component declaration entity FULLADDER is port (A,B, CARRY_IN: in bit; SUM, CARRY: out bit); end FULLADDER; architecture STRUCT of FULLADDER is component HALFADDER port (X, Y : in bit; SUM, CARRY : out bit); end component; . . . signal W_SUM, W_CARRY1, W_CARRY2 : bit; begin MODULE1: HALFADDER port map (X => A, SUM => W_SUM, Y => B, CARRY => W_CARRY1); . . . end STRUCT;
- 21. References
- 22. • Zainalabedin Navabi, “Verilog Digital System Design”, 2th edition. • Zainalabedin Navabi, “VHDL modular Design and Synthesis of cores and Systems”, 3th edition. • Morteza Saheb Zamani, FPGA course slides, Spring 2016.
- 23. Parham Alvani Amirhossein Sohrabbeig Thank you ! Any Questions ?