![PALs
The project to create the PAL device was managed by John Birkner and the
actual PAL circuit was designed by H. T. Chua.[3] In a previous job, Birkner
had developed a 16-bit processor using 80 standard logic devices. His
experience with standard logic led him to believe that user programmable
devices would be more attractive to users if the devices were designed to
replace standard logic. This meant that the package sizes had to be more
typical of the existing devices, and the speeds had to be improved. The
PAL met these requirements and was a huge success and was "second
sourced" by National Semiconductor, Texas Instruments, and Advanced
Micro Devices.
Early PALs were 20-pin DIP components fabricated in silicon using bipolar
transistor technology with one-time programmable (OTP) titanium-tungsten
programming fuses.[4] Later devices were manufactured by Lattice
Semiconductor and Advanced Micro Devices using CMOS technology.
The original 20 and 24-pin PALs were denoted by MMI as medium-scale
integration (MSI) devices.](https://image.slidesharecdn.com/flashmemory-140915072304-phpapp01/85/Flash-memory-7-320.jpg)
Flash memory
- 3. PLDs Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable switches Main types of PLDs PLA PAL ROM CPLD FPGA Custom chips: standard cells, sea of gates
- 4. PLD as a Black Box Logic gates and programmable switches Inputs (logic variables) Outputs (logic functions)
- 5. Basic Programmable Logic Organizations Depending on which of the AND/OR logic arrays is programmable, we have three basic organizations AND ARRAY PROG. FIXED PROG. OR ARRAY FIXED PROG. PROG. ORGANIZATION PAL PROM PLA
- 6. Programmable Array Logic EARLY HISTORY:- Before PALs were introduced, designers of digital logic circuits would use small-scale integration (SSI) components, such as those in the 7400 series TTL (transistor-transistor logic) family; the 7400 family included a variety of logic building blocks, such as gates (NOT, NAND, NOR, AND, OR), multiplexers (MUXes) and demultiplexers (DEMUXes), flip flops (D-type, JK, etc.) and others. One PAL device would typically replace dozens of such "discrete" logic packages, so the SSI business went into decline as the PAL business took off. PALs were used advantageously in many products, such as minicomputers, as documented in Tracy Kidder's best-selling book "The Soul of a New Machine." PALs were not the first commercial programmable logic devices; Signetics had been selling its field programmable logic array (FPLA) since 1975. These devices were completely unfamiliar to most circuit designers and were perceived to be too difficult to use. The FPLA had a relatively slow maximum operating speed (due to having both programmable-AND and programmable-OR arrays), was expensive, and had a poor reputation for testability. Another factor limiting the acceptance of the FPLA was the large package, a 600-mil (0.6", or 15.24 mm) wide 28-pin dual in-line package (DIP).
- 7. PALs The project to create the PAL device was managed by John Birkner and the actual PAL circuit was designed by H. T. Chua.[3] In a previous job, Birkner had developed a 16-bit processor using 80 standard logic devices. His experience with standard logic led him to believe that user programmable devices would be more attractive to users if the devices were designed to replace standard logic. This meant that the package sizes had to be more typical of the existing devices, and the speeds had to be improved. The PAL met these requirements and was a huge success and was "second sourced" by National Semiconductor, Texas Instruments, and Advanced Micro Devices. Early PALs were 20-pin DIP components fabricated in silicon using bipolar transistor technology with one-time programmable (OTP) titanium-tungsten programming fuses.[4] Later devices were manufactured by Lattice Semiconductor and Advanced Micro Devices using CMOS technology. The original 20 and 24-pin PALs were denoted by MMI as medium-scale integration (MSI) devices.
- 9. PALs The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND gates. These AND gates, also known as product terms, are ORed together to form a sum-of-products logic array. The PAL architecture consists of two main components: a logic plane and output logic macrocells. Programmable logic plane The programmable logic plane is a programmable read-only memory (PROM) array that allows the signals present on the devices pins (or the logical complements of those signals) to be routed to an output logic macrocell. PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "sum-of-products" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs.
- 10. Programmable Array Logic (PAL) Also used to implement circuits in SOP form The connections in the AND plane are programmable The connections in the OR plane are NOT programmable and AND plane OR plane f 1 Input buffers inverters P 1 P k f m x 1 x 2 x n x 1 x 1 x n x n fixed connections
- 11. Example Schematic of a PAL f 1 P 1 P 2 f 2 x 1 x 2 x 3 AND plane P 3 P 4 f1 = x1x2x3'+x1'x2x3 f2 = x1'x2'+x1x2x3
- 12. PALs and PLAs What is difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA)? PAL concept — implemented by Monolithic Memories AND array is programmable, OR array is fixed at fabrication A given column of the OR array has access to only a subset of the possible product terms PLA concept — Both AND and OR arrays are programmable
- 13. PALs and PLAs Of the two organizations the PLA is the most flexible One PLA can implement a huge range of logic functions BUT many pins; large package, higher cost PALs are more restricted / you trade number of OR terms vs number of outputs Many device variations needed Each device is cheaper than a PLA
- 14. PAL 1st output section 2nd output section 3rd output section 4th output section Only functions with at most four products can be implemented inputs
- 15. PAL x x W = ABC + CD X = ABC + ACD + ACD + BCD Y = ACD + ACD + ABD x
- 16. PAL Logic Implementation Programmed PAL: Minimized Functions: W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D 4 product terms per each OR gate A B C D A B C D A BD BC 0 0 0 0 B C 0 0 BC BCD AD BCD W X Y Z
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