programmable logic devices part 1
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This document discusses programmable logic devices and how they can be used to implement integrated circuit designs that are required in small volumes but need to be produced in large volumes. It describes how programmable logic devices like PLDs, PALs, PLAs, CPLDs and FPGAs can be manufactured at large scale and then programmed to implement different designs. These programmable devices use technologies like lookup tables, transistor switching control and non-volatile memory to allow designs to be programmed after manufacturing.
programmable logic devices part 1
- 2. Facts: It is most economical to produce an IC in large volumes Many designs required only small volumes of ICs Need an IC that can be: Produced in large volumes Handle many designs required in small volumes A programmable logic part can be: Made in large volumes Programmed to implement large numbers of different low-volume designs
- 3. The technologies (continued) ◦ Build lookup tables Storage elements (as in a memory) ◦ Transistor Switching Control Stored charge on a floating transistor gate Erasable Electrically erasable Flash (as in Flash Memory) Storage elements (as in a memory)
- 4. Permanent - Cannot be erased and reprogrammed Mask programming Fuse Antifuse Reprogrammable ◦ Volatile - Programming lost if chip power lost Single-bit storage element ◦ Non-Volatile Erasable Electrically erasable Flash (as in Flash Memory)
- 5. Read Only Memory (ROM) - a fixed array of AND gates and a programmable array of OR gates Programmable Array Logic (PAL)® - a programmable array of AND gates feeding a fixed array of OR gates. Programmable Logic Array (PLA) - a programmable array of AND gates feeding a programmable array of OR gates. Complex Programmable Logic Device (CPLD) /Field- Programmable Gate Array (FPGA) complex enough to be called “architectures”
- 7. Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have: ◦ N input lines, ◦ M output lines, and ◦ 2N decoded minterms. Fixed AND array with 2N outputs implementing all N-literal minterms. Programmable OR Array with M outputs lines to form up to M sum of minterm expressions. A program for a ROM or PROM is simply a multiple-output truth table ◦ If a 1 entry, a connection is made to the corresponding minterm for the corresponding output ◦ If a 0, no connection is made Can be viewed as a memory with the inputs as addresses of data (output values), hence ROM or PROM names
- 8. The fixed "AND" array is a “decoder” with 3 inputs and 8 outputs implementing minterms. Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) The programmable "OR“ array uses a single line to represent all inputs to an OR gate. An “X” in the array corresponds to attaching the minterm to the OR Read Example: For input (A2, A1, A0) = 001, output is (F3,F2,F1,F0 ) = 0011.
- 9. A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output
- 10. This layout allows for a large number of logic functions to be synthesized in the sum of products (and sometimes product of sums) canonical forms
- 12. Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs. Advantages ◦ A PLA can have large N and M permitting implementation of equations that are impractical for a ROM (because of the number of inputs, N, required) ◦ A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL ORs ◦ Some PLAs have outputs that can be complemented, adding POS functions Disadvantage ◦ Often, the product term count limits the application of a PLA. Twolevel multiple-output optimization reduces the number of product terms in an implementation, helping to fit it into a PLA.
- 13. by kundan gupta