Programmable Logic Devices
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This document provides an introduction to programmable logic devices including read-only memory (ROM) and programmable logic arrays (PLA). It discusses the basic components and operations of random-access memory (RAM) and ROM. It then describes how PLA and programmable array logic (PAL) work, using AND-OR logic to implement combinational logic functions. Examples are provided to demonstrate how to design circuits using these programmable logic devices and simplify Boolean functions for efficient implementation.
Programmable Logic Devices
- 2. Introduction 2 There are two types of memories that are used in digital systems: Random-access memory(RAM): perform both the write and read operations. Read-only memory(ROM): perform only the read operation. The read-only memory is a programmable logic device. Other such units are the Programmable logic array(PLA) Programmable array logic(PAL) Field-programmable gate array(FPGA).
- 3. Array logic A typical programmable logic device may have hundreds to millions of gates interconnected through hundreds to thousands of internal paths. In order to show the internal logic diagram in a concise form, it is necessary to employ a special gate symbology applicable to array logic. 3
- 4. Random-Access Memory A memory unit stores binary information in groups of bits called words. 1 byte = 8 bits 1 word = 2 bytes The communication between a memory and its environment is achieved through data input and output lines, address selection lines, and control lines that specify the direction of transfer. 4
- 5. Content of a memory Each word in memory is assigned an identification number, called an address, starting from 0 up to 2k -1, where k is the number of address lines. The number of words in a memory with one of the letters K=210, M=220, or G=230. 64K = 216 2M = 221 4G = 232 5
- 6. Write and Read operations 6 Transferring a new word to be stored into memory: 1. Apply the binary address of the desired word to the address lines. 2. Apply the data bits that must be stored in memory to the data input lines. 3. Activate the write input.
- 7. Write and Read operations Transferring a stored word out of memory: 1. Apply the binary address of the desired word to the address lines. 2. Activate the read input. Commercial memory sometimes provide the two control inputs for reading and writing in a somewhat different configuration in table 7-1. 7
- 8. Types of memories 8 Memory units that lose stored information when power is turned off are said to be volatile. Both static and dynamic, are of this category since the binary cells need external power to maintain the stored information. Nonvolatile memory, such as magnetic disk, ROM, retains its stored information after removal of power.
- 9. Read-Only Memory A block diagram of a ROM is shown below. It consists of k address inputs and n data outputs. The number of words in a ROM is determined from the fact that k address input lines are needed to specify 2k words. 10
- 10. Construction of ROM Each output of the decoder represents a memory address. Each OR gate must be considered as having 32 inputs. A 2k X n ROM will have an internal k X 2k decoder and n OR gates. 11
- 11. Truth table of ROM A programmable connection between to lines is logically equivalent to a switch that can be altered to either be close or open. Intersection between two lines is sometimes called a cross- point. 12
- 12. Programming the ROM In Table 7-3, 0 no connection 1 connection Address 3 = 10110010 is permanent storage using fuse link 13 1 0 1 1 0 0 1 0 X : means connection
- 13. Combinational circuit implementation 14 The internal operation of a ROM can be interpreted in two way: First, a memory unit that contains a fixed pattern of stored words. Second, implements a combinational circuit. Fig. 7-11 may be considered as a combinational circuit with eight outputs, each being a function of the five input variables. A7(I4, I3, I2, I1, I0) = Σ(0,2,3…,29) In Table 7-3, output A7 Sum of minterms
- 14. Example Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number. Derive truth table first 15
- 15. Example 16
- 16. Types of ROMs 17 The required paths in a ROM may be programmed in four different ways. 1. Mask programming: fabrication process 2. Read-only memory or PROM: blown fuse /fuse intact 3. Erasable PROM or EPROM: placed under a special ultraviolet light for a given period of time will erase the pattern in ROM. 4. Electrically-erasable PROM(EEPROM): erased with an electrical signal instead of ultraviolet light.
- 17. Combinational PLDs 18 A combinational PLD is an integrated circuit with programmable gates divided into an AND array and an OR array to provide an AND-OR sum of product implementation. PROM: fixed AND array constructed as a decoder and programmable OR array. PAL: programmable AND array and fixed OR array. PLA: both the AND and OR arrays can be programmed.
- 19. Programmable Logic Array 24 Fig.7-14, the decoder in PROM is replaced by an array of AND gates that can be programmed to generate any product term of the input variables. The product terms are then connected to OR gates to provide the sum of products for the required Boolean functions. The output is inverted when the XOR input is connected to 1 (since x⊕1 = x’). The output doesn’t change and connect to 0 (since x⊕0 = x).
- 20. Programming Table 25 1. First: lists the product terms numerically 2. Second: specifies the required paths between inputs and AND gates 3. Third: specifies the paths between the AND and OR gates 4. For each output variable, we may have a T(ture) or C(complement) for programming the XOR gate
- 21. PLA F1 = AB’+AC+A’BC’ F2 = (AC+BC)’ 26
- 22. PLA 27
- 23. Simplification of PLA 28 Careful investigation must be undertaken in order to reduce the number of distinct product terms, PLA has a finite number of AND gates. Both the true and complement of each function should be simplified to see which one can be expressed with fewer product terms and which one provides product terms that are common to other functions.
- 24. Example 7-2 Implement the following two Boolean functions with a PLA: F1(A, B, C) = ∑(0, 1, 2, 4) F2(A, B, C) = ∑(0, 5, 6, 7) The two functions are simplified in the maps of Fig.7-15 29 1 elements 0 elements
- 25. PLA table by simplifying the function Both the true and complement of the functions are simplified in sum of products. We can find the same terms from the group terms of the functions of F1, F1’,F2 and F2’ which will make the minimum terms. F1 = (AB + AC + BC)’ F2 = AB + AC + A’B’C’ 30
- 27. 32 Example 1:
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- 29. Programmable Array Logic The PAL is a programmable logic device with a fixed OR array and a programmable AND array. 34
- 30. PAL 35 When designing with a PAL, the Boolean functions must be simplified to fit into each section. Unlike the PLA, a product term cannot be shared among two or more OR gates. Therefore, each function can be simplified by itself without regard to common product terms. The output terminals are sometimes driven by three-state buffers or inverters.
- 31. Example 36 w(A, B, C, D) = ∑(2, 12, 13) x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15) y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) z(A, B, C, D) = ∑(1, 2, 8, 12, 13) Simplifying the four functions as following Boolean functions: w = ABC’ + A’B’CD’ x = A + BCD w = A’B + CD + B’D’ w = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D
- 32. PAL Table z has four product terms, and we can replace by w with two product terms, this will reduce the number of terms for z from four to three. 37
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