Synthesis Examples

VHDL 360©by: Mohamed Samy Samer El-Saadany

CopyrightsCopyright © 2010/2011 to authors. All rights reservedAll content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners.VHDL 360 ©2

ObjectiveGetting familiar with code changes' impact on synthesisSkills gained:Writing synthesis friendly codeVHDL 360 ©4

OutlineIntroductionSynthesize and LearnCombinational LogicLatch InferenceSequential LogicFlip-Flop InferenceVHDL 360 ©5

IntroductionVHDL 360 ©6VHDL is a H/W modeling language used to model digital circuitsDigital circuits can be either Combinational or SequentialCombinational Logic circuits: Implement Boolean functions whose output is only dependant on the present inputsSequential Logic circuits: Implement circuits whose output depends on the present inputs & the history of the inputs. i.e. Circuits having storage elements

IntroductionVHDL 360 ©7VHDL StandardSynthesizable VHDLSynthesis tools translate the VHDL code to a gate level netlist representing the actual H/W gates [and, or, not, Flip-Flops…etc]Only a subset of the language is synthesizableA model can be eitherSynthesizable: Used for both Simulation & SynthesisNon-Synthesizable: Used for Simulation only

Synthesize and LearnIn the next slides we will use examples from the previous modules to demonstrate synthesis and study the synthesized logicWe will also modify these examples and observe the impact on the synthesized logic9VHDL 360 ©

Combinational LogiclibraryIEEE;useIEEE.std_logic_1164.all;Entitymux_caseis Port(a, b, c, d:instd_logic;Sel:instd_logic_vector(1downto0); F:outstd_logic);Endentity;Architecture rtl ofmux_caseisbegin process(a,b,c,d,sel)isbeginCaseselisWhen"00"=> f <= a;When"01"=> f <= b;When"10"=> f <= c;When"11"=> f <= d;whenothers=> f <= a;Endcase; Endprocess;Endarchitecture;VHDL 360 ©10Example 1: 4x1 Multiplexer

Skills CheckWhat is the impact of removing some signals from the sensitivity list as shown in example 2? Architecture rtl ofmux_caseisbegin process(a,b,c,d,sel)isbeginCaseselisWhen"00"=> f <= a;When"01"=> f <= b;When"10"=> f <= c;When"11"=> f <= d;whenothers=> f <= a;Endcase; Endprocess;Endarchitecture;VHDL 360 ©11Example 1: 4x1 MultiplexerExample 2: 4x1 Multiplexer Architecture rtl ofmux_caseisbegin process(a, sel)isbeginCaseselisWhen"00"=> f <= a;When"01"=> f <= b;When"10"=> f <= c;When"11"=> f <= d;whenothers=> f <= a;Endcase; Endprocess;Endarchitecture;

Skills Check (Soln.)Architecture rtl ofmux_caseisbegin process(a,b,c,d,sel)isbeginCaseselisWhen"00"=> f <= a;When"01"=> f <= b;When"10"=> f <= c;When"11"=> f <= d;whenothers=> f <= a;Endcase; Endprocess;Endarchitecture;VHDL 360 ©12No Impact on the synthesis results, however we will find that the simulation results differ

Synthesis tools don’t use the sensitivity list to determine the logic, but simulation tools depend on the sensitivity list to execute the process

Example 2 suffers a problem called “Simulation – Synthesis mismatch”Example 1: 4x1 MultiplexerExample 2: 4x1 MultiplexerArchitecture rtl ofmux_caseisbegin process(a, sel)isbeginCaseselisWhen"00"=> f <= a;When"01"=> f <= b;When"10"=> f <= c;When"11"=> f <= d;whenothers=> f <= a;Endcase; Endprocess;Endarchitecture;

Combinational LogicVHDL 2008* introduced the keyword "all" that implicitly adds all read signals to the sensitivity list to avoid “Simulation Synthesis mismatch”Architecture rtl ofmux_caseisbegin process(all)is beginCaseselisWhen"00"=> f <= a;When"01"=> f <= b;When"10"=> f <= c;When"11"=> f <= d;whenothers=> f <= a;Endcase; Endprocess;Endarchitecture;VHDL 360 ©13Example 3Golden rule of thumbTo avoid “Simulation Synthesis mismatch” problems when modeling Combinational logic, add all read signals to the sensitivity list*Not yet supported by all tools in the market

Combinational Logic14VHDL 360 ©Example 4: Adder-SubtractorLIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITYadd_subISport(a, b :ininteger; result :outinteger;operation:instd_logic);ENDENTITY;ARCHITECTURE behave OFadd_subISBEGINprocess(a, b, operation)beginif(operation = '1')thenresult <= a + b;else result <= a - b;endif;endprocess;ENDARCHITECTURE;

Combinational Logic15VHDL 360 ©Consider that someone tries to re-use that code to implement an adder with an enable  He modifies the add_sub example; removes the else branch & renames the “operation” port to “enable” as shown below, How would these changes affect the logic?Example 5:LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY adder ISport(a, b :ininteger; result :outinteger;enable:instd_logic);ENDENTITY adder;ARCHITECTURE behave OF adder ISBEGINprocess(a, b, enable)beginif(enable = '1')then result <= a + b;endif;endprocess;ENDARCHITECTURE;

Combinational Logic16VHDL 360 ©This will infer a latch, because we didn’t specify what should happen to “result” when “enable” isn’t equal to '1'Simulation & synthesis tools will just keep the value as is…i.e. It latches the last valueExample 5:LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY adder ISport(a, b :ininteger; result :outinteger;enable:instd_logic);ENDENTITY adder;ARCHITECTURE behave OF adder ISBEGINprocess(a, b, enable)beginif(enable = '1')then result <= a + b;endif;endprocess;ENDARCHITECTURE;

Combinational LogicIn the below example, the "11" value of "sel" signal is not listed as a case choice, hence signal "F" is not assigned a value in this caseA Latch is inferred in this example  Probably that wasn’t neededExample 6:LIBRARYieee;USEieee.std_logic_1164.all;ENTITYincomplete_caseISport(sel:std_logic_vector(1downto0); A, B:std_logic; F :outstd_logic);ENDENTITY;ARCHITECTURE rtl OFincomplete_caseISBEGIN process(sel, A, B) begin case(sel)is when"00"=> F <= A; when"01"=> F <= B; when"10"=> F <= A xor B; whenothers=>null; endcase; endprocess;ENDARCHITECTURE;17VHDL 360 ©

Skills CheckDo you think a Latch would be inferred in the below example?Example 7:LIBRARYieee;USEieee.std_logic_1164.all;ENTITYincomplete_assignmentIS port(sel:instd_logic_vector(1downto0); A, B :instd_logic; O1, O2:outstd_logic);ENDENTITY;ARCHITECTURE rtl OFincomplete_assignmentISBEGIN process(sel, A, B)begin case(sel)is when"00"=> O1 <= A; O2 <= A and B; when"01"=> O1 <= B; O2 <= A xor B; when"10"=> O1 <= A xor B; when"11"=> O2 <= A or B; whenothers=> O1 <= '0'; O2 <= '0'; endcase; endprocess;ENDARCHITECTURE;18VHDL 360 ©

Skills Check (Soln.)Example 7:LIBRARYieee;USEieee.std_logic_1164.all;ENTITYincomplete_assignmentIS port(sel:instd_logic_vector(1downto0); A, B :instd_logic; O1, O2:outstd_logic);ENDENTITY;ARCHITECTURE rtl OFincomplete_assignmentISBEGIN process(sel, A, B)begin case(sel)is when"00"=> O1 <= A; O2 <= A and B; when"01"=> O1 <= B; O2 <= A xor B; when"10"=> O1 <= A xor B; when"11"=> O2 <= A or B; whenothers=> O1 <= '0'; O2 <= '0'; endcase; endprocess;ENDARCHITECTURE;19VHDL 360 ©Do you think a Latch would be inferred in the below example?Latches are inferred for both signals "O1" & "O2"

Though the case is complete & no "null" statement is there, we find that "O1" & "O2" are not assigned in all case's branches  This is called “Incomplete signal assignment”Latch InferenceMost of the time latches are not desired in the design because they affect timing badlyTo remove unintended latches: Cover all branches of if-else and case statementsAvoid incomplete signal assignment by assigning a value to each signal in each branchif you don’t care about other conditional values then assign the output to '0' or '1'20VHDL 360 ©

Enough CombinationalLet's Go Sequential21

Sequential Logic22VHDL 360 ©Let's model the well known D-FF with outputs Q & nQ and see the synthesis resultsExample 8:Libraryieee;useieee.std_logic_1164.all;Entity d_ff isPort(d, clk, rst :instd_logic;Q, nQ :outstd_logic);endentity;Architecture behav of d_ff isBeginprocess(clk)beginIf(rising_edge(clk))thenIf(rst = '1')then Q <= '0'; nQ <= '0'; else Q <= d; nQ <=not (d); endif; endif;endprocess;end behav;

Sequential Logic23VHDL 360 ©Let's model the well known D-FF with outputs Q & nQ and see the synthesis resultsExample 8:Libraryieee;useieee.std_logic_1164.all;Entity d_ff isPort(d, clk, rst :instd_logic;Q, nQ :outstd_logic);endentity;Architecture behav of d_ff isBeginprocess(clk)beginIf(rising_edge(clk))thenIf(rst = '1')then Q <= '0'; nQ <='1'; else Q <= d; nQ <=not (d); endif; endif;endprocess;end behav;Two Flip-Flops ?!Change the code to have only one Flip-Flop

Sequential Logic24VHDL 360 ©Let's model the well known D-FF with outputs Q & nQ and see the synthesis resultsExample 9:Libraryieee;useieee.std_logic_1164.all;Entity d_ff isPort( d, clk, rst :instd_logic; Q, nQ :outstd_logic);endentity;Architecture behav of d_ff issignal Q_int:std_logic;Beginprocess(clk)beginIf(rising_edge(clk))thenIf(rst = '1')then Q_int <= '0'; else Q_int <= d; endif; endif;endprocess;Q <= Q_int;nQ <=not (Q_int);end behav;Yep…That's what we want!

Sequential Logic25VHDL 360 ©What about making an array of D-FFs?Example 10:Libraryieee;useieee.std_logic_1164.all;Entity d_ffs isPort(d: std_logic_vector(3downto0);clk, rst :instd_logic;Q, nQ :outstd_logic_vector(3downto0));endentity;Architecture behav of d_ffs issignal Q_int:std_logic_vector(3downto0);Beginprocess(clk)beginIf(rising_edge(clk))thenIf(rst = '1')then Q_int <= (others => '0'); else Q_int <= d; endif; endif;endprocess;Q <= Q_int;nQ <=not (Q_int);end behav;

Sequential LogicExample 11: 8-bit Shift Register (Shift right)Libraryieee;useieee.std_logic_1164.all;entity shift_register is Port( clk, D, enable :inSTD_LOGIC; Q :outSTD_LOGIC);endentity;architecture Behavioral of shift_register isbeginprocess(clk)variable reg:std_logic_vector(7downto0);beginifrising_edge(clk)thenif enable = '1' thenfor i in1to7loop reg(i-1):= reg(i);endloop; reg(7):= d;endif;endif; Q <= reg(0); endprocess;end Behavioral;7 6 5 4 3 2 1 0VHDL 360 ©26

Flip-Flop InferenceAssignments under clock edge where the object value needs to be remembered across multiple process invocations  Flip-FlopSignal assignment under clock edge will always infer a Flip-FlopVariable assignment under clock edge will infer Flip-Flop only when its value ought to be remembered across process invocations27VHDL 360 ©

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