![ADF7901
OUTLINE DIMENSIONS
7.90
7.80
7.70
24 13
4.50
4.40
4.30
6.40 BSC
1 12
PIN 1
0.65 1.20
BSC MAX
0.15
0.05
8° 0.75
0.30 0° 0.60
SEATING 0.20
0.19 PLANE 0.45
0.09
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153AD
Figure 9. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADF7901BRU 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24
ADF7901BRU-REEL 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24
ADF7901BRU-REEL7 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24
ADF7901BRUZ 1 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24
ADF7901BRUZ-RL1 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24
ADF7901BRUZ-RL71 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24
EVAL-ADF7901EB Evaluation Board
1
Z = Pb-free part.
Rev. A| Page 11 of 12](https://image.slidesharecdn.com/adf7901-121206031905-phpapp02/85/Adf7901-11-320.jpg)
Adf7901
- 1. High Performance ISM Band OOK/FSK Transmitter IC ADF7901 FEATURES GENERAL DESCRIPTION Single-chip, low power UHF transmitter The ADF7901 is a low power OOK/FSK UHF transmitter 369.5 MHz to 395.9 MHz frequency operation using designed for use in RF remote control devices. It is capable of fractional-N PLL and fully integrated VCO frequency shift keying (FSK) modulation on eight different 3.0 V supply voltage channels, selectable by three external control lines. OOK Data rates up to 50 kbps supported modulation is performed by modulating the PA control line. Low current consumption 26 mA at 12 dBm output at 384 MHz The on-chip VCO operates at 2× the output frequency. The Power-down mode (<1 μA) division by 2 at the output of the VCO reduces the amount of 24-lead TSSOP PA feedthrough. As a result, OOK modulation depths of greater than 50 dB are easily achievable. The FSK_ADJ and ASK_ADJ resistors can be adjusted in the system to optimize output power for each modulation scheme. An additional 1.5 dB of output power is provided for the lower bank of channels to adjust for antenna performance. The CE line allows the transmitter to be powered down completely. In this mode, the leakage current is typically 0.1 μA. FUNCTIONAL BLOCK DIAGRAM CREG2 PA_EN CVCO OSC1 OSC2 VDD VCO RFOUT PA DVDD R=1 RFGND PDF CHARGE PUMP LDO CREG1 REGULATOR 1 ⎟ FRACTIONAL N LDO REGULATOR CREG2 TXDATA FSK Σ-Δ 2 CHANNEL SELECT RSET CE DGND FSK1 FSK2 FSK3 OOK_SEL 05349-001 RSET_FSK RSET_OOK Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
- 2. ADF7901 TABLE OF CONTENTS Features .............................................................................................. 1 Channel Frequencies.....................................................................9 General Description ......................................................................... 1 Layout Guidelines....................................................................... 10 Functional Block Diagram .............................................................. 1 Decoupling.............................................................................. 10 Specifications..................................................................................... 3 Regulator Stability .................................................................. 10 Absolute Maximum Ratings............................................................ 5 Grounding............................................................................... 10 ESD Caution.................................................................................. 5 Supply ...................................................................................... 10 Pin Configuration and Function Descriptions............................. 6 Digital Lines............................................................................ 10 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 11 Circuit Description........................................................................... 9 Ordering Guide .......................................................................... 11 Loop Filter ..................................................................................... 9 REVISION HISTORY 3/06—Rev. 0 to Rev. A Added Crystal ESR Parameter ........................................................ 4 Change to Figure 8 ......................................................................... 10 Updated Outline Dimensions ....................................................... 11 Changes to Ordering Guide .......................................................... 11 3/05—Revision 0: Initial Version Rev. A | Page 2 of 12
- 3. ADF7901 SPECIFICATIONS VDD =3.0 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Typical specifications, TA = 25°C. 1 Table 1. Parameter Min Typ Max Unit Comments/Conditions RF CHARACTERISTICS Output Frequency Ranges Channel 1 369.5 MHz Channel 2 371.1 MHz Channel 3 375.3 MHz Channel 4 376.9 MHz Channel 5 384.0 MHz Channel 6 388.3 MHz Channel 7 391.5 MHz Channel 8 394.3 MHz Channel 9 395.9 MHz Phase Frequency Detector Frequency 9.8304 MHz TRANSMISSION PARAMETERS Transmit Rate FSK 50 kbps OOK 50 kbps Frequency Shift Keying FSK Separation 2 −34.8 kHz Data = 1 +34.8 kHz Data = 0 On/Off Keying Modulation Depth 3 83 dB Output power = 12 dBm Output Power Min/Max Range 4 15 dBm fOUT ≤ 384 MHz 10 12 dBm fOUT > 384 MHz 7 10.5 dBm Occupied 20 dB BW OOK at 1 kbps ±28 ±461.9 kHz FSK (PA Off/On) at10 Hz 5 ±26 ±461.9 kHz LOGIC INPUTS VINH, Input High Voltage 2.124 V VINL, Input Low Voltage 0.2 × VDD V IINH/IINL, Input Current ±1 μA CIN, Input Capacitance 10 pF POWER SUPPLIES Voltage Supply DVDD 3.0 V Transmit Current Consumption 369.5 MHz to 376.9 MHz at 12 dBm 26 mA 384 MHz at +12 dBm 26 mA 388.3 MHz to 395.9 MHz at 10.5 dBm 21 mA 384 MHz at 5 dBm 17 mA Power-Down Mode Low Power Sleep Mode 6 0.2 1 μA Rev. A| Page 3 of 12
- 4. ADF7901 Parameter Min Typ Max Unit Comments/Conditions PHASE-LOCKED LOOP VCO Gain 30 MHz/V At 384 MHz Spurious3, 7 100 kHz loop BW Integer Boundary –45 −23 dBc Reference −70 −23 dBc Harmonics3 Second Harmonic VDD = 3.0 V −24 −21 dBc Third Harmonic VDD = 3.0 V −14 −11 dBc All Other Harmonics −18 dBc REFERENCE INPUT Crystal Reference 9.8304 MHz Crystal ESR 8 80 Ω POWER AMPLIFIER PA Output Impedance 97 Ω + 6.4 pF At 384 MHz TIMING INFORMATION Crystal Oscillator to PLL Lock3 2 3 ms PA Enable to PA Ready–PLL Settle 9 100 250 μs TEMPERATURE RANGE (TA) 0 50 °C 1 Operating temperature range is 0°C to 50°C. 2 Frequency Deviation = 58 × (9.8304 MHz)/214. Error in the crystal is reflected in variation in the desired deviation. 3 Not production tested; based on characterization. 4 The output power can be varied in both ASK/FSK mode by altering the relevant external resistor. 5 Measured using spectrum analyzer, 1 MHz span, 100 kHz RBW, maximum hold enabled. 6 Maximum power-down current specification applies for the OSC2 pin grounded. 7 Measured >461.9 kHz away from channel. 8 Maximum recommended crystal ESR. The crystal oscillator works with crystals with higher ESR, but this results in longer power-up times. 9 This specification refers to the time taken for the PLL to regain lock after the PA has been enabled. The PA is should only be enabled after the PLL has settled to the correct frequency. Rev. A | Page 4 of 12
- 5. ADF7901 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. 1 Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Value may cause permanent damage to the device. This is a stress VDD to GND 2 −0.3 V to +4.0 V rating only; functional operation of the device at these or any RFVDD to GND −0.3 V to +4.0 V other conditions above those listed in the operational sections Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V of this specification is not implied. Exposure to absolute Operating Temperature Range maximum rating conditions for extended periods may affect Industrial (B Version) 0°C to 50°C device reliability. Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 125°C TSSOP θJA Thermal Impedance 150.4°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 235°C Infrared (15 sec) 240°C 1 This device is a high performance, RF-integrated circuit with an ESD rating of <1 kV. It is ESD sensitive. Take proper precautions for handling and assembly. 2 GND = RFGND = DGND = 0 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A| Page 5 of 12
- 6. ADF7901 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD 1 24 CREG2 CREG1 2 23 RSET CPOUT 3 22 PA_EN TxDATA 4 21 DVDD DGND 5 20 RFOUT ADF7901 NC 6 19 RFGND DGND 7 TOP VIEW 18 VCOIN (Not to Scale) OSC1 8 17 CVCO OSC2 9 16 RSET_FSK OOK_SEL 10 15 RSET_OOK FSK1 11 14 CE 05349-002 FSK2 12 13 FSK3 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Function 1 DVDD Positive Supply for the Digital Circuitry. This must be 3.0 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 2 CREG1 A 2.2 μF capacitor should be added at CREG1 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but can cause higher spurious. 3 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 4 TxDATA Digital FSK data to be transmitted is inputted on this pin. 5 DGND Ground for Digital Section. 6 NC No Connect. 7 DGND Ground for Digital Section. 8 OSC1 The reference crystal should be connected between this pin and the OSC2 pin. The necessary crystal load capacitor should be tied between this pin and ground. 9 OSC2 The reference crystal should be connected between this pin and the OSC1 pin. The necessary crystal load capacitor should be tied between this pin and ground. A TCXO or external square wave can also be connected to this pin, with OSC1 left floating. A DC-blocking capacitor (4.7 nF is adequate) should be placed between the TCXO output and OSC2 pin. When not using an external regulator, a 1 MΩ resistor can be tied between the OSC2 pin and ground to meet the power-down current specification of 1 μA. 10 OOK_SEL A high on this pin selects operation in OOK mode at 384 MHz when CE is high. 11 FSK1 FSK Channel Select Pin. This represents the LSB of the channel select pins. 12 FSK2 FSK Channel Select Pin. 13 FSK3 FSK Channel Select Pin. 14 CE Bringing CE low puts the ADF7901 into power-down, drawing <1 μA of current. 15 RSET_OOK The value of this resistor sets the output power for data = 1 in OOK mode. A resistor of 3.6 kΩ provides the maximum output power. Increasing the resistor reduces the power and the current consumption. A lower resistor value than 3.6 kΩ can be used to increase the power to a maximum of 14 dBm. The PA does not operate efficiently in this mode. 16 RSET_FSK The value of this resistor sets the output power in FSK mode. A resistor of 3.6 kΩ provides maximum output power. Increasing the resistor reduces the power and the current consumption. A resistor value lower than 3.6 kΩ can be used to increase the power to a maximum of 14 dBm. The PA does not operate efficiently in this mode. 17 CVCO A 22 nF capacitor should be tied between the CVCO and CREG2 pins. This line should run underneath the ADF7901. The capacitor is necessary to ensure stable VCO operation. 18 VCOIN The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage the higher the output frequency. The output of the loop filter is connected here. 19 RFGND Ground for Output Stage of Transmitter. 20 RFOUT The modulated signal is available at this pin. Output power levels are from –5 dBm to +12 dBm. The output should be impedance matched using suitable components to the desired load. Rev. A | Page 6 of 12
- 7. ADF7901 Pin No. Mnemonic Function 21 DVDD Voltage Supply for VCO and PA Section. It should be supplied with 3.0 V. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. 22 PA_EN This pin is used to enable the power amplifier. It should be modulated with the OOK data in OOK mode. In FSK mode, it should be enabled when the PLL is locked. 23 RSET External Resistor. Sets charge pump current and some internal bias currents. Use 3.6 kΩ as default. 24 CREG2 A 2.2 μF capacitor should be added at CREG2 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but can cause higher spurs. Rev. A| Page 7 of 12
- 8. ADF7901 TYPICAL PERFORMANCE CHARACTERISTICS Mkr1 10.00kHz Ref 15dBm Atten 30dB Noise –89.55dB/Hz 16 Avg Log 10 1R dB/ 12 OUTPUT POWER (dBm) RBW 300.0000000Hz 8 PAvg 1 W1 S2 S3 FS 4 AA £(f): f<50k Swp 05349-004 05349-006 0 2 3 4 5 6 7 8 9 10 Center 395.948 29MHz Span 50kHz RSET #Res BW 300Hz VBW 300Hz Sweep 2.118 s (601 pts) Figure 3. Output Power vs. RSET FSK, Upper FSK Channels, Figure 5. Phase Noise at Channel 9 Measured into 50 Ω Mkr4 1.59GHz Ref 15dBm Atten 30dB –21.30dB Peak 35 Log 10 4R Marker Trace Type X Axis Amplitude dB/ 2 1 (1) Freq 400MHz –25.56dB 4 2 (1) Freq 800MHz –13.89dB 30 3 (1) Freq 1.19GHz –34.53dB 1 4 (1) Freq 1.59GHz –21.30dB 3 25 IDD (mA) 20 15 LgAv 05349-007 10 05349-005 4 5 6 7 8 9 10 Center 5.50GHz Span 10.5GHz OUTPUT POWER (dBm) #Res BW 1MHz VBW 1MHz Sweep 17.52 ms (601 pts) Figure 4. Current Consumption vs. Output Power, Upper FSK Channels, Figure 6. Harmonic Levels—Up to Fourth Harmonic, Measured into 50 Ω Measured at Channel 9 into 50 Ω Rev. A | Page 8 of 12
- 9. ADF7901 CIRCUIT DESCRIPTION Table 4. CHANNEL FREQUENCIES Frequency (MHz) FSK3 FSK2 FSK1 OOK_SEL 369.5 0 0 0 0 The nine channel frequencies listed in Table 4 are obtainable 371.1 0 0 1 0 from a single 9.8304 MHz crystal reference by changing the 375.3 0 1 0 0 value of the N and F numbers in the fractional PLL, using 376.9 0 1 0 0 control lines FSK1, FSK2, and FSK3. The channel frequency is 384.0 Don’t Don’t Don’t 1 given by care care care FCHANNEL = FREF × (N + F) 388.3 1 0 0 0 391.5 1 0 1 0 However, the VCO is tuned to operate over a frequency range 394.3 1 1 0 0 of 344 MHz to 401 MHz (typically). Therefore, any channel 395.9 1 1 1 0 frequency within this range can be obtained if the required reference frequency is used. The N and F numbers for each LOOP FILTER channel are listed in Table 5, together with the corresponding The loop filter integrates the current pulses from the charge channel frequencies for 9.8304 MHz and, for example purposes, pump to form a voltage that tunes the output of the VCO to the frequencies for 10 MHz. With the 10 MHz reference, the two desired frequency. It also attenuates spurious levels generated by largest N settings give channel frequencies above the maximum the PLL. The recommended loop filter design for this circuit is VCO output frequency and are therefore invalid. 297 kHz. This is based on the trade-off between attenuation of beat note spurs and the need to minimize chirp when the PA is Frequency deviation is also dependent on reference frequency. turned on. The relationship is given by FDEV = 58 × (9.8304 MHz)/214 CHARGE R2 = 6.2kΩ Therefore, the frequency deviation is 34.8 kHz when the VCO PUMP OUT 9.8304 MHz reference is used and 35.4 kHz when the 10 MHz R1 = 3kΩ reference is used. C1 = 33pF C2 = 390pF C3 = 10pF Table 5. 05349-008 Channel Frequency (MHz) Figure 7. N F 9.8304 MHz Ref 10 MHz Ref 37 2406/4096 369.5 375.9 Improved spurious performance in FSK mode can be achieved 37 3073/4096 371.1 377.5 by using a narrower loop bandwidth. For a data rate of 20 kbps, 38 727/4096 375.3 381.8 a loop bandwidth of roughly 50 kHz would be suitable. The 38 1374/4096 376.9 383.4 following components give a loop bandwidth of 51.1 kHz: 39 256/4096 384.0 390.6 C1 = 680 pF 39 2048/4096 388.3 395 39 3381/4096 391.5 398.3 C2 = 15 nF 40 452/4096 394.3 N/A 40 1118/4096 395.9 N/A C3 = 180 pF R1 = 510 Ω R2 = 6.2 kΩ ADIsimPLL is a free software tool offered by Analog Devices for assistance in designing with ADI’s frequency synthesizers and ISM band transmitters. To select the correct loop filter components for use with the ADF7901, open a project for the ADF7012 device. Then, enter the desired output carrier frequency and loop bandwidth, and use the 870 μA charge pump current setting. ADIsimPLL can be downloaded from www.analog.com. Rev. A| Page 9 of 12
- 10. ADF7901 2.2μF 2.2μF 22nF MATCHING RFOUT TO 50Ω CVCO CREG2 CREG1 DVDD RSET 27nH 5TH-ORDER, LOW-PASS FILTER 3.6kΩ 5.6pF 22nH 22nH 1.5pF RFOUT ANTENNA 3pF 8pF 3pF 36nH VCOIN CPOUT VCOIN ADF7901 MATCHING 50Ω RSET_FSK TO ANTENNA 3.6kΩ TxDATA RSET_OOK FSK1 3.6kΩ FSK2 OSC2 FSK3 9.8304MHz OOK_SEL OSC1 PA_EN 33pF 33pF CE GND 05349-003 NOTES 1. DECOUPLING CAPACITORS HAVE BEEN OMITTED FOR CLARITY. Figure 8. Applications Diagram for the ADF7901 in a Remote Control System LAYOUT GUIDELINES Grounding The layout of the board is crucial to ensuring low levels of Emphasis should be placed on grounding once the decoupling spurious and harmonics. capacitors have been added. The PA stage switches currents of 15 mA in maximum power mode. This causes changes in the Decoupling ground resulting in large return currents that can radiate to Decoupling capacitors (high frequency 22 pF, low frequency other parts of the board. The shortest and least obstructed 100 nF) should be placed as close as possible to the supply pins ground from RFGND back to the ground of the battery should be on the part. Low size 0402 and 0603 components are recom- ensured. A 4-layer board helps, as well as flooding the top layer. mended for the high frequency rejection on the supply. The ground paths should not have any vias and should be wide tracks. Regulator Stability A minimum of 1 μF is needed on both CREG1 and CREG2 to ensure Supply stability. An additional 22 pF capacitor can be added to reject The supply tracks can be routed through vias, because they act higher frequency noise. Because many of the internal blocks as free inductors and make layout easier on a 2-layer board run off the regulator, it is critical to reduce its noise. Low size (see the Decoupling section). Tracks should be wide. 0402 and 0603 components are recommended for the high frequency rejection on the supply. Digital Lines Digital lines should contain a large resistor in series. This impedance blocks signals of many frequencies, including harmonics and the carrier frequency. Long control lines can act as antennae. It can be useful to add capacitance to ground. There is some capacitance to ground provided by the lines and at the input of the digital pins. Rev. A | Page 10 of 12
- 11. ADF7901 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 0° 0.60 SEATING 0.20 0.19 PLANE 0.45 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153AD Figure 9. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADF7901BRU 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24 ADF7901BRU-REEL 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24 ADF7901BRU-REEL7 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24 ADF7901BRUZ 1 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24 ADF7901BRUZ-RL1 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24 ADF7901BRUZ-RL71 0°C to 50°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24 EVAL-ADF7901EB Evaluation Board 1 Z = Pb-free part. Rev. A| Page 11 of 12
- 12. ADF7901 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05349-0-3/06(A) Rev. A | Page 12 of 12