An Explicit Approach for Dynamic Power Evaluation for Deep submicron Global Interconnects with Current Mode Signaling Technique

ACEEE Int. J. on Electrical and Power Engineering, Vol. 01, No. 03, Dec 2010

An Explicit Approach for Dynamic Power
Evaluation for Deep submicron Global
Interconnects with Current Mode Signaling
Technique
Rajib Kar, K.Ramakrishna Reddy, Ashis K. Mal, A.K.Bhattacharjee
Department of Electronics & Communication Engg.,
NIT Durgapur-713209, India
Email: {rajibkarece, ramu023}@gmail.com

Abstract— As the VLSI process technology is shrinking to the the global interconnects can be reduced by reducing
nanometer regime, power consumption of on-chip VLSI voltage swings on the line. However, in a voltage mode
interconnects has become a crucial and an important issue. scenario, this means that the signals need to be amplified
There are several methodologies proposed to estimate the on- back, which consumes power and leads to a tradeoff
chip power consumption using Voltage Mode Signaling
technique (VMS). But the major drawback of VMS is that it
between the circuit power loss and the interconnect power
increases the power consumption of on-chip interconnects loss [6]. In a current mode situation, the swings can be
compared to current mode signaling (CMS). A closed form independently controlled leading to extremely low power
formula is, thus, necessary for current mode signaling to consumption in the wire and reduced wire delays.
accurately estimate the power dissipation in the distributed The power analysis of current mode signaling for RC
line. In this paper, we derived an explicit dynamic power interconnects was presented in [1]. However, the analysis is
formula in S-domain based on Modified Nodal Analysis carried out by considering DC node voltages in dynamic
(MNA) formulation. The usefulness of our approach is that power calculations. In order to model the dynamic power
dynamic power consumption of an interconnect line can be dissipation of current mode signaling, an efficient and
estimated accurately and efficiently at any operating
frequency. By substituting s=0 in the vector of node voltages
accurate as well as generic model is being developed based
in our model results similar solution as that of Bashirullah
on modified nodal analysis (MNA) approach. In this work,
et. al. Comparison of simulation results with other total analysis is carried out in S-domain in order to estimate
established models justifies the accuracy of our approach.
dynamic power dissipation accurately at any operating
frequency. To the best of our knowledge, there are no such
Index Terms— Current mode signaling, On-chip Interconnect, generic closed form expressions available which can
MNA Analysis, Dynamic Power. estimate the dynamic power dissipation at varying
frequency.
I. INTRODUCTION We have made the following contributions in this
literature:
The continuous miniaturization of integrated circuits has A novel and efficient as well as an accurate model is
opened the path towards System-on-Chip realizations. being proposed for the estimation of the dynamic power for
Process shrinking into the nanometer regime improves global on-chip VLSI RC interconnects. Our proposal is
transistor performance while the dynamic power different from [1] in the sense that [1] only can estimate the
dissipation of global interconnects, connecting circuit dynamic power for dc node voltages. On the contrary,
blocks separated by a long distance, significantly increases. using our model, the dynamic power can be accurately
Signaling across long global on-chip interconnects is estimated at any given frequency.
rapidly becoming a performance limiter due to reverse The paper is organized as follows:
interconnect scaling trends. Traditionally, voltage mode In section 2, the basic theory regarding the dynamic
repeaters along the interconnect have been used to reduce power dissipation and the modified nodal analysis is being
the delays in signal transmission. However, there is a limit discussed. Section 3 describes the model to calculate the
in the performance improvement that can be obtained with node voltage and the dynamic power for any given
repeaters in deep submicron designs in terms of power and frequency. Section 4 shows the dynamic power model for a
delay [5], [7]. Current mode signaling has been explored as typical case, i.e. at dc node voltage. Section 5 discusses the
an alternative choice for data transmission over results and the comparison to some established methods.
interconnects in [1], [4], and [8]. Power consumption on And finally section 6 concludes the paper.

Corresponding author: RAJIB KAR
Email: rajibkarece@gmail.com

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© 2010 ACEEE
DOI: 01.IJEPE.01.03.90


II. BASIC THEORY A. Dynamic Power Model
Long global interconnects can be modeled by distributed We can not accurately model the dynamic power
RC transmission lines as long as the overall line resistance dissipation of current mode circuits by the following well
dominates the response (i.e. R>>jwL). These RC known equation:
interconnect lines can be driven either by voltage-mode or
current-mode signals. For Current mode signaling, Pd=Vdd2 Ct f (A)
interconnect terminates at a finite resistance in addition to a Since it assumes that all the capacitive
capacitive load, as shown in fig. 1. components of a distributed RC line are charged to Vdd. As
illustrated in fig. 2, the voltage at any point of a resistively
terminated line will be less than Vdd, resulting in smaller
dynamic power dissipation components. In order to
accurately model this effect, we find voltage at each node
of an N-segment distributed RC line by using modified
nodal analysis.
B. Modified Nodal Analysis Approach
The distributed RC network shown in figure 1 , can be
conveniently expressed in terms of state equations by using
Modified Nodal Analysis representation (MNA) [2-3]. The
Figure 1. Generalized distributed RC model generalized output equation can be expressed in the
Laplace domain as:
[G + sC ] ⋅ [X(s )] = b(s ) (1)
A generalized model for a driven distributed RC line is Where G and C are the nodal conductance and
shown in Fig. 1. The diver is modeled as a voltage source capacitance matrices, respectively. X is vector of node
with output resistance RS. For the sake of generality the voltages and b(s) is the input source excitation.
output of the line is terminated with a resistor RL, and load
capacitance CL. For voltage-mode signaling, the ⎡Gs1 + Gu − Gu 0 ... ... 0 ⎤
termination resistance RL is infinite and the output voltage ⎢ −G ⎥
⎢ 2Gu − Gu 0 ... 0 ⎥
is seen across CL. In current mode signaling (CMS), the u

terminating resistance RL is finite. ⎢ 0 − Gu 2Gu − Gu 0 ... ⎥ (2)
Power dissipation in current mode circuits are classified [G ] = ⎢ ...
⎢ ... ... ... ... ... ⎥
⎥
into three components: static, dynamic and short circuit ⎢ ... 0 − Gu 2Gu − Gu 0 ⎥
power dissipation components. Static power dissipation ⎢ ⎥
⎢ ... ... 0 − Gu 2Gu − Gu ⎥
component arises from the constant current path from Vdd ⎢ 0
⎣ ... 0 0 − Gu GL + Gu ⎥
⎦
to ground via the resistive termination RL as shown in fig.
2. The dynamic power is dissipated when the capacitive
components are charged through the PMOS device and Gu is the segment conductance of the distributed
discharged via the NMOS device. The third source of transmission line and GL is the load conductance.
power dissipation arises from the finite input signal edge Gs1=1/(Rs+Ru); where Rs is the source resistance
rates that result in short-circuit current. Generally, careful The capacitance matrix of the distributed RC line is:
control of input edge rates can minimize the cross-over
current component to within 20% of the total dynamic ⎡Cu 0u 0 ... ... 0 ⎤
power dissipation [9]. ⎢0 Cu 0 0 ... 0 ⎥
⎢ ⎥
⎢0 0u Cu 0 0 ... ⎥ (3)
[C ] = ⎢ ...
⎢ ... ... ... ... ... ⎥
⎥
⎢ ... 0 0 Cu 0 0 ⎥
⎢ ⎥
⎢ ... ... 0 0 Cu 0 ⎥
⎢0 ... 0 0 0 Cu + CL ⎥
⎣ ⎦

Where Cu is the segment capacitance of the distributed
transmission line and CL is the load capacitance.

Figure 2. Power dissipation in interconnect line for current mode III. POWER DISSIPATION FOR AC NODE VOLTAGES
signaling
In order to determine dynamic power dissipation of the
distributed line, node voltages are required. The node
voltage vector X(s) can be determined by using (1).

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© 2010 ACEEE
DOI: 01.IJEPE.01.03.90


[ X ( s )] = [G + sC ]−1 b( s ) (4) A general closed form expression for ith node voltage of
A general closed form expression for ith node voltage of X(s) is given by,
X(s) is given by:
vi =
1
D
[
(vdd.Gs1 ) AGu .GL + Gu2 ] (14)

⎡ ( A +1)A ⎤
1 ⎢ AGu .GL + 2 Gu sCu ⎥ (5) Where
vi = (vdd .Gs1 ) ⎢ ⎥ D. = mG s1G L Gu + G s1G u +G u2G L
2
(15)
D ⎢+ G2 + A.G sC + ( A +1)( A −1)A sC G ⎥
⎢ u
⎣
u L
6
u L
⎥
⎦ A = N-I (16)
Where By substituting these node voltages in (11) gives final
A = N-i (6) expression for total dynamic power dissipation is,
D = X+Y (7) Pdyn = (α ⋅ v dd ) f ⋅ act ⋅ (C u ⋅ Q + C L )
2
(17)
X . = mG s1 G L G u + G s1 G + mG u G s1 sC L +G G L
2
u
2
u
(8) Where,
⎡ R N (N + 1)(2 N + 1) ⎛ Ru ⎞ ⎤
2
(18)
⎡ mN ⎤ Q = ⎢ N + N (N + 1) u + ⎜ ⎟
⎜R ⎟ ⎥
⎢ 2 Gs1Gu sCL + NGu sCu + Gu sCL ⎥
2 2
⎢ RL 6 ⎝ L⎠ ⎥
⎣ ⎦
Y =⎢ ⎥ (9)
⎢+ mN G G sC + nC G sC G ⎥ As N approaches infinity in the above equation, (18)
⎢ 2 u L u
⎣
N −3 s1 u L
⎥
⎦ results a closed form expression for total dynamic power
dissipation for current mode circuits. It is given as,
Here m = N-1; where N is number of nodes in
Pdyn = (α ⋅ vdd ) f ⋅ act ⋅ K
2
(19)
distributed line
In (8), higher order terms are not considered since And k and α are defined as,
product of s and C (Cu or CL) for higher powers is almost
⎡ ⎛ R 1⎛ R ⎞
2
⎞⎤
zero. K = ⎢C L + C t ⎜1 + t + ⎜ t ⎟ ⎟⎥ (20)
The dynamic power at each node can be written as ⎢ ⎜ RL 3 ⎜ RL
⎝
⎟
⎠ ⎟⎥
⎣ ⎝ ⎠⎦
Pi = vi2 C i f ⋅ act (10)
RL
α= (21)
Where Ci is the capacitance at each node and act is the R L + R s + Rt
switching activity factor. Hence, the total dynamic power
dissipation can be expressed as, Where, Rt =N Ru (22)
N N
Pdyn = ∑ Pi = ∑ v C i f ⋅ act
2
i
(11)
and Ct = N Cu (23)
i =1 i =1

Evaluating the summation in closed-form gives total The expression (19) is much similar to the established
dynamic power dissipation for current-mode circuits. The model [1]. For a given frequency, (11) gives better result
usefulness of our approach is that power consumption of an when compared to (19), since its node voltages depends
interconnect line can be estimated accurately at any upon the operating frequency.
operating frequency. Note that as RL approaches, infinity (i.e. voltage-mode),
(19) reduces to the more familiar dynamic power
IV. POWER DISSIPATION OF DC NODE VOLTAGES dissipation formulation of voltage-mode circuit.
The static power dissipation component of an
On substituting s=0 in (4), the DC node voltages are interconnect line for current-mode signaling can be
obtained. It can be written as, expressed as:
2
[X(s )] = [G ]⋅−1 b(s ) (12) Vdd (24)
p stst =
−1 Rs + R L + Rt
Ginv is the inverse matrix ( G ) which can be expressed
as: Equation (24) signifies that the static power dissipation
component dominates for low interconnect resistance line
⎧ [Gu + ( N − k )GL ]⋅ [Gu + (i − 1)Gs1 ] (i.e Rt < 500 Ω), indicating that current mode signaling
⎪ G [G G + ( N − 1)G G + G G ] ∈ i ≤ k should be used for long global interconnects to minimize
⎪ u u s1 L s1 L u
(13)
⎪ the total power dissipation
Ginv (k , i ) = ⎨
⎪ V. SIMULATION RESULTS
⎪ [Gu + ( N − i )GL ]⋅ [Gu + (k − 1)Gs1 ]
⎪ G [G G + ( N − 1)G G + G G ] ∈ i > k In order to verify the accuracy of the proposed power
⎩ u u s1 L s1 L u
model, it is compared with the well excepted model
Where k and i are row and column of an inverse matrix proposed in [1]. The results are based on (11), (19) and
−1 other established model [1] for 0.18-µm process with
( G ).
29
© 2010 ACEEE
DOI: 01.IJEPE.01.03.90


interconnect resistance (Rt) and capacitance (Ct) varied dissipate more dynamic power when compared to current
from 50Ω-1000Ω resistance and 100fF-2pF, respectively. mode circuits.
Other pertinent parameters are defined as follows: Comparison of dynamic power dissipation expression
f clock
=2GHz, Vdd =l.8V, Wp/Wn=3, activity factor act=0.5, (for s=0) and Bsh model for typical values of RL is shown
in table 1. From table 1, we find that our model is much
Rs=50 Ω, CL =50pf and RL =100 Ω. similar to the Bsh model for current mode signaling at dc
node voltages i.e. at s=0.
-3
We can easily extend our result to voltage mode (By
x 10
3.5 substituting RL = ∞ and RS = 0 ). If we do so, we will get
our work for s=0 the similar expression as that of [1].
3 our work
Bsh model

2.5
VI. CONCLUSION
A closed form expression for the dynamic power
2
dissipation of a driven distributed RC line is derived in
power(w)

1.5
Laplace domain for current mode signaling. The expression
is modeled in such a way that power dissipation in
1 distributed line is estimated accurately at any operating
frequency. For a typical case, the closed form power
0.5 dissipation expression, on substituting s=0 in our model, is
also presented. The derived expression along with this
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 analysis can serve as a convenient tool for dynamic power
RC(sec) -9
x 10 estimation without much computation during design.
Figure 3. Dynamic power dissipation for different
values of RC with RL=100 Ω
TABLE I. DYNAMIC POWER DISSIPATION (MW) FOR
CMS WITH R L =100 Ω, CL=50PF
Fig. 3 illustrates the dynamic power dissipation
dependency on interconnect RC delay (i.e Rt.Ct) for current RC(ns) Bsh Our work Our work
for s=0
mode drivers. Above figure signifies that our proposed
1 1.5 1.5 0.68
model is having higher accuracy than the Bsh model [1] at 1.5 1.9 1.9 0.81
2GHz frequency. The reason that our approach is showing 2 2.2 2.2 0.91
lesser power dissipation because of the fact that we are 2.5 2.4 2.4 1.0
dealing with the ac node voltage in the power dissipation 3 2.6 2.6 1.1
calculation. For dc node voltage (i.e. s=0) the magnitude of
the dynamic power dissipation will be higher compared to
that of the ac nodes. TABLE II. DYNAMIC POWER DISSIPATION (MW) FOR
CMS WITH R L=150 Ω, CL=50PF

1.4
RC(ns) Bsh Our work Our work
RL=100 for s=0
1.2
RL=200 1 1.6 1.6 0.71
RL=500 1.5 2.0 2.0 0.85
RL=1000
1 RL=inf(VM)
2 2.3 2.3 0.93
2.5 2.5 2.5 1.0
0.8
3 2.7 2.7 1.1
power(mW)

0.6
TABLE III. DYNAMIC POWER DISSIPATION (MW) FOR
0.4 CMS WITH R L =200 Ω, CL =50PF
RC(ns) Bsh Our work Our work
0.2
for s=0
1 1.7 1.7 0.73
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.5 2.1 2.1 0.85
RC(ns)
2 2.4 2.4 0.96
Figure 4: dynamic power dissipation for different values of RL 2.5 2.6 2.6 1.1
3 2.8 2.8 1.1

Fig. 4 illustrates the dynamic power dissipation
dependency on load resistance RL. In figure 4, as load
resistance increases, the dynamic power dissipation
increases indicating that voltage mode circuits (i.e. RL = ∞ )

30
© 2010 ACEEE
DOI: 01.IJEPE.01.03.90


REFERENCES [6] C. Svensson, “Optimum Voltage Swing on On-Chip and Off-
Chip Interconnect,” IEEE Journal of Solid State Circuits and
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Approach to network analysis,” IEEE Trans. Circuits and Presence of Process Variations,” Proceedings of Sixth
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[4] I Dhaou, M. Ismail, and H. Tenhunen. Current mode ,Low pages 522– 527, March 2005
Power ,On –Chip Signaling in Deep Sub-micron CMOS [9] M. K. Gowan, L.L. Biro, D.B. Jackson, “Power
Technology, IEEE Transactions on Circuits and Systems considerations in the design of the Alpha 21264
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and Systems, 29, No.6:663-670, June 1994.

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DOI: 01.IJEPE.01.03.90

An Explicit Approach for Dynamic Power Evaluation for Deep submicron Global Interconnects with Current Mode Signaling Technique

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