ANALYTICAL AND NUMERICAL MODELING OF VTH AND S FOR NEW CG MOSFET STRUCTURE

International Journal of Information Sciences and Techniques (IJIST) Vol.6, No.3/4/5/6, November 2016
DOI : 10.5121/ijist.2016.6601 1
ANALYTICAL AND NUMERICAL MODELING OF VTH
AND S FOR NEW CG MOSFET STRUCTURE
H. Jaafar*, A. Aouaj*, and A. Bouziane*
*
Laboratory of automatic, conversion of energy and Microelectronics
Team: Automatic, Microelectronics and Nanotechnology
University Sultan Moulay Slimane - Faculty of Sciences and Techniques,
Béni Mellal, Morocco
ABSTRACT
In this work, we study analytical model such threshold voltage (VTH) and Subthreshold swing (SS) for a new
Surrounding Gate MOSFET. This new SG-MOSFET is composed of Dual-metal Gate (DMG) M1 and M2
with different work function, Graded Channel (GC) whose the doping is higher near the source side than
the drain side and Dual Oxide Thickness (DOT). Analytical model for VTH and SS are developed by solving
2D Poisson equation using parabolic approximation method. Results for new device are compared to those
obtained by numerical simulation and have been found to be in good agreement. Comparative study
between (DMG-GC-DOT) SG MOSFET and with different device engineering shows that the new structure
provides improved electron transport and reduced short channel effects (SCE).
KEYWORDS
Surrounding gate MOSFET, Dual Oxide Thickness (DOT), Threshold voltage, Subthreshold swing, Short
channel effects.
1. INTRODUCTION
With the decrease of the length of the channel, short-channel effects (SCE) impose a physical
limit on the ultimate performance of traditional planar metal-oxide-semiconductor field effect
transistors (MOSFETs) [1]. Over the past few years, various alternative structures have been
proposed to address these gaps, among them surrounding cylindrical MOSFET gate (SG) offers a
better control of the SCE, and is regarded as one of the devices of the most promising [2]. In
addition, SG MOSFET can be used for the construction of integrated circuits to very high density
for its dimensions extremely reduced [3].
New structures are proposed incorporating dual-material gate (DMG), graded channel (GC) and
dual layer oxide (DOT) to strengthen the immunity against the effects of short canals (SCE), such
as the threshold voltage, and Subthreshold Swing (SS) degradation, and to provide choice more
realistic for the process of MOSFET.
Dual-material gate (DMG) structure using two metals with different work functions provides a
step in the surface potential profile [4, 5], the electric field peak near the drain is lowered
considerably. In addition, the dual-material gate achieves simultaneous suppression of SCE, and
the performance improvement is dependent on the work function difference [6]. The structure of
GC constitutes an excellent immunity despite the SCEs [7], with doping near the side of the
source is high and low doping near the side of the drain. The use of two oxides thickness (DOT)
in the dielectric oxide has became an attractive solution to reduce the short effects of channel [8].

2
Figure 1. Cross-sectional views of various device design engineering on SG MOSFET. (a) DMG,
(b) DMG-DOT, (c) DMG–GC–DOT
In this study, a new device structure as Dual Material Graded Channel Dual Oxide Thickness
Surrounding Gate (DMG-GC-DOT) MOSFET is suggested as shown in Figure 1, which the gates
has two metal (M1 and M2) with different work functions, an oxide structure with two different
layers oxide tox1 and tox2 and a graded channel with two different doping (NH and NL) (H, high; L,
low).
By solving 2D Poisson equation using parabolic approximation method, the expressions for
surface potential, electric field, and threshold voltage are derived [9]. Subsequently, using device
simulation and employing the analytical models [10], the reduction of SCE in DMG-GC-DOT
MOSFET is presented. The results obtained are compared to results for (DMG) and (DMG-DOT)
SG MOSFET. Also the analytical model results are verified by comparing them with the
simulated results obtained from the numerical simulation.
2. MODEL DERIVATION
In our new structure (DMG-GC-DOT) MOSFET, as shown in figure 1(c), the channel can be
divided in two parts the lengths of the two metal M1 and M2 are L1 and L2=L-L1 respectively, the
doping concentration NH in the halo region (L1) is higher than NL in the rest of the channel
(L2=L-L1) and the thickness oxide tox1 in the rest of the channel in region L1 is large than tox2 in
region L2=L-L1.
Analytical and numerical models of threshold voltage and subthreshold swing for DMG-GC-DOT
MOSFET are compared to those for DMG, and DMG-DOT MOSFET.
2.1. SURFACE POTENTIAL MODEL
The surface potential and electric field distribution in the silicon are derived by solving 2D
Poisson’s equation. Presuming that the impact of fixed charges and charge carriers can be
ignored on electrostatics of the channel.

3
The electrostatic potential ( )
z
r
i ,
ϕ in two regions (i=1, 2) of the channel can be written as:
( ) ( )
si
i
i
i qN
z
z
r
r
z
r
r
r ε
ϕ
ϕ
=
∂
∂
+






∂
∂
∂
∂
2
2
,
,
1
,
0 L
z ≤
≤
2
0 si
t
r ≤
≤
(1)
Where si
t is the thickness of the silicon channel, si
ε is the dielectric constant of silicon pillar,
H
N
N =
1 and L
N
N =
2 .
The potential distribution in the two regions is assumed to be a parabolic profile in the radial
direction and can be written as:
( ) ( ) ( ) ( ) 2
2
1
0 .
.
, r
z
p
r
z
p
z
p
z
r i
i
i
i +
+
=
ϕ (2)
Where ( )
z
pi0 , ( )
z
pi1 , and ( )
z
pi2 are functions of z only.
In the centre of the silicon pillar, the electric field equal zero by symmetry
( ) ( )
z
p
r
z
r
i
r
i
1
0
0
,
=
=






∂
∂
=
ϕ
(3)
At the oxide-silicon interface, the electric flux is given as
( ) ( )
( ) ( ) si
i
si
FB
GS
si
ox
t
r
i
t
z
p
z
V
V
c
r
z
r
i
i
si
2
2
,
=
+
+
=






∂
∂
=
ϕ
ε
ϕ
(4)
Where








+
=
si
oxi
si
ox
oxi
t
t
t
c
2
1
ln
2ε
is the oxide capacitance of slice oxide (i=1, 2), VGS is the gate to
source voltage. ( )
z
r
i ,
ϕ is the surface potential, ox
ε the dielectric constant of SiO2 gate oxide
and 1
ox
t is the oxide layer of region L1 and 2
ox
t is oxide layer of region L-L1.
i
FB
V is The flat band voltages of the two part of regions (i=1, 2) will be different and they are
presented as:
siH
FB
V ϕ
ϕ −
= 1
1
, siL
FB
V ϕ
ϕ −
= 2
2 (5)
Where 1
ϕ is the work function of M1 and 2
ϕ is also the work function of M2, and siH
ϕ and siL
ϕ
the work functions of the region L1 and the rest of silicon pillar, respectively.
By using the boundary conditions, the Poisson equation in the two parts of regions is resolved,
and is reduced as following:

4
( ) ( ) i
si
i
si
D
z
z
z
=
−
∂
∂
ϕ
λ
ϕ 2
2
2
i=1, 2
(6)
Where si
si
oxi
i t
c ε
λ 4
= is characteristic length and ( )
FBi
GS
i
si
i
i V
V
qN
D −
−
=
2
λ
ε
At the source end, the potential is ( ) 1
1 0
,
0 bi
V
=
ϕ , where 1
bi
V is the built in potential
1 2
ln H d
bi t
i
N N
V V
N
 
=  
 
.
At the drain end, the potential is ( ) ds
bi V
V
L +
= 2
2 ,
0
ϕ , Where L is the device channel length,
DS
V is drain to source voltage and 2 2
ln L d
bi t
i
N N
V V
N
 
=  
 
.
The general solution for the surface potential has the form:
( ) ( ) ( ) 2
exp
exp
i
i
i
i
i
i
si
D
z
B
z
A
z
λ
λ
λ
ϕ −
+
−
=
(7)
Using boundary conditions, the coefficients Ai and Bi (i = 1, 2) can be determined as:
1
2
1
1
1 1
B
D
V
A bi −
+
=
λ
(8)
( ) ( )
L
L
B
D
V
V
A ds
bi 2
2
2
2
2
2
2 exp
exp
2
λ
λ
λ 







−








+
+
= (9)
0
2
2
U
U
B = ,
0
1
1
U
U
B = , 1
0
2
0
2 C
c
C
a
U −
= , 2
0
1
0
1 C
b
C
d
U −
= , 0
0
0
0
0 c
b
d
a
U −
= (10)
( ) ( ) ( )
1
1
2
2
1
1
1
2
2
2
2
1 exp
exp
exp 1
2
L
L
D
V
L
D
V
V
C bi
ds
bi λ
λ
λ
λ
λ
−
−








+
−
−








+
+
=
( )
L
D
D
2
2
2
2
2
1
1
exp λ
λ
λ
−








−
+
(11)
( ) ( ) ( )
1
1
2
2
1
1
1
1
2
2
2
2
2
2 exp
exp
exp 1
2
L
L
D
V
L
D
V
V
C bi
ds
bi λ
λ
λ
λ
λ
λ
λ −
−








+
+
−








+
+
−
=
(12)
The differentiation of surface potential is carried out along the channel to get the distribution of
the Electric Field disposed by:
( ) ( ) ( )
z
B
z
A
z
E i
i
i
i
i
i
i λ
λ
λ
λ exp
exp +
−
−
= L
z ≤
≤
0 i=1, 2
(13)

5
2.2. THRESHOLD VOLTAGE MODEL
In the structure which has two material gates, the position of the minimum surface potential is
always located under the gate material having higher work function (M1). Accordingly, the
derivative of the expression of surface potential under M1 to zero, the position of the minimum
surface potential can be found. By equating 1
0
s
d
dz
ϕ
= , we get:
1
1
min
2
1
A
B
z
λ
=
(14)
By definition, the threshold voltage VTH is determined as the value of VGS at which the minimum
surface potential is ( )
,min min 2
si si B
z
ϕ ϕ ϕ
= = , where φB is the bulk Fermi potential.
We considered the minimum surface potential in the region L1, where the concentration of doping
NH is high (region (1)).
,min
si
ϕ can be deduced from Equation (7):
2
1
1
1
1
min
, 2
λ
ϕ
D
B
A
si −
=
(15)
The threshold voltage can be expressed as:
( ) σ
σξ
η
η 2
4
2
−
+
−
=
TH
V (16)
Figure 2. Surface potential along the channel for DMG-GC-DOT, DMG-DOT and DMG.

6
Where:
( ) ( )
1
1
2
0 sinh
exp
2 L
L
a λ
λ
−
= , ( )
( )
1
2
0 sinh
2 L
L
b −
= λ (17)
( ) ( )
1
1
2
1
0 cosh
exp
2 L
L
c λ
λ
λ −
= , ( )
( )
1
2
2
0 cosh
2 L
L
d −
−
= λ
λ (18)
0
0
0
0
0 c
b
d
a
U −
= , ( )
1
1
0 exp L
e λ
−
= , ( )
1
2
1 exp L
e λ
−
= (19)
( )
L
e 2
2 exp λ
−
= ,
( )
1
2
1
1 FB
si
aH
V
qN
a +
=
λ
ε
,
( )
2
2
2
2 FB
si
aL
V
qN
a +
=
λ
ε (20)
( )
1
0
2
1 1
a
V
e
e
b bi +
= , 1
1
1 b
c λ
= (21)
( )
2
1
2 2
a
V
V
e
b bi
ds +
+
= , 2
2
2 b
c λ
= , ( ) ( )
( ) 0
1
2
0
2
1
1
0
2 U
e
e
e
b
e
e
e
d
E λ
λ −
+
−
=
(22)
( )
( ) ( )
( ) 0
1
2
2
1
2
1
2 U
c
c
b
a
a
e
b
b
d
D −
+
−
+
−
= , ( )
1
4
4 2
+
+
−
= E
E
σ (23)
( ) B
bi a
DE
D
E
a
V ϕ
η 4
2
8
4
4 1
1
1
+
+
−
+
+
=
( ) 2
1
2
1
2
1 4
4
4
4 1 B
B
bi a
a
D
D
a
V ϕ
ϕ
ξ −
−
−
−
+
=
(24)
2.3. SUBTHRESHOLD SWING
In a simple approach, the subthreshold swing (SS) can be expressed as:
Figure 3. Surface potential for DMG-GC-DOT (L1=25nm), DMG-GC-DOT (L1=50nm) and DMG-GC-
DOT (L1=75nm) as a function of channel length with L=100nm, tsi=20nm, tox1=2nm, tox2=4nm, VGS=0.1V
and VDS=0.5V
( )
1
min
,
10
ln
−








∂
∂
=
GS
si
V
q
KT
SS
ϕ
(25)

7
From Equation (15), we obtain:
( ) ( )
2
1
1
1
2
1
1
1
min
,
1 P
B
P
A
B
A
VGS
si
+
+
=








∂
∂ 




 −
ϕ
(26)
Where
( )
( ) ( )
( ) ( ) ( )
( )
( )
1
1
2
1
2
2
0
0
1
2
1
1
2
0
0
1 exp
exp
exp
exp L
L
L
U
b
L
L
L
U
d
P λ
λ
λ
λ
λ
λ
λ +
−
−
−
−
−
+
−
=
1
2 1 P
P −
−
=
3. RESULTS AND DISCUSSION
By using the derived analytical models, the performances of DMG-GC-DOT MOSFET are
examined in terms of threshold voltage and subthreshold swing. To verify the proposed analytical
model, surface potential distribution versus the channel length was plotted and compared with the
numerical results. For analytical modeling, the doping concentrations in two regions are:
17 3
3.10
H
N cm−
= , 16 3
4.10
L
N cm−
= .
Figure 4. Variation of the Electric Field versus channel length for DMG-GC-DOT, DMG-DOT and DMG
with VGS=0.1V and VDS=0.5V
In figure 2, we show the evolution of the surface potential for DMG-GC-DOT, DMG and DMG-
DOT along the channel for L=100nm, 1 25
L nm
= , 20
si
t nm
= , 1 2
ox
t nm
= ,
2 4
ox
t nm
= , 0.1
GS
V V
= , 0.5
DS
V V
= , 20 3
2.10
d
N cm−
= , 16 3
4.10
L
N cm−
= , 1 4.8
ϕ = ,
17 3
3.10
H
N cm−
= , and 2 4.4
ϕ = .
It can see according to the figure that the minimal surface potential occurs in the first region of
DMG-GC-DOT. For DMG-GC-DOT, there is an additional step of potential near the limit of the

8
two metal gates which indicates a better control of the channel region near the source from drain
voltage of DMG-GC-DOT.
Figure 3 shows the variation of surface potential for various values of L1 by keeping the total sum
length of gate constant. Consequently, there is a shift in the potential of surface, a change of step
of potential along the channel with interface M1-M2.
Figure 4 reveals a Variation of the Electric Field. The profile involves a change of step in the
electric Field located at the junction of two metals. The augment in the lateral Electric Field in the
channel located under the interface of two gate materials creates an increase in the carrier
transport efficiency.
Figure 5 presents the variation of the threshold voltage along the channel for DMG–GC–DOT,
DMG and DMG-DOT. The figure indicates that when the channel length reduced, the threshold
voltage decreases more quickly in DMG-DOT and DMG compared to DMG-GC-DOT.
20 30 40 50 60 70 80 90 100
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
Channel length L(nm)
threshold
voltage
(V)
Figure 5. Threshold voltage VTH as a function of channel length L for DMG–GC–DOT, DMG and DMG-
DOT.
In figure 6, we plot the threshold voltage shift (∆VTH) variation versus channel length for DMG,
DMG-DOT and DMG-GC-DOT MOSFETs. In Fig.6, it is evident that DMG-GC-DOT MOSFET
provides higher efficacy to (∆VTH) as compared to DMG, and DMG-DOT MOSFETs.

9
20 30 40 50 60 70 80 90 100
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
channel length L(nm)
threshold
voltage
shift
(V)
Figure 6. Threshold voltage shift versus channel length for DMG-GC-DOT, DMG and DMG-DOT
MOSFET
The threshold voltage variation of DMG-GC-DOT keeps very small when the gate length is over
60 nm. This feature is very important when the device dimensions are continuously shrinking.
20 30 40 50 60 70 80 90 100
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Channel length L(nm)
thresh
old
v
olta
ge
(V)
Figure 7. Effect of the gate ratio of L1 to L2 on threshold voltage
Figure 7 shows the smallest ratio of L1 to L2 degrade the threshold voltage much more than other
ratios. It can be concluded that a larger ratio of control gate length to the total gate length can
efficiently lower the channel potential barrier and enhance the immunity to SCE.

10
20 30 40 50 60 70 80 90 100
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
Channel length,L(nm)
Su
bthresho
ld
S
win
g,SS
(V/dec)
Figure 8. Subthreshold swing (SS) versus Channel length (L) for DMG-GC-DOT, DMG and DMG-DOT.
Figure 8 shows the variation of the subthreshold swing along the channel for DMG-GC-DOT,
DMG and DMG-DOT. It is clear that the subthreshold reduced for device DMG-GC-DOT than
DMG-DOT and DMG.
4. CONCLUSIONS
In short, two dimensional analytical models of the surface potential, electric field, and threshold
voltage are derived for the new structure MOSFET (DMG-GC-DOT), by solving 2D Poisson’s
equation in the two channel regions. From the results obtained Physics based analytical model of
the surface potential, Electric Field and threshold voltage has been developed to find the influence
of gate engineering and oxide thickness on the SCEs. It has been demonstrated that DMG-GC-
DOT MOSFET provides a better immunity to SCEs as compared to other structure MOSFET, so
it can be concluded that the use of two oxide thickness causes better threshold-voltage, SS
performance of DMG-GC-DOT devices. By using numerical simulation, the simulated results
obtained coincide with The results obtained from the models. In this manner witness of the
validity and the accuracy of the developed model. DMG-GC-DOT provides choice of process
more flexible to optimize the execution of MOSFETs.
REFERENCES
[1] Y. Taur, C. H. Wann, and D. J. Frank, (1998) “25 nm CMOS design considerations”, Electron
Devices Meeting, 1998. IEDM'98. Technical Digest., International. IEEE, 1998. pp789 -792.
[2] H. Abd-Elhamid, (2007 ) “Compact Modeling of multiple gate MOS devices”.
[3] Y. Pratap, P. Ghosh, S. Haldar, R. S. Gupta, and M. Gupta, (2014) “An analytical subthreshold
current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of
device design engineering”, Microelectronics Journal, Vol. 45, No.4, pp408-415.
[4] A. Pal, and A. Sarkar, (2014) “Analytical study of Dual Material Surrounding Gate MOSFET to
suppress short-channel effects (SCEs)”, Engineering Science and Technology, an International
Journal, Vol.17, No.4, pp205-212.
[5] C. Li, Y. Zhuang, and R. Han, (2011) “Cylindrical surrounding-gate MOSFETs with electrically
induced source/drain extension”, Microelectronics Journal, Vol.42, No.2, pp341-346.
[6] L. Cong, Z. Yi-Qi, Z. Li, and J. Gang, (2014) “Quasi-two-dimensional threshold voltage model for
junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-
material gate,” Chinese Physics B, Vol.23, No.1, pp018501.

11
[7] H. Kaur, S. Kabra, S. Bindra, S. Haldar, and R. S. Gupta, (2007) “Impact of graded channel (GC)
design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short
channel immunity and hot carrier reliability,” Solid-state electronics, Vol.51, No.3, pp398-404.
[8] M. Wu, X. Jin, H. I. Kwon, R. Chuai, X. Liu, and J. H. Lee, (2013) “The optimal design of
junctionless transistors with double-gate structure for reducing the effect of band-to-band tunneling,”
JSTS: Journal of Semiconductor Technology and Science, Vol.13, No.3, pp245-251.
[9] L. Zun-Chao, (2009) “Dual-material surrounding-gate metal–oxide–semiconductor field effect
transistors with asymmetric halo”, Chinese Physics Letters, Vol.26, No.1, pp018502.
[10] A. Aouaj, A. Bouziane, and A. Nouaçry, (2012) “Analytical V TH and S models for (DMG–GC–
stack) surrounding-gate MOSFET”, International Journal of Electronics, Vol.99, No.1, pp141-148.
AUTHORS
H. Jaafar
She earned his BS degree in science physique in 2008, and her Magister degree in
Microelectronic of system Engineering in 2014 from University of mohamed ben abdellah,
Fes. Her main research interests include modelisation and simulation of new device of
MOSFET cylindrical gate.

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