anlog layout .. (2)
- 1. VENKATESWARLU KOTA E-mail: shanmukhavenky.org@gmail.com Mobile: +91-9492778695 Institute of Silicon Systems Pvt. Ltd. OBJECTIVE: Seeking a challenging career wherein I can integrate my technical and analytical skills to produce some original contribution of my own in the emerging technologies. EDUCATION PROFILE: M.Tech in VLSI & ES from GMR Institute of Technology (Affiliated to JNTU Kakinada) with an aggregate of 7.79 CGPA in 2015. B.Tech (ECE) from BVC Engineering College (Affiliated to JNTU Kakinada) with an aggregate of 74.97% in 2012. Intermediate from GRC Junior College (Board of Intermediate) with an aggregate of 86.40% in 2005. SSC from Smt.GMD High School (Board of Secondary Education) with an aggregate of 73% in 2003. CUSTOM LAYOUT DESIGN SUMMARY: Completed intensive training in VLSI-Custom Layout Designing from Institute of Silicon SystemsPvt. Ltd., Hyderabad from28th December, 2015 to 8th April, 2016. Cadence Tools: Experience in Custom Layout Designing using Cadence tools. Virtuoso Layout (L/XL) Editor - Floor Planning and Routing Assura & PVS Verification - DRC & LVS Targeted Technology - TSMC 130nm and GPDK 45nm CUSTOM LAYOUT PROJECTS: DIGITAL LAYOUT DESIGNS: Project 1: Standard Cell Layout Designs Cells Designed: INVERTER, NAND, AND, NOR, OR, EX-OR, and DFF. Targeted Technology: TSMC 130nm Role: Developing the Standard cells for given Spice Netlist and verify errors. Challenges: Creating devices manually, maintain equal Cell height for all cells in-terms of no. of metal track, carving, maintain Half DRC rules and De-bugging errors (DRC and LVS).
- 2. VENKATESWARLU KOTA E-mail: shanmukhavenky.org@gmail.com Mobile: +91-9492778695 Institute of Silicon Systems Pvt. Ltd. ANALOG LAYOUT DESIGNS: Targeted Technology: GPDK 45nm Role: Development of layout from schematic, providing critical matching for devices and verifying DRC and LVS for both top level and bottom level blocks. Project 2: Level Shifter Description: It is a conventional level shifter which is used to shift the voltage levels. Challenges: Taken care of PSUB2(for isolating substrate) and drawing the layout in optimized way. Project 3: Operational Amplifier (Op-Amp) Description: It is a DC differential amplifier which produces high gain by providing proper feedback. Challenges: Critical matching for Diff-pair and current mirrors, signal flow, provide dummy's to protect the critical devices, provide guard rings, layout compactness and protect critical nets from noise coupling. Project 4: Band Gap Reference (BGR) Description: It is a circuit which provides a constant voltage irrespective of temperature variations and input violations. Challenges: Floor planning, power routing, taken care of EM and IR drop, BJT’s & device matching with respect to PVT and protecting critical nets (shielding) from noise coupling. Project 5: Digital to Analog Converter (8-bits) Description: It scales digital reference signal as an analog output signal according to the digital input given (Switches to R-2R network). Challenges: Providing proper matching for resistor network (R-2R), match the critical nets to meet the same delay, device matching with respect to PVT, taken care of EM and IR drop, taken care of critical nets, antenna effect, provide proper bias from sources and signal flow. Project 6: PLL Phase Locked Loop (PLL) Description: A phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. Challenges: Floor planning, power routing, taken care of EM, device matching with respect to PVT as well from (STI, LOD, and WPE), protecting critical nets and capacitors matching.
- 3. VENKATESWARLU KOTA E-mail: shanmukhavenky.org@gmail.com Mobile: +91-9492778695 Institute of Silicon Systems Pvt. Ltd. SKILLS GAINED: Writing a SPICE level net list of a given circuit Debugging DRC and LVS violations Matching with respect to PVT Shielding ESD Effect Antenna Effect IR and EM Effects Floor Planning and Power Routing WPE, STI and LOD Effects Latch-up Noise Coupling Device Formation ACDEMIC PROJECT: Title: “Design of A Synthesizable Pipelined MIPS Core for Embedded Applications” Description: The use of soft core processors has become inevitable in electronic and mechanical industries for embedded applications. In my project soft-core reconfigurable pipelined MIPS processor is developed, which is used in all embedded on-chip applications. Specifically, synthesizable VHDL model for un-pipelined and pipelined MIPS Processor is simulated. This design is useful for all synthesized to verify the synthesizability. Modelsim is used for logical verification and synthesizing is carried out using Xilinx- ISE14.2 tool. The results prove the proper functioning of the processor and found to occupy less area compared to previous one. PERSONAL PROFILE: Father’s Name : Ramudu K Mother’s Name : Lakshmi K Date of Birth : 01-05-1987 Languages Known : English, Telugu Current Location : Hyderabad (Flexible to migrate)