Application of 8086 and 8085 Microprocessor in Robots.pptx

8085 Microprocessor
Architecture
&
Pin configuration

8085 Microprocessor Architecture & Pin configuration
• Pin configuration of 8085
• Limitations of 8085
• Internal Architecture of 8085
• 8085 Single board Microcomputer System

Pin configuration of 8085
8-bit general purpose μp
Capable of addressing 64 k of memory
Has 40 pins
Requires +5 v power supply
Can operate with 3 MHz clock

Pin configuration of 8085
All the signals can be classified into
Six groups –
1. Address Bus
2. Data Bus
3. Control & Status signals
4. Power signal & frequency
signals
5. Externally initiated signals
6. Serial I/O ports

Address & data bus
• 8085 μp consists of 16 signal pins use as address bus.
• Divide into 2 part: A15 – A8 (upper)
AD7 – AD0 (lower).
– A15 – A8 : Unidirectional, known as ‘high order address’.
– AD7 – AD0 : bidirectional and dual purpose (address and data placed
once at a time).
– AD7 – AD0 also known as ‘low order address’.
– To execute an instruction, at early stage AD7 – AD0 uses
as address bus and alternately as data bus for the next
cycle.
– The method to change from address bus to data bus
known as ‘bus multiplexing’.

Control & Status signals
This group of signal includes-
 Two control signals (RD’ & WR’)
 Three status signals (IO/M’ , S1 & S0)
 One special signal (ALE)
• RD’ – Read (active low). To indicate that the I/O or memory
selected is to be read and data are available on the bus.
• WR’ – Write (Active low). This is to indicate that the data available
on the bus are to be written to memory or I/O ports.
• IO/M’ – To differentiate I/O operation or memory operations.
– ‘0’ - indicates a memory operation.
– ‘1’-indicates an I/O operation.
– IO/M’ combined with RD and WR to generate I/O and memory control
signals.

Control and Status Signals.
•S1 and S0: Status signals, similar to IO/M, can identify various
operations as shown on the following table :

Control & Status signals
•ALE (Address Latch Enable) signal :
ALE used to de-multiplex address/data bus
Active high signal - generated to show the start of 8085 operation.
When transition 1-to-0: indicate that lines AD7-AD0
(AD7-AD0 = A7-A0) act as address lines.

Power signal & frequency signals
 Vcc : +5 V power supply
 Vss : Ground reference
 X1 & X2 : A crystal is connected at
these two pins. The frequency is
divided by two.
Therefore, to operate a system at 3
MHz, the crystal should have a
frequency of 6 MHz.
 CLK OUT : This signal is used as the
system clock for other devices.

Externally initiated Signals including Interrupt

Externally initiated Signals including Interrupt
RESET IN’ : When the signal on this pin goes low,
the program counter is set to zero.
the buses are tri-sated.
MPU is reset.
RESET OUT : This signal is used to reset other
devices.

Serial I/O ports
The 8085 has two signals to implement the
serial transmission:
 SID: Serial Input Data
 SOD: Serial Output Data

Limitations of 8085
• The low order address bus is multiplexed with the
data bus. The buses need to be de-multiplexed.
• Appropriate control signals need to be generated
to interface memory and I/O with the 8085.

De-multiplexed Address & Data bus with Control Signals

Internal Architecture of 8085
• It includes-
– ALU
– Timing & Control Unit
– Instruction Register and Decoder
– Register Array
– Interrupt Control
– Serial I/O Control

8085Single board Microcomputer System

8086 Microprocessor
J Srinivasa Rao
Govt Polytechnic Kothagudem
Khammam

Microprocessor
Program controlled semiconductor device (IC)
which fetches (from memory), decodes and
executes instructions.
It is used as CPU (Central Processing Unit) in
computers.
19

Microprocessor
First Generation
Between 1971 – 1973
PMOS technology, non compatible with TTL
4 bit processors  16 pins
8 and 16 bit processors  40 pins
Due to limitations of pins, signals are
multiplexed
Second Generation
During 1973
NMOS technology  Faster speed, Higher
density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
Ability to address large memory spaces
and I/O ports
Greater number of levels of subroutine
nesting
Better interrupt handling capabilities
Intel 8085 (8 bit processor)
Third Generation
During 1978
HMOS technology  Faster speed, Higher
packing density
16 bit processors  40/ 48/ 64 pins
Easier to program
Dynamically relatable programs
Processor has multiply/ divide arithmetic
hardware
More powerful interrupt handling
capabilities
Flexible I/O port addressing
Intel 8086 (16 bit processor)
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
32 bit processors
Physical memory space 224 bytes = 16 Mb
Virtual memory space 240 bytes = 1 Tb
Floating point hardware
Supports increased number of addressing
modes
Intel 80386
Fifth Generation Pentium
20

Functional blocks
Microprocessor
Flag
Register
Timing and
control unit
Register array or
internal memory
Instruction
decoding unit
PC/ IP
ALU
Control Bus Address Bus
Data Bus
21
Computational Unit;
performs arithmetic and
logic operations
Various conditions of the
results are stored as
status bits called flags in
flag register
Internal storage of data
Generates the
address of the
instructions to be
fetched from the
memory and send
through address
bus to the
memory
Decodes instructions; sends
information to the timing and
control unit
Generates control signals for
internal and external
operations of the
microprocessor

Overview
8086 Microprocessor
First 16- bit processor released by
INTEL in the year 1978
Originally HMOS, now manufactured
using HMOS III technique
Approximately 29, 000 transistors, 40
pin DIP, 5V supply
Does not have internal clock; external
asymmetric clock source with 33%
duty cycle
20-bit address to access memory  can
address up to 220 = 1 megabytes of
memory space.
Addressable memory space is
organized in to two banks of 512 kb
each; Even (or lower) bank and Odd (or
higher) bank. Address line A0 is used to
select even bank and control signal 𝐁𝐇𝐄
is used to access odd bank
Uses a separate 16 bit address for I/O
mapped devices  can generate 216 =
64 k addresses.
Operates in two modes: minimum mode
and maximum mode, decided by the
signal at MN and 𝐌𝐗 pins.
22

Pins and Signals
8086 Microprocessor
24
Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are
multiplexed with data.
When AD lines are used to transmit
memory address the symbol A is used
instead of AD, for example A0-A15.
When data are transmitted over AD lines
the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are
multiplexed with status signals

Pins and Signals
8086 Microprocessor
25
Common signals
BHE (Active Low)/S7 (Output)
Bus High Enable/Status
It is used to enable data onto the most
significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation.
It is an output signal.
It is active when low.

Pins and Signals
8086 Microprocessor
26
Common signals
TEST
𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’
instruction.
8086 will enter a wait state after
execution of the WAIT instruction and
will resume execution only when the
𝐓𝐄𝐒𝐓 is made low by an active hardware.
This is used to synchronize an external
activity to the processor internal
operation.
READY
This is the acknowledgement from the
slow device or memory that they have
completed the data transfer.
The signal made available by the devices
is synchronized by the 8284A clock
generator to provide ready input to the
8086.
The signal is active high.

Pins and Signals
8086 Microprocessor
27
Common signals
RESET (Input)
Causes the processor to immediately
terminate its present activity.
The signal must be active HIGH for at
least four clock cycles.
CLK
The clock input provides the basic timing
for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.
INTR Interrupt Request
This is a triggered input. This is sampled
during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.
This signal is active high and internally
synchronized.

Pins and Signals
8086 Microprocessor
29
Min/ Max Pins
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.
In the minimum mode of operation the
microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.
In the maximum mode the 8086 can work
in multi-processor or co-processor
configuration.
Minimum or maximum mode operations
are decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates in
minimum mode otherwise it operates in
Maximum mode.

Pins and Signals
8086 Microprocessor
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied
to VCC (logic high)
8086 itself generates all the bus control signals
DT/𝐑 (Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers
𝐃𝐄𝐍 (Data Enable) Output signal from the processor
used as out put enable for the transceivers
ALE (Address Latch Enable) Used to demultiplex the
address and data lines using external latches
M/𝐈𝐎 Used to differentiate memory access and I/O
access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.
𝐖𝐑 Write control signal; asserted low Whenever
processor writes data to memory or I/O port
𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt
request is accepted by the processor, the output is
low on this line.
30
Minimum mode signals

Pins and Signals
8086 Microprocessor
HOLD Input signal to the processor form the bus masters
as a request to grant the control of the bus.
Usually used by the DMA controller to get the
control of the bus.
HLDA (Hold Acknowledge) Acknowledge signal by the
processor to the bus master requesting the control
of the bus through HOLD.
The acknowledge is asserted high, when the
processor accepts HOLD.
31
Minimum mode signals
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied
to VCC (logic high)
8086 itself generates all the bus control signals

Pins and Signals
8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)
Pins 24 -31 are reassigned
𝑺𝟎, 𝑺𝟏, 𝑺𝟐 Status signals; used by the 8086 bus controller to
generate bus timing and control signals. These are
decoded as shown.
32
Maximum mode signals

Pins and Signals
8086 Microprocessor
𝑸𝑺𝟎, 𝑸𝑺𝟏 (Queue Status) The processor provides the status
of queue in these lines.
The queue status can be used by external device to
track the internal status of the queue in 8086.
The output on QS0 and QS1 can be interpreted as
shown in the table.
33

Pins and Signals
8086 Microprocessor
𝐑𝐐/𝐆𝐓𝟎,
𝐑𝐐/𝐆𝐓𝟏
(Bus Request/ Bus Grant) These requests are used
by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.
These pins are bidirectional.
The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏
34
𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix
instruction.
Remains active until the completion of the
instruction prefixed by LOCK.
The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while
executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.

Architecture
8086 Microprocessor
36
Execution Unit (EU)
EU executes instructions that have
already been fetched by the BIU.
BIU and EU functions separately.
Bus Interface Unit (BIU)
BIU fetches instructions, reads data
from memory and I/O ports, writes
data to memory and I/ O ports.

Architecture
8086 Microprocessor
37
Dedicated Adder to generate
20 bit address
Four 16-bit segment
registers
Code Segment (CS)
Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Segment Registers >>

Architecture
8086 Microprocessor
38
Segment
Registers
8086’s 1-megabyte memory
is divided into segments of
up to 64K bytes each.
Programs obtain access to code
and data in the segments by
changing the segment register
content to point to the desired
segments.
The 8086 can directly address four
segments (256 K bytes within the 1
M byte of memory) at a particular
time.

Architecture
8086 Microprocessor
39
Segment
Registers
Code Segment Register
16-bit
CS contains the base or start of the current code segment; IP contains the
distance or offset from this address to the next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically shifting the contents of CS
4-bits to the left and then adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the contents of the CS
register multiplied by 16 and then offset is added provided by the IP.

Architecture
8086 Microprocessor
40
Segment
Registers
Data Segment Register
16-bit
Points to the current data segment; operands for most instructions are fetched
from this segment.
The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a 16-bit
displacement are used as offset for computing the 20-bit physical address.

Architecture
8086 Microprocessor
41
Segment
Registers
Stack Segment Register
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the Stack Segment (SS) and
the Stack Pointer (SP) for stack instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack address is calculated from
the Stack segment (SS) and the Base Pointer (BP).

Architecture
8086 Microprocessor
42
Segment
Registers
Extra Segment Register
16-bit
Points to the extra segment in which data (in excess of 64K pointed to by the DS)
is stored.
String instructions use the ES and DI to determine the 20-bit physical address for
the destination.

Architecture
8086 Microprocessor
43
Segment
Registers
Instruction Pointer
16-bit
Always points to the next instruction to be executed within
the currently executing code segment.
So, this register contains the 16-bit offset address pointing
to the next instruction code within the 64Kb of the code
segment area.
Its content is automatically incremented as the execution
of the next instruction takes place.

Architecture
8086 Microprocessor
44
A group of First-In-First-Out (FIFO)
in which up to 6 bytes of
instruction code are pre fetched
from the memory ahead of time.
This is done in order to speed up
the execution by overlapping
instruction fetch with execution.
This mechanism is known as
pipelining.
Instruction queue

Architecture
8086 Microprocessor
45
Some of the 16 bit registers can be
used as two 8 bit registers as :
AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL
DX can be used as DH and DL
Execution Unit (EU)
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
16-bit ALU for
performing arithmetic
and logic operation
Four general purpose
registers(AX, BX, CX, DX);
Pointer registers (Stack
Pointer, Base Pointer);
and
Index registers (Source
Index, Destination Index)
each of 16-bits

Architecture
8086 Microprocessor
46
EU
Registers
Accumulator Register (AX)
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word,
and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /
outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or
AL.
Execution Unit (EU)

Architecture
8086 Microprocessor
47
EU
Registers
Base Register (BX)
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word,
and BH contains the high-order byte.
This is the only general purpose register whose contents
can be used for addressing the 8086 memory.
All memory references utilizing this register content for
addressing use DS as the default segment register.
Execution Unit (EU)

Architecture
8086 Microprocessor
48
EU
Registers
Counter Register (CX)
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of
the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the
contents of CX as a counter.
Execution Unit (EU)
Example:
The instruction LOOP START automatically decrements
CX by 1 without affecting flags and will check if [CX] =
0.
If it is zero, 8086 executes the next instruction;
otherwise the 8086 branches to the label START.

Architecture
8086 Microprocessor
49
EU
Registers
Data Register (DX)
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.
When combined, DL register contains the low order byte of
the word, and DH contains the high-order byte.
Used to hold the high 16-bit result (data) in 16 X 16
multiplication or the high 16-bit dividend (data) before a
32 ÷ 16 division and the 16-bit reminder after division.
Execution Unit (EU)

Architecture
8086 Microprocessor
50
EU
Registers
Stack Pointer (SP) and Base Pointer (BP)
SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during
execution of instructions that involve the stack segment in
the external memory.
SP contents are automatically updated (incremented/
decremented) due to execution of a POP or PUSH
instruction.
BP contains an offset address in the current SS, which is
used by instructions utilizing the based addressing mode.
Execution Unit (EU)

Architecture
8086 Microprocessor
51
EU
Registers
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.
Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
Execution Unit (EU)

Architecture
8086 Microprocessor
52
EU
Registers
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.
Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
Execution Unit (EU)

Architecture
8086 Microprocessor
53
Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Carry Flag
This flag is set, when there is
a carry out of MSB in case of
addition or a borrow in case
of subtraction.
Parity Flag
This flag is set to 1, if the lower
byte of the result contains even
number of 1’s ; for odd number
of 1’s set to zero.
Auxiliary Carry Flag
This is set, if there is a carry from the
lowest nibble, i.e, bit three during
addition, or borrow for the lowest
nibble, i.e, bit three, during
subtraction.
Zero Flag
This flag is set, if the result of
the computation or comparison
performed by an instruction is
zero
Sign Flag
This flag is set, when the
result of any computation
is negative
Tarp Flag
If this flag is set, the processor
enters the single step execution
mode by generating internal
interrupts after the execution of
each instruction
Interrupt Flag
Causes the 8086 to recognize
external mask interrupts; clearing IF
disables these interrupts.
Direction Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest
address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address
towards the lowest address, i.e., auto incrementing mode.
Over flow Flag
This flag is set, if an overflow occurs, i.e, if the result of a signed
operation is large enough to accommodate in a destination
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit
sign operations, then the overflow will be set.
Execution Unit (EU)

54
Architecture
8086 Microprocessor
Sl.No. Type Register width Name of register
1 General purpose register 16 bit AX, BX, CX, DX
8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register
8086 registers
categorized
into 4 groups
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF

55
Architecture
8086 Microprocessor
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations
BX Base register Used to hold base value in base addressing mode to access memory
data
CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP instructions
DX Data Register Used to hold data for multiplication and division operations
SP Stack Pointer Used to hold the offset address of top stack memory
BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory
SI Source Index Used to hold index value of source operand (data) for string
instructions
DI Data Index Used to hold the index value of destination operand (data) for string
operations
Registers and Special Functions

ADDRESSING MODES
&
Instruction set

Introduction
57
8086 Microprocessor
Program
A set of instructions written to solve a problem.
Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.
Computer language
High Level Low Level
Machine Language Assembly Language
 Binary bits  English Alphabets
 ‘Mnemonics’
 Assembler Mnemonics 
Machine Language

Group I : Addressing modes for register and
immediate data
Group IV : Relative Addressing mode
Group V : Implied Addressing mode
Group III : Addressing modes for I/O ports
Group II : Addressing modes for memory data
Addressing Modes
60
8086 Microprocessor
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted
in an instruction are known as addressing modes.
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing

Addressing Modes
61
8086 Microprocessor
5. Based Addressing
The instruction will specify the name of the
register which holds the data to be operated by
the instruction.
Example:
MOV CL, DH
The content of 8-bit register DH is moved to
another 8-bit register CL
(CL)  (DH)
immediate data

Addressing Modes
62
8086 Microprocessor
5. Based Addressing
In immediate addressing mode, an 8-bit or 16-bit
data is specified as part of the instruction
Example:
MOV DL, 08H
The 8-bit data (08H) given in the instruction is
moved to DL
(DL)  08H
MOV AX, 0A9FH
The 16-bit data (0A9FH) given in the instruction is
moved to AX register
(AX)  0A9FH
immediate data

Addressing Modes : Memory Access
64
8086 Microprocessor
20 Address lines  8086 can address up to 220 = 1M bytes
of memory
However, the largest register is only 16 bits
Physical Address will have to be calculated Physical Address :
Actual address of a byte in memory. i.e. the value which goes out
onto the address bus.
Memory Address represented in the form – Seg : Offset (Eg
- 89AB:F012)
Each time the processor wants to access memory, it takes the
contents of a segment register, shifts it one hexadecimal place to
the left (same as multiplying by 1610), then add the required
offset to form the 20- bit address
89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)
F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
16 bytes of contiguous
memory

Addressing Modes
66
8086 Microprocessor
5. Based Addressing
Here, the effective address of the memory
location at which the data operand is stored is
given in the instruction.
The effective address is just a 16-bit number
written directly in the instruction.
Example:
MOV BX, [1354H]
MOV BL, [0400H]
The square brackets around the 1354H denotes
the contents of the memory location. When
executed, this instruction will copy the contents of
the memory location into BX register.
This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
Group II : Addressing modes for memory
data

Addressing Modes
67
8086 Microprocessor
5. Based Addressing
In Register indirect addressing, name of the
register which holds the effective address (EA)
will be specified in the instruction.
Registers used to hold EA are any of the following
registers:
BX, BP, DI and SI.
Content of the DS register is used for base
address calculation.
Example:
MOV CX, [BX]
Operations:
EA = (BX)
BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA +1)
data
Note : Register/ memory
enclosed in brackets refer to
content of register/ memory

Addressing Modes
68
8086 Microprocessor
5. Based Addressing
In Based Addressing, BX or BP is used to hold the
base value for effective address and a signed 8-bit
or unsigned 16-bit displacement will be specified
in the instruction.
In case of 8-bit displacement, it is sign extended
to 16-bit before adding to the base value.
When BX holds the base value of EA, 20-bit
physical address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS is
used.
Example:
MOV AX, [BX + 08H]
Operations:
0008H  08H (Sign extended)
EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA
(AX)  (MA) or,
(AL)  (MA)
(AH)  (MA + 1)
data

Addressing Modes
69
8086 Microprocessor
5. Based Addressing
SI or DI register is used to hold an index value for
memory data and a signed 8-bit or unsigned 16-
bit displacement will be specified in the
instruction.
Displacement is added to the index value in SI or
DI register to obtain the EA.
In case of 8-bit displacement, it is sign extended
to 16-bit before adding to the base value.
Example:
MOV CX, [SI + 0A2H]
Operations:
FFA2H  A2H (Sign extended)
EA = (SI) + FFA2H
BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA + 1)
data

Addressing Modes
70
8086 Microprocessor
5. Based Addressing
In Based Index Addressing, the effective address
is computed from the sum of a base register (BX
or BP), an index register (SI or DI) and a
displacement.
Example:
MOV DX, [BX + SI + 0AH]
Operations:
000AH  0AH (Sign extended)
EA = (BX) + (SI) + 000AH
BA = (DS) x 1610
MA = BA + EA
(DX)  (MA) or,
(DL)  (MA)
(DH)  (MA + 1)
data

Addressing Modes
71
8086 Microprocessor
5. Based Addressing
Employed in string operations to operate on string
data.
The effective address (EA) of source data is stored
in SI register and the EA of destination is stored in
DI register.
Segment register for calculating base address of
source data is DS and that of the destination data
is ES
Example: MOVS BYTE
Operations:
Calculation of source memory location:
EA = (SI) BA = (DS) x 1610 MA = BA + EA
Calculation of destination memory location:
EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
(MAE)  (MA)
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) + 1
data
Note : Effective address of the
Extra segment register

Addressing Modes
8086 Microprocessor
5. Based Addressing
These addressing modes are used to access data
from standard I/O mapped devices or ports.
In direct port addressing mode, an 8-bit port
address is directly specified in the instruction.
Example: IN AL, [09H]
Operations: PORTaddr = 09H
(AL)  (PORT)
Content of port with address 09H is
moved to AL register
In indirect port addressing mode, the instruction
will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
is stored in the DX register.
Example: OUT [DX], AX
Operations: PORTaddr = (DX)
(PORT)  (AX)
Content of AX is moved to port
whose address is specified by DX
register. 72
Group III : Addressing modes for I/O
ports

Addressing Modes
73
8086 Microprocessor
5. Based Addressing
In this addressing mode, the effective address of
a program instruction is specified relative to
Instruction Pointer (IP) by an 8-bit signed
displacement.
Example: JZ 0AH
Operations:
000AH  0AH (sign extend)
If ZF = 1, then
EA = (IP) + 000AH
BA = (CS) x 1610
MA = BA + EA
If ZF = 1, then the program control jumps to
new address calculated above.
If ZF = 0, then next instruction of the
program is executed.
Group IV : Relative Addressing
mode

Addressing Modes
74
8086 Microprocessor
5. Based Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
operated by the instruction.
Example: CLC
This clears the carry flag to zero.
Group IV : Implied Addressing
mode

1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. String manipulation Instructions
5. Process Control Instructions
6. Control Transfer Instructions
Instruction Set
76
8086 Microprocessor
8086 supports 6 types of instructions.

Instruction Set
77
8086 Microprocessor
Instructions that are used to transfer data/ address in to registers, memory
locations and I/O ports.
Generally involve two operands: Source operand and Destination operand of the
same size.
Source: Register or a memory location or an immediate data
Destination : Register or a memory location.
The size should be a either a byte or a word.
A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit data can be
moved to 16-bit register/ memory.

Instruction Set
78
8086 Microprocessor
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
MOV reg2/ mem, reg1/ mem
MOV reg2, reg1
MOV mem, reg1
MOV reg2, mem
(reg2)  (reg1)
(mem)  (reg1)
(reg2)  (mem)
MOV reg/ mem, data
MOV reg, data
MOV mem, data
(reg)  data
(mem)  data
XCHG reg2/ mem, reg1
XCHG reg2, reg1
XCHG mem, reg1
(reg2)  (reg1)
(mem)  (reg1)

Instruction Set
79
8086 Microprocessor
PUSH reg16/ mem
PUSH reg16
PUSH mem
(SP)  (SP) – 2
MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)
(SP)  (SP) – 2
MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)
POP reg16/ mem
POP reg16
POP mem
MA S = (SS) x 1610 + SP
(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2
MA S = (SS) x 1610 + SP
(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2

Instruction Set
80
8086 Microprocessor
IN A, [DX]
IN AL, [DX]
IN AX, [DX]
PORTaddr = (DX)
(AL)  (PORT)
PORTaddr = (DX)
(AX)  (PORT)
IN A, addr8
IN AL, addr8
IN AX, addr8
(AL)  (addr8)
(AX)  (addr8)
OUT [DX], A
OUT [DX], AL
OUT [DX], AX
PORTaddr = (DX)
(PORT)  (AL)
PORTaddr = (DX)
(PORT)  (AX)
OUT addr8, A
OUT addr8, AL
OUT addr8, AX
(addr8)  (AL)
(addr8)  (AX)

Instruction Set
81
8086 Microprocessor
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD reg2/ mem, reg1/mem
ADC reg2, reg1
ADC reg2, mem
ADC mem, reg1
(reg2)  (reg1) + (reg2)
(reg2)  (reg2) + (mem)
(mem)  (mem)+(reg1)
ADD reg/mem, data
ADD reg, data
ADD mem, data
(reg)  (reg)+ data
(mem)  (mem)+data
ADD A, data
ADD AL, data8
ADD AX, data16
(AL)  (AL) + data8
(AX)  (AX) +data16

Instruction Set
82
8086 Microprocessor
ADC reg2/ mem, reg1/mem
ADC reg2, reg1
ADC reg2, mem
ADC mem, reg1
(reg2)  (reg1) + (reg2)+CF
(reg2)  (reg2) + (mem)+CF
(mem)  (mem)+(reg1)+CF
ADC reg/mem, data
ADC reg, data
ADC mem, data
(reg)  (reg)+ data+CF
(mem)  (mem)+data+CF
ADDC A, data
ADD AL, data8
ADD AX, data16
(AL)  (AL) + data8+CF
(AX)  (AX) +data16+CF

Instruction Set
83
8086 Microprocessor
SUB reg2/ mem, reg1/mem
SUB reg2, reg1
SUB reg2, mem
SUB mem, reg1
(reg2)  (reg1) - (reg2)
(reg2)  (reg2) - (mem)
(mem)  (mem) - (reg1)
SUB reg/mem, data
SUB reg, data
SUB mem, data
(reg)  (reg) - data
(mem)  (mem) - data
SUB A, data
SUB AL, data8
SUB AX, data16
(AL)  (AL) - data8
(AX)  (AX) - data16

Instruction Set
84
8086 Microprocessor
SBB reg2/ mem, reg1/mem
SBB reg2, reg1
SBB reg2, mem
SBB mem, reg1
(reg2)  (reg1) - (reg2) - CF
(reg2)  (reg2) - (mem)- CF
(mem)  (mem) - (reg1) –CF
SBB reg/mem, data
SBB reg, data
SBB mem, data
(reg)  (reg) – data - CF
(mem)  (mem) - data - CF
SBB A, data
SBB AL, data8
SBB AX, data16
(AL)  (AL) - data8 - CF
(AX)  (AX) - data16 - CF

Instruction Set
85
8086 Microprocessor
INC reg/ mem
INC reg8
INC reg16
INC mem
(reg8)  (reg8) + 1
(reg16)  (reg16) + 1
(mem)  (mem) + 1
DEC reg/ mem
DEC reg8
DEC reg16
DEC mem
(reg8)  (reg8) - 1
(reg16)  (reg16) - 1
(mem)  (mem) - 1

Instruction Set
86
8086 Microprocessor
MUL reg/ mem
MUL reg
MUL mem
For byte : (AX)  (AL) x (reg8)
For word : (DX)(AX)  (AX) x (reg16)
For byte : (AX)  (AL) x (mem8)
For word : (DX)(AX)  (AX) x (mem16)
IMUL reg/ mem
IMUL reg
IMUL mem
For byte : (AX)  (AL) x (reg8)
For word : (DX)(AX)  (AX) x (reg16)
For byte : (AX)  (AX) x (mem8)
For word : (DX)(AX)  (AX) x (mem16)

Instruction Set
87
8086 Microprocessor
DIV reg/ mem
DIV reg
DIV mem
For 16-bit :- 8-bit :
(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder
(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder
(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

Instruction Set
88
8086 Microprocessor
IDIV reg/ mem
IDIV reg
IDIV mem
(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder
(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder
(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

Instruction Set
89
8086 Microprocessor
CMP reg2/mem, reg1/ mem
CMP reg2, reg1
CMP reg2, mem
CMP mem, reg1
Modify flags  (reg2) – (reg1)
If (reg2) > (reg1) then CF=0, ZF=0, SF=0
If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0
Modify flags  (reg2) – (mem)
If (reg2) > (mem) then CF=0, ZF=0, SF=0
If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0
Modify flags  (mem) – (reg1)
If (mem) > (reg1) then CF=0, ZF=0, SF=0
If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

Instruction Set
90
8086 Microprocessor
CMP reg/mem, data
CMP reg, data
CMP mem, data
Modify flags  (reg) – (data)
If (reg) > data then CF=0, ZF=0, SF=0
If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0
Modify flags  (mem) – (mem)
If (mem) > data then CF=0, ZF=0, SF=0
If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

Instruction Set
91
8086 Microprocessor
CMP A, data
CMP AL, data8
CMP AX, data16
Modify flags  (AL) – data8
If (AL) > data8 then CF=0, ZF=0, SF=0
If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0
Modify flags  (AX) – data16
If (AX) > data16 then CF=0, ZF=0, SF=0
If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

Instruction Set
92
8086 Microprocessor
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

Instruction Set
93
8086 Microprocessor

Instruction Set
94
8086 Microprocessor

Instruction Set
95
8086 Microprocessor

Instruction Set
96
8086 Microprocessor

Instruction Set
97
8086 Microprocessor

Instruction Set
98
8086 Microprocessor

Instruction Set
99
8086 Microprocessor

4. String Manipulation Instructions
Instruction Set
100
8086 Microprocessor
 String : Sequence of bytes or words
 8086 instruction set includes instruction for string movement, comparison, scan, load and store.
 REP instruction prefix : used to repeat execution of string instructions
 String instructions end with S or SB or SW. S represents string, SB string
byte and SW string word.
 Offset or effective address of the source operand is stored in SI register and that of the destination
operand is stored in DI register.
 Depending on the status of DF, SI and DI registers are automatically updated.
 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.
 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

Instruction Set
101
8086 Microprocessor
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP
REPZ/ REPE
(Repeat CMPS or SCAS until ZF = 0)
REPNZ/ REPNE
(Repeat CMPS or SCAS until ZF = 1)
While CX  0 and ZF = 1, repeat execution of string instruction
and
(CX)  (CX) – 1
While CX  0 and ZF = 0, repeat execution of string instruction
and
(CX)  (CX) - 1

Instruction Set
102
8086 Microprocessor
MOVS
MOVSB
MOVSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
(MAE)  (MA)
If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1)  (MA; MA + 1)

Instruction Set
103
8086 Microprocessor
CMPS
CMPSB
CMPSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
Modify flags  (MA) - (MAE)
If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0
If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0
For byte operation
For word operation
Compare two string byte or string word

Instruction Set
104
8086 Microprocessor
SCAS
SCASB
SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0
If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 1
If DF = 1, then (DI)  (DI) – 1
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0
If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 2
If DF = 1, then (DI)  (DI) – 2
Scan (compare) a string byte or word with accumulator

Instruction Set
105
8086 Microprocessor
LODS
LODSB
LODSW
MA = (DS) x 1610 + (SI)
(AL)  (MA)
If DF = 0, then (SI)  (SI) + 1
If DF = 1, then (SI)  (SI) – 1
MA = (DS) x 1610 + (SI)
(AX)  (MA ; MA + 1)
If DF = 0, then (SI)  (SI) + 2
If DF = 1, then (SI)  (SI) – 2
Load string byte in to AL or string word in to AX

Instruction Set
106
8086 Microprocessor
STOS
STOSB
STOSW
MAE = (ES) x 1610 + (DI)
(MAE)  (AL)
If DF = 0, then (DI)  (DI) + 1
If DF = 1, then (DI)  (DI) – 1
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1 )  (AX)
If DF = 0, then (DI)  (DI) + 2
If DF = 1, then (DI)  (DI) – 2
Store byte from AL or word from AX in to string

Mnemonics Explanation
STC Set CF  1
CLC Clear CF  0
CMC Complement carry CF  CF/
STD Set direction flag DF  1
CLD Clear direction flag DF  0
STI Set interrupt enable flag IF  1
CLI Clear interrupt enable flag IF  0
NOP No operation
HLT Halt after interrupt is set
WAIT Wait for TEST pin active
ESC opcode mem/ reg Used to pass instruction to a coprocessor which shares the
address and data bus with the 8086
LOCK Lock bus during next instruction
5. Processor Control Instructions
Instruction Set
107
8086 Microprocessor

Instruction Set
108
8086 Microprocessor
Transfer the control to a specific destination or target instruction
Do not affect flags
CALL reg/ mem/ disp16 Call subroutine
RET Return from subroutine
JMP reg/ mem/ disp8/ disp16 Unconditional jump
 8086 Unconditional transfers

Instruction Set
109
8086 Microprocessor
 8086 signed conditional branch
instructions
 8086 unsigned conditional branch
instructions
Checks flags
If conditions are true, the program control is transferred to the new
memory location in the same segment by modifying the content of IP

Instruction Set
110
8086 Microprocessor
Name Alternate name
JE disp8
Jump if equal
JZ disp8
Jump if result is 0
JNE disp8
Jump if not equal
JNZ disp8
Jump if not zero
JG disp8
Jump if greater
JNLE disp8
Jump if not less or equal
JGE disp8
Jump if greater than or
equal
JNL disp8
Jump if not less
JL disp8
Jump if less than
JNGE disp8
Jump if not greater than
or equal
JLE disp8
Jump if less than or
equal
JNG disp8
Jump if not greater
 8086 signed conditional branch
instructions
 8086 unsigned conditional branch
instructions
Name Alternate name
JE disp8
Jump if equal
JZ disp8
Jump if result is 0
JNE disp8
Jump if not equal
JNZ disp8
Jump if not zero
JA disp8
Jump if above
JNBE disp8
Jump if not below or
equal
JAE disp8
Jump if above or equal
JNB disp8
Jump if not below
JB disp8
Jump if below
JNAE disp8
Jump if not above or
equal
JBE disp8
Jump if below or equal
JNA disp8
Jump if not above

Instruction Set
111
8086 Microprocessor
JC disp8 Jump if CF = 1
JNC disp8 Jump if CF = 0
JP disp8 Jump if PF = 1
JNP disp8 Jump if PF = 0
JO disp8 Jump if OF = 1
JNO disp8 Jump if OF = 0
JS disp8 Jump if SF = 1
JNS disp8 Jump if SF = 0
JZ disp8 Jump if result is zero, i.e, Z = 1
JNZ disp8 Jump if result is not zero, i.e, Z = 1
 8086 conditional branch instructions affecting individual flags

Assemble Directives
113
8086 Microprocessor
Instructions to the Assembler regarding the program being executed.
Control the generation of machine codes and organization of the program; but no
machine codes are generated for assembler directives.
Also called ‘pseudo instructions’
Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..

Assemble Directives
114
8086 Microprocessor
Define Byte
Define a byte type (8-bit) variable
Reserves specific amount of memory locations to each
variable
Range : 00H – FFH for unsigned value; 00H – 7FH for
positive value and 80H – FFH for negative value
General form : variable DB value/ values
Example:
LIST DB 7FH, 42H, 35H
Three consecutive memory locations are reserved for the variable LIST
and each data specified in the instruction are stored as initial value in
the reserved memory location
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM

Assemble Directives
115
8086 Microprocessor
Define Word
Define a word type (16-bit) variable
Reserves two consecutive memory locations to each variable
Range : 0000H – FFFFH for unsigned value; 0000H –
7FFFH for positive value and 8000H – FFFFH for negative
value
General form : variable DW value/ values
Example:
ALIST DW 6512H, 0F251H, 0CDE2H
Six consecutive memory locations are reserved for the variable ALIST and
each 16-bit data specified in the instruction is stored in two consecutive
memory location.
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM

Assemble Directives
116
8086 Microprocessor
SEGMENT : Used to indicate the beginning of a code/ data/
stack segment
ENDS : Used to indicate the end of a code/ data/ stack
segment
General form:
Segnam SEGMENT
…
…
…
…
…
…
Segnam ENDS
Program code
or
Data Defining Statements
User defined name of the
segment
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM

Assemble Directives
117
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM
Informs the assembler the name of the program/ data
segment that should be used for a specific segment.
General form:
Segment Register
ASSUME segreg : segnam, .. , segreg : segnam
segment
ASSUME CS: ACODE, DS:ADATA Tells the compiler that the instructions of the
program are stored in the segment ACODE and
data are stored in the segment ADATA
Example:

Assemble Directives
118
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM
ORG (Origin) is used to assign the starting address (Effective address)
for a program/ data segment
END is used to terminate a program; statements after END will be
ignored
EVEN : Informs the assembler to store program/ data segment
starting from an even address
EQU (Equate) is used to attach a value to a variable
ORG 1000H Informs the assembler that the statements following ORG
1000H should be stored in memory starting with effective
address 1000H
LOOP EQU 10FEH Value of variable LOOP is 10FEH
_SDATA SEGMENT
ORG 1200H
A DB 4CH
EVEN
B DW 1052H
_SDATA ENDS
In this data segment, effective address of memory location
assigned to A will be 1200H and that of B will be 1202H and
1203H.
Examples:

Assemble Directives
119
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM
PROC Indicates the beginning of a procedure
ENDP End of procedure
FAR Intersegment call
NEAR Intrasegment call
General form
procname PROC[NEAR/ FAR]
…
…
…
RET
procname ENDP
Program statements of the procedure
Last statement of the procedure
procedure

Assemble Directives
120
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM
ADD64 PROC NEAR
…
…
…
RET
ADD64 ENDP
The subroutine/ procedure named ADD64 is declared as
NEAR and so the assembler will code the CALL and RET
instructions involved in this procedure as near call and
return
CONVERT PROC FAR
…
…
…
RET
CONVERT ENDP
The subroutine/ procedure named CONVERT is declared as
FAR and so the assembler will code the CALL and RET
instructions involved in this procedure as far call and return
Examples:

Assemble Directives
121
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM
Reserves one memory location for 8-bit signed displacement
in jump instructions
JMP SHORT AHEAD The directive will reserve one memory location
for 8-bit displacement named AHEAD
Example:

Assemble Directives
122
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM
MACRO Indicate the beginning of a macro
ENDM End of a macro
General form:
macroname MACRO[Arg1, Arg2 ...]
…
…
…
macroname ENDM
Program statements
in the macro
User defined name of the macro

Interfacing memory and i/o ports

Memory
125
8086 Microprocessor
Memory
Processor Memory
Primary or Main Memory
Secondary Memory
Store Programs
and Data
 Registers inside a microcomputer
 Store data and results temporarily
 No speed disparity
 Cost 
 Storage area which can be directly accessed by
microprocessor
 Store programs and data prior to execution
 Should not have speed disparity with processor 
Semi Conductor memories using CMOS technology
 ROM, EPROM, Static RAM, DRAM
 Storage media comprising of slow devices such as
magnetic tapes and disks
 Hold large data files and programs: Operating
system, compilers, databases, permanent programs
etc.

Memory organization in 8086
126
8086 Microprocessor
Memory IC’s : Byte oriented
8086 : 16-bit
Word : Stored by two consecutive memory
locations; for LSB and MSB
Address of word : Address of LSB
Bank 0 : A0 = 0  Even addressed
memory bank
Bank 1 : 𝑩𝑯𝑬 = 0  Odd
addressed memory bank

127
8086 Microprocessor
Operation 𝑩𝑯𝑬 A0 Data Lines Used
1 Read/ Write byte at an even address 1 0 D7 – D0
2 Read/ Write byte at an odd address 0 1 D15 – D8
3 Read/ Write word at an even address 0 0 D15 – D0
4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation byte from
odd bank is transferred
1 0 D7 – D0 in first operation byte from
odd bank is transferred

128
8086 Microprocessor
Available memory space = EPROM + RAM
Allot equal address space in odd and even bank for both
EPROM and RAM
Can be implemented in two IC’s (one for even and other for
odd) or in multiple IC’s

Interfacing SRAM and EPROM
129
8086 Microprocessor
Memory interface  Read from and write in to a set of
semiconductor memory IC chip
EPROM  Read operations
RAM  Read and Write
In order to perform read/ write operations,
Memory access time  read / write time of the processor
Chip Select (CS) signal has to be generated
Control signals for read / write operations
Allot address for each memory location

130
8086 Microprocessor
Typical Semiconductor IC Chip
No of
Address pins
Memory capacity Range of address
in hexa
In Decimal In kilo In hexa
20 220= 10,48,576 1024 k = 1M 100000 00000
to
FFFFF

131
8086 Microprocessor
Memory map of 8086
RAM are mapped at the beginning; 00000H is allotted to RAM
EPROM’s are mapped at FFFFFH
 Facilitate automatic execution of monitor programs and creation of
interrupt vector table

132
8086 Microprocessor
Monitor Programs
 Programing 8279 for keyboard scanning and display refreshing
 Programming peripheral IC’s 8259, 8257, 8255, 8251, 8254 etc
 Initialization of stack
 Display a message on display (output)
 Initializing interrupt vector table
8279 Programmable keyboard/ display controller
8257 DMA controller
8259 Programmable interrupt controller
8255 Programmable peripheral interface
Note :

Interfacing I/O and peripheral devices
133
8086 Microprocessor
I/O devices
 For communication between microprocessor and outside world
 Keyboards, CRT displays, Printers, Compact Discs etc.

 Data transfer types
Microprocessor I/ O devices
Ports / Buffer IC’s
(interface circuitry)
Programmed I/ O
Data transfer is accomplished
through an I/O port controlled by
software
Interrupt driven I/ O
I/O device interrupts the processor and
initiate data transfer
Direct memory access
Data transfer is achieved by bypassing
the microprocessor
Memory mapped
I/O mapped

8086 and 8088 comparison
134
8086 Microprocessor
Memory mapping I/O mapping
20 bit address are provided for I/O devices 8-bit or 16-bit addresses are provided for I/O
devices
The I/O ports or peripherals can be treated like
memory locations and so all instructions related
to memory can be used for data transmission
between I/O device and processor
Only IN and OUT instructions can be used for data
transfer between I/O device and processor
Data can be moved from any register to ports
and vice versa
Data transfer takes place only between
accumulator and ports
When memory mapping is used for I/O devices,
full memory address space cannot be used for
addressing memory.
 Useful only for small systems where memory
requirement is less
Full memory space can be used for addressing
memory.
 Suitable for systems which require large
memory capacity
For accessing the memory mapped devices, the
processor executes memory read or write cycle.
 M / 𝐈𝐎 is asserted high
For accessing the I/O mapped devices, the
processor executes I/O read or write cycle.
 M / 𝐈𝐎 is asserted low

8086 and 8088 comparison
136
8086 Microprocessor
8086 8088
Similar EU and Instruction set ; dissimilar BIU
16-bit Data bus lines obtained by demultiplexing
AD0 – AD15
8-bit Data bus lines obtained by demultiplexing
AD0 – AD7
20-bit address bus 8-bit address bus
Two banks of memory each of 512 kb Single memory bank
6-bit instruction queue 4-bit instruction queue
Clock speeds: 5 / 8 / 10 MHz 5 / 8 MHz
In MIN mode, pin 28 is assigned the signal M /
𝐈𝐎
In MIN mode, pin 28 is assigned the signal IO / 𝐌
To access higher byte, 𝐁𝐇𝐄 signal is used No such signal required, since the data width is
only 1-byte

Co-processor – Intel 8087
138
8086 Microprocessor
Multiprocessor
system
A microprocessor system comprising of two or more processors
Distributed processing: Entire task is divided in to subtasks
Advantages Better system throughput by having more than one processor
Each processor have a local bus to access local memory or I/O devices so
that a greater degree of parallel processing can be achieved
System structure is more flexible. One can easily
add or remove modules to change the system configuration
without affecting the other modules in the system

139
8086 Microprocessor
Specially designed to take care of mathematical calculations involving
integer and floating point data
“Math coprocessor” or “Numeric Data Processor (NDP)”
Works in parallel with a 8086 in the maximum mode
8087
coprocessor
1) Can operate on data of the integer, decimal and real types with lengths
ranging from 2 to 10 bytes
2) Instruction set involves square root, exponential, tangent etc. in addition to
addition, subtraction, multiplication and division.
3) High performance numeric data processor  it can multiply two 64-bit real
numbers in about 27s and calculate square root in about 36 s
4) Follows IEEE floating point standard
5) It is multi bus compatible
Features

140
8086 Microprocessor
16 multiplexed address / data pins and 4
multiplexed address / status pins
Hence it can have 16-bit external data bus and 20-
bit external address bus like 8086
Processor clock, ready and reset signals are applied
as clock, ready and reset signals for coprocessor

141
8086 Microprocessor
BUSY signal from 8087 is connected to the 𝐓𝐄𝐒𝐓
input of 8086
If the 8086 needs the result of some computation
that the 8087 is doing before it can execute the
next instruction in the program, a user can tell
8086 with a WAIT instruction to keep looking at its
𝐓𝐄𝐒𝐓 pin until it finds the pin low
A low on the BUSY output indicates that the 8087
has completed the computation
BUSY

142
8086 Microprocessor
The request / grant signal from the 8087 is usually
connected to the request / grant (𝐑𝐐 / 𝐆𝐓𝟎 or 𝐑𝐐
/ 𝐆𝐓𝟏) pin of the 8086
𝐑𝐐 / 𝐆𝐓𝟎
The request / grant signal from the 8087 is usually
connected to the request / grant pin of the
independent processor such as 8089
𝐑𝐐 / 𝐆𝐓𝟏

143
8086 Microprocessor
The interrupt pin is connected to the interrupt
management logic.
The 8087 can interrupt the 8086 through this
interrupt management logic at the time error
condition exists
INT

144
8086 Microprocessor
𝐒𝟎- 𝐒𝟐
𝐒𝟐 𝐒𝟏 𝐒𝟎 Status
1 0 0 Unused
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
QS0 – QS1
QS0 QS1 Status
0 0 No operation
0 1 First byte of opcode
from queue
1 0 Queue empty
1 1 Subsequent byte of
opcode from queue

145
8086 Microprocessor
8087 instructions
are inserted in
the 8086
program
8086 and 8087 reads
instruction bytes and puts
them in the respective queues
NOP
8087 instructions have 11011
as the MSB of their first code
byte
8087 keeps track for ESC
instruction by monitoring 𝑺𝟐 - 𝑺𝟎
and AD0 – AD15 of 8086.
Also keeps track of QS0 – QS1.
Q status 00; does nothing
Q status 01; 8087 compares the
five MSB bits with 11011
If there is a match, then the ESC
instruction is fetched and executed
by 8087
If there is error during decoding an
ESC instruction, 8087 sends an
interrupt request
Memory read/ write
Additional words : 𝑹𝑸- 𝑮𝑻𝟎
8087 BUSY pin high
𝑻𝑬𝑺𝑻
WAIT
Ref: Microprocessor, Atul P. Godse, Deepali A. Gode, Technical publications, Chap 11

146
8086 Microprocessor
ESC
Execute the 8086
instructions
WAIT
Monitor
8086/ 8088
Deactivate the host’s
TEST pin and execute
the specific operation
Activate the
TEST pin
Wake up the
coprocessor
Wake up the 8086/
8088
8086/ 8088 Coprocessor

Reference Book
“Microprocessor Architecture, Programming
and Applications with 8085”, 5thEdition,
Prentice Hall
by
Ramesh S. Goankar

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