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CSE 209
Computer Architecture
Design of an ALU
Saem Hasan
Lecturer
CSE, BUET
ALU and the Processor
 ALU stands for Arithmetic Logic Unit
 A part of the processor or CPU
Some Terminologies Revisiting
 Decoder, Encoder
2X4
Decoder
𝑋0
𝑋1
𝑌 0
𝑌 1
𝑌 2
𝑌 3
E
𝑋0
𝑋1
𝑋2
𝑋3
4X2
Encoder
E
𝑌 0
𝑌 1
Some Terminologies Revisiting
 DeMUX, MUX
1X4
DeMUX
𝑋0
𝑌 0
𝑌 1
𝑌 2
𝑌 3
𝑆1
𝑋0
𝑋1
𝑋2
𝑋3
4X1
MUX
𝑌 0
𝑆0 𝑆1 𝑆0
An ALU Unit
 Can perform both Arithmetic and Logic Operations
Arithmetic/Logical Operation
Which Operation/Function
Helps Function-select to add
more variants
Parallel Adder
 Parallel adder
 A number of full-adder circuits connected in cascade
1-bit Half Adder
1-bit Full Adder
𝐶𝑖𝑛
𝐶𝑜𝑢𝑡
Parallel Adders
 number of 1-bit full-adders are connected in cascade to form a -bit parallel adder
Arithmetic Operations by ALU
Arithmetic Operations by ALU
What are we doing?
 Keeping A fixed and changing B to generate different operations
 Changes in B
 Keeping B as it is
 Inverting all bits of B
 Changing each bit of B to 0
 Changing each bit of B to 1
 Let’s assume represents modified representation of and thus represents
 So, following 4 combinations can be obtained
 Keeping B as it is ()
 Inverting all bits of B ()
 Changing each bit of B to 0 ()
 Changing each bit of B to 1 ()
What are we doing?
 So Following 4 combinations can be obtained
 Keeping B as it is ()
 Inverting all bits of B ()
 Changing each bit of B to 0 ()
 Changing each bit of B to 1 ()
 +
Function Table
Modified
Function Table: Designer’s perspective
Modified
Function Table
Modified
Logic Diagram of an
independent
Arithmetic Circuit
Parallel
adder
Combinati
onal
Circuit
𝑋
𝑌
𝐴
𝐵
…
Selection
Variables
𝐶𝑖𝑛
Design Example
 Design an adder/subtractor circuit with one selection variable s and two
inputs A and B. When s=0, the circuit performs A+B. When s=1, the circuit
performs A-B by taking the 2’s complement of B.
 Functions
Parallel
adder
Combinati
onal
Circuit
𝑋
𝑌
𝐴
𝐵
…
Selection
Variables
𝐶𝑖𝑛
s
0
1
𝑌 𝑖=𝑠′
𝐵𝑖+𝑠 𝐵𝑖
′
=s⨁ 𝐵𝑖
s
0 0
1 1
𝐶𝑖𝑛=𝑠
Design Example
Designing a Logic Circuit
 We shall implement three basic logical operations (AND, OR and NOT)
and an XOR operation
Designing a Logic Circuit
 Let’s combine it with arithmetic operations
More Efficient Design
 Use already available arithmetic circuit and incorporate logical operations
 Procedure
 Design the arithmetic section independently
 Take the circuit, consider and determine which logic operations are
automatically generated from the arithmetic circuit
 Modify the circuit to incorporate required but not automatically generated logic
operations
More Efficient Design
 Use already available arithmetic circuit and incorporate logical operations
Incorporating remaining functions
 Unresolved cases
Automatically Obtained Required
1 0 0 0
1 1 0
Incorporating remaining functions
(A + K)
Final Boolean Functions
 Combining the arithmetic and logical cases, we get the final form of the
Boolean function as:
where C1 = Cin
Let’s See Another Example
 Derive the input equations (Xi, Yi and Zi) for the parallel adders to be used
in the ALU which satisfies the following functional design specification.
s2 s1 cin Required Functions
0 0 0 F = AB + C
0 0 1 F = AB + C + 1
0 1 0 F = AB
0 1 1 F = AB + 1
1 0 x F = (AB)’
1 1 x F = AB
Solution
s2 s1 cin X Y Z Required
Functions
0 0 0 AB C 0 F= AB + C
0 0 1 AB C 1 F = AB + C +1
0 1 0 AB 0 0 F = AB
0 1 1 AB 0 1 F = AB + 1
1 0 x F = (AB)’
1 1 x F = AB
Solution
 X = AB
 Y = s1’ C
 Z = ci
where c1 = cin
Solution
s2 s1 cin X Y Z Required
Functions
0 0 0 AB C 0 F= AB + C
0 0 1 AB C 1 F = AB + C +1
0 1 0 AB 0 0 F = AB
0 1 1 AB 0 1 F = AB + 1
1 0 x AB 1 x F = (AB)’
1 1 x AB 0 x F = AB
Solution
 X = AB
 Y = s1’ C
 Z = ci
where c1 = cin
 Then for logical operations,
 X = AB
 Y = s1’ C + s2 s1’
 Z = s2’ ci
Status Register
 Four bits represents four status bits
 C: Contains the output carry of the operation
 S: Contains the sign of the result of the operation
 Z: Indicates whether the -bit of the result is 0 or not
 V: Indicates any overflow has occurred due to the operation
 Status bits help to determine relationships among inputs
 Example:
 Compare the value of A with the value of B
 Determine the value of bit of an input
Status Register
Comparing two unsigned numbers
 Compare the value of A with the value of B
 Check the status bits (mainly C and Z) after the performing the following operation
Comparing two signed numbers
 Compare the value of A with the value of B
 Check the status bits (mainly Z, V and S) after the performing the following
operation
Effect of Output Carry
References
 Digital Logic and Computer Design by M. Morris Mano
 Chapter 9 (9.1-9.7)
Acknowledgements
 These slides contain material developed and copyright by:
 Lecture slides by Madhusudan Basak, Assistant Professor, CSE, BUET
Thank You 
We are looking for Questions!

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Arithmatic and logical Unit designing and Flag Derivation

  • 1. CSE 209 Computer Architecture Design of an ALU Saem Hasan Lecturer CSE, BUET
  • 2. ALU and the Processor  ALU stands for Arithmetic Logic Unit  A part of the processor or CPU
  • 3. Some Terminologies Revisiting  Decoder, Encoder 2X4 Decoder 𝑋0 𝑋1 𝑌 0 𝑌 1 𝑌 2 𝑌 3 E 𝑋0 𝑋1 𝑋2 𝑋3 4X2 Encoder E 𝑌 0 𝑌 1
  • 4. Some Terminologies Revisiting  DeMUX, MUX 1X4 DeMUX 𝑋0 𝑌 0 𝑌 1 𝑌 2 𝑌 3 𝑆1 𝑋0 𝑋1 𝑋2 𝑋3 4X1 MUX 𝑌 0 𝑆0 𝑆1 𝑆0
  • 5. An ALU Unit  Can perform both Arithmetic and Logic Operations Arithmetic/Logical Operation Which Operation/Function Helps Function-select to add more variants
  • 6. Parallel Adder  Parallel adder  A number of full-adder circuits connected in cascade
  • 9. Parallel Adders  number of 1-bit full-adders are connected in cascade to form a -bit parallel adder
  • 12. What are we doing?  Keeping A fixed and changing B to generate different operations  Changes in B  Keeping B as it is  Inverting all bits of B  Changing each bit of B to 0  Changing each bit of B to 1  Let’s assume represents modified representation of and thus represents  So, following 4 combinations can be obtained  Keeping B as it is ()  Inverting all bits of B ()  Changing each bit of B to 0 ()  Changing each bit of B to 1 ()
  • 13. What are we doing?  So Following 4 combinations can be obtained  Keeping B as it is ()  Inverting all bits of B ()  Changing each bit of B to 0 ()  Changing each bit of B to 1 ()  +
  • 15. Function Table: Designer’s perspective Modified
  • 17. Logic Diagram of an independent Arithmetic Circuit Parallel adder Combinati onal Circuit 𝑋 𝑌 𝐴 𝐵 … Selection Variables 𝐶𝑖𝑛
  • 18. Design Example  Design an adder/subtractor circuit with one selection variable s and two inputs A and B. When s=0, the circuit performs A+B. When s=1, the circuit performs A-B by taking the 2’s complement of B.  Functions Parallel adder Combinati onal Circuit 𝑋 𝑌 𝐴 𝐵 … Selection Variables 𝐶𝑖𝑛 s 0 1 𝑌 𝑖=𝑠′ 𝐵𝑖+𝑠 𝐵𝑖 ′ =s⨁ 𝐵𝑖 s 0 0 1 1 𝐶𝑖𝑛=𝑠
  • 20. Designing a Logic Circuit  We shall implement three basic logical operations (AND, OR and NOT) and an XOR operation
  • 21. Designing a Logic Circuit  Let’s combine it with arithmetic operations
  • 22. More Efficient Design  Use already available arithmetic circuit and incorporate logical operations  Procedure  Design the arithmetic section independently  Take the circuit, consider and determine which logic operations are automatically generated from the arithmetic circuit  Modify the circuit to incorporate required but not automatically generated logic operations
  • 23. More Efficient Design  Use already available arithmetic circuit and incorporate logical operations
  • 24. Incorporating remaining functions  Unresolved cases Automatically Obtained Required 1 0 0 0 1 1 0
  • 26. Final Boolean Functions  Combining the arithmetic and logical cases, we get the final form of the Boolean function as: where C1 = Cin
  • 27. Let’s See Another Example  Derive the input equations (Xi, Yi and Zi) for the parallel adders to be used in the ALU which satisfies the following functional design specification. s2 s1 cin Required Functions 0 0 0 F = AB + C 0 0 1 F = AB + C + 1 0 1 0 F = AB 0 1 1 F = AB + 1 1 0 x F = (AB)’ 1 1 x F = AB
  • 28. Solution s2 s1 cin X Y Z Required Functions 0 0 0 AB C 0 F= AB + C 0 0 1 AB C 1 F = AB + C +1 0 1 0 AB 0 0 F = AB 0 1 1 AB 0 1 F = AB + 1 1 0 x F = (AB)’ 1 1 x F = AB
  • 29. Solution  X = AB  Y = s1’ C  Z = ci where c1 = cin
  • 30. Solution s2 s1 cin X Y Z Required Functions 0 0 0 AB C 0 F= AB + C 0 0 1 AB C 1 F = AB + C +1 0 1 0 AB 0 0 F = AB 0 1 1 AB 0 1 F = AB + 1 1 0 x AB 1 x F = (AB)’ 1 1 x AB 0 x F = AB
  • 31. Solution  X = AB  Y = s1’ C  Z = ci where c1 = cin  Then for logical operations,  X = AB  Y = s1’ C + s2 s1’  Z = s2’ ci
  • 32. Status Register  Four bits represents four status bits  C: Contains the output carry of the operation  S: Contains the sign of the result of the operation  Z: Indicates whether the -bit of the result is 0 or not  V: Indicates any overflow has occurred due to the operation  Status bits help to determine relationships among inputs  Example:  Compare the value of A with the value of B  Determine the value of bit of an input
  • 34. Comparing two unsigned numbers  Compare the value of A with the value of B  Check the status bits (mainly C and Z) after the performing the following operation
  • 35. Comparing two signed numbers  Compare the value of A with the value of B  Check the status bits (mainly Z, V and S) after the performing the following operation
  • 37. References  Digital Logic and Computer Design by M. Morris Mano  Chapter 9 (9.1-9.7)
  • 38. Acknowledgements  These slides contain material developed and copyright by:  Lecture slides by Madhusudan Basak, Assistant Professor, CSE, BUET
  • 39. Thank You  We are looking for Questions!