Arm Cortex-A Comparison Table_v4.pdf
- 1. The Cortex-A series of applications processors provide a range of solutions for devices undertaking complex compute tasks, such as hosting a rich operating system (OS) platform, and supporting multiple software applications. Feature Cortex-A5 Cortex-A7 Cortex-A9† Cortex-A15† Cortex-A17† Architecture Armv7-A Armv7-A Armv7-A Armv7-A Armv7-A Main Extensions LPAE Virtualization LPAE Virtualization LPAE Virtualization Pipeline In order In order Out of order Out of order Out of order Superscalar No Partial Yes Yes Yes Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit TrustZone for Cortex-A Yes Yes Yes Yes Yes Neon and Floating Point Unit Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Included Floating Point Unit only Optional Optional Optional Optional Included Interrupt Controller Optional Integrated GIC v1 (MP only) Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GIC v2 Optional Integrated GIC v2 Bus Protocol AXI ACE AXI ACE or CHI ACE L1 I-Cache/D-Cache 4-64kB 8-64kB 16-64kB 32kB/ 32kB 32-64kB/ 32kB Arm Cortex-A Processor Comparison Table 1
- 2. Feature Cortex-A5 Cortex-A7 Cortex-A9† Cortex-A15† Cortex-A17† L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB L3 Cache N/A N/A N/A N/A N/A Dual Core Lock-Step (DCLS) No No No No No Functional Safety Support No No No No No CryptographyUnit No No No No No Error Code Correction (ECC)/Parity No No Optional Optional Yes Accelerator Coherency Port (ACP) Optional No Optional Optional Optional Peripheral Port No No No No No Generic Timer No Yes No Yes Yes Non-intrusive debug (trace) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) 2
- 3. Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57† Cortex-A65 Cortex- A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex- A76AE Cortex-A77 Cortex-A78 Cortex- A78AE Architecture Armv8-A (AArch32 only) Armv8-A (AArch64 only) Armv8-A Armv8-A Armv8.2-A Armv8-A Armv8.2-A (AArch64 only) Armv8.2-A (AArch64 only) Armv8-A Armv8-A Armv8.2-A Armv8.2-A (AArch32 at EL0 only) Armv8.2-A (AArch32 at EL0 only) Armv8.2-A (AArch32 at EL0 only) Armv8.2-A (AArch32 at EL0 only) Armv8.2-A (AArch32 at EL0 only) Main Extensions Armv8.1 extensions Armv8.2 extensions Armv8.3 (LDAPR instructions only) Armv8.4Dot Product Cryptography extensions RASextensions Armv8.1 extensions Armv8.2 extensions Armv8.3 (LDAPR instructions only) Armv8.4 Dot Product Cryptography extensions RAS extensions Armv8.1 extensions Armv8.2 extensions Armv8.3 (LDAPR instructions only) Armv8.4Dot Product Cryptography extensions RAS extensions Armv8.1 extensions Armv8.2 extensions Armv8.3 (LDAPR instructions only) Armv8.4Dot Product Cryptography extensions RAS extensions Armv8.1 extensions Armv8.2 extensions Armv8.3 (LDAPR instructions only) Armv8.4Dot Product Cryptography extensions RASextensions Armv8.1 extensions Armv8.2 extensions Armv8.3 (LDAPR instructions only) Armv8.4Dot Product Cryptography extensions RAS extensions Armv8.1 extensions Armv8.2 extensions Armv8.3 (LDAPR instructions only) Armv8.4Dot Product Cryptography extensions RAS extensions Armv8.1 extensions Armv8.2 extensions Armv8.3 (LDAPR instructions only) Armv8.4Dot Product Cryptography extensions RAS extensions Armv8.1 extensions Armv8.2 extensions Armv8.3 (LDAPR instructions only) Armv8.4Dot Product Cryptography extensions RAS extensions Pipeline In order In order In order In order In order Out of order Out of order Out of order Out of order Out of order Out of order Out of order Out of order Out of order Out of order Out of order Superscalar Partial Partial Partial Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 44-bit 40-bit 44-bit 40-bit 40-bit 40-bit 40-bit 48-bit TrustZone for Cortex-A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Neon and Floating Point Unit Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable)with DotProduct, andIEEEFP16 Included Included with Dot Product and IEEE FP16 Included with INT8 Dot Product and IEEE FP16 Included Included Included with INT8 Dot Product and IEEE FP16 Included with INT8 Dot Product and IEEE FP16 Included with INT8 Dot Product and IEEE FP16 Included with INT8 Dot Product and IEEE FP16 Included with INT8 Dot Product and IEEE FP16 Included with INT8 Dot Product and IEEE FP16 FloatingPoint Unitonly N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included Included Included Interrupt Controller External GICv3 External GICv3 External GICv3 External GICv3 External GICv4 External GICv3 External GICv4 External GICv4 External GICv3 External GICv3 External GICv3 External GICv4 External GICv4 External GICv4 External GICv4 External GICv4 3
- 4. Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57† Cortex-A65 Cortex- A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex- A76AE Cortex-A77 Cortex-A78 Cortex- A78AE Bus Protocol ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI L1 I-Cache/ D-Cache 8-64kB 8-64kB 8-64kB 8-64kB 8-64kB 48kB/ 32kB 16-64kB 16-64kB 48kB/ 32-64kB 32kB/ 32-64kB 64kB 64kB 64kB 64kB 64kB 64kB L2 Cache 128kB-1MB 128kB-1MB 128kB-1MB 128kB-2MB 64-256kB 512kB-2MB 64-256kB 64-256kB 512kB-4MB 256kB-8MB 256-512kB 128-512KB 128-512KB 256-512kB 256-512kB 256-512kB L3 Cache N/A N/A N/A N/A Optional 256kB-4MB N/A Optional 512kB-4MB Optional 512kB-4MB N/A N/A Optional 512kB-4MB Optional 512kB-4MB Optional 512kB-4MB Optional 512kB-4MB Optional 512kB-4MB Optional 512kB-4MB Dual Core Lock-Step (DCLS) No No No No No No No Yes (in Lock-mode) No No No No Yes (in Lock-mode) No No Yes Functional Safety Support Yes Yes Yes Yes ASILD Systematic1 Yes ASILD Systematic1 ASILD Systematic1 andASILD Diagnostic2 Yes No ASILD Systematic1 ASILD Systematic1 ASILD Systematic1 andASILD Diagnostic2 No ASILD Systematic1 ASILD Systematic1 andASILD Diagnostic2 Cryptography Unit Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Supported (with cryptography extensions) Error Code Correction (ECC)/Parity Optional Optional Optional Optional Optional Optional Optional Yes Optional Yes Optional Optional Yes Optional Optional Yes Accelerator Coherency Port (ACP) Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional Optional Optional Peripheral Port No No No No Optional No Optional Optional No No Optional Optional Optional Optional Optional Optional Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Non- intrusive debug (trace) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Included Included Included Included Included Included Included Included Included Included Included Included Included 4
- 5. Feature Cortex-A510 Cortex-A710 Architecture Armv9-A Armv9-A Main Extensions Up to Armv8.5 extensions SVE2 extension Memory Tagging Extension Cryptography extensions RAS extensions Up to Armv8.5 extensions SVE2 extension Memory Tagging Extension Cryptography extensions RAS extensions Pipeline In-order Out-of-order Superscalar Yes Yes Physical Addressing (PA) 40-bit 40-bit Security TrustZone, Secure-EL2 TrustZone, Secure-EL2 Neon, Floating Point Unit and SVE Included Included Floating Point Unit only Included Included Interrupt Controller GIC interface, GICv4.1 GIC interface, GICv4.1 Bus Protocol AMBA AXI5 or CHI.E AMBA AXI5 or CHI.E L1 I-Cache/D-Cache 32KB or 64KB 32KB or 64KB L2 Cache Optional,128KB, 192KB, 256KB, 384KB, 512KB 256KB or 512KB L3 Cache Optional, 256KB to 16MB Optional, 256KB to 16MB Dual Core Lock-Step (DCLS) No No Functional Safety Support No No Cryptography Unit Optional Optional Error Code Correction (ECC)/Parity Yes Yes Accelerator Coherency Port (ACP) Optional Optional Peripheral Port Optional Optional Generic Timer Armv9.0-A Armv9.0-A Non-intrusive debug (trace) Included Included 5
- 6. For more information, contact your Arm account manager today or explore the processors in more detail here: developer.arm.com/ip-products/processors/cortex-a The Arm trademarks featured in this presentation are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. www.arm.com/company/policies/trademarks © Arm Ltd. | Version 2021 † Arm products undergo continual development and improvement. These Cortex-A processors are no longer available to license and are included here for comparison purposes only. 1 Suitable for up to ASIL D systematic development 2 Contributes towards up to ASIL D hardware diagnostic metrics