Atomic Rules - Arkville DPDK Acceleration 20.08
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Arkville is a DPDK-aware packet conduit that provides FPGA acceleration of DPDK workloads. It consists of an open-source DPDK Poll Mode Driver software and an Arkville FPGA RTL IP core sold by Atomic Rules. Arkville enables zero-copy packet exchange between processor DPDK buffers and FPGA packet streams. It is used in smart NICs, network appliances, and DPDK accelerators to efficiently move packets between hardware and software. Arkville aims to push more processing to FPGA hardware while maintaining high throughput and low latency comparable to processor-only DPDK.
Atomic Rules - Arkville DPDK Acceleration 20.08
- 1. Arkville DPDK Acceleration Shep Siegel Atomic Rules LLC 1©2020 Atomic Rules LLC Shepard.Siegel@atomicrules.com Arkville DPDK Acceleration – Release 20.08 2020-09-05
- 2. AR Background • Providing FPGA Design Services since 2008 – Contributions to numerous Open-Source Projects – Over a decade of industrial-grade Engineering Solutions – Networking IP focus both at the Datacenter and Edge • Selling IP Core Products and Support since 2015 – UDP Offload Engine (2015) – Arkville DPDK-Aware Data Mover (2016) – TimeServo FPGA Coherent System Timer (2017) • Differentiation with Tools and Methodology • Broad and Agnostic set of Partners • Select list of Recurring Customers and Clients 2©2020 Atomic Rules LLC
- 3. Arkville: A DPDK Packet Conduit 3©2020 Atomic Rules LLC
- 4. Arkville: Why? • DPDK First – Not an Afterthought or Adaptation – Both Higher Throughput and Lower Latency • DPDK Aware – Push GPP cycles to specialized FPGA RTL gates – Zero-Copy GPP Driver = Lowest Possible Overhead • DPDK Acceleration – Certain workloads are better in RTL gateware – Arkville enables a HW/SW balanced approach 4©2020 Atomic Rules LLC
- 5. Arkville: Where? • Arkville is used as a building-block component in products and solutions such as – Smart-NIC Devices – Network Appliances – Including ZU+ and RFSoC – DPDK Accelerators (e.g. BBDEV, IPSEC) • Anywhere there is the need to efficiently exchange data between – Processor DPDK-MBUFs – FPGA AXI Packet Streams 5©2020 Atomic Rules LLC
- 6. Smart-NIC 6©2020 Atomic Rules LLC 6 Any Rate ENET MAC NIC H/W Offload RTL IP Arkville AXI HW Arkville DPDK PMD SW DPDK Applications GPP SW PCIe FPGA GPP AR Arkville HW/SW DPDK SW API AXI HW API
- 7. Network Appliance 7©2020 Atomic Rules LLC 7 Any Rate ENET MAC Appliance RTL IP Arkville AXI HW Arkville DPDK PMD SW Appliance GPP SW PCIe FPGA GPP AR Arkville HW/SW DPDK SW API AXI HW API
- 8. DPDK Accelerator 8©2020 Atomic Rules LLC 8 AXI Accelerator IP (BBDEV, IPSEC, etc.) Arkville AXI HW Arkville DPDK PMD SW DPDK Applications or fd.io/VPP Nodes GPP SW PCIe FPGA GPP AR Arkville HW/SW DPDK SW API AXI HW API
- 9. Arkville: How? • A Software and Gateware Combination: – Arkville DPDK Poll Mode Driver (DPDK PMD) • Open-Source BSD from The Linux Foundation • http://dpdk.org/doc/guides/nics/ark.html – Arkville FPGA RTL IP Core (AXI RTL IP) • Atomic Rules sells named-project and multi-project licenses • http://www.atomicrules.com/arkville • Arkville performs the data-mover work for products and solutions that require FPGA/GPP communication 9©2020 Atomic Rules LLC
- 10. 100 GbE DPDK Offload 10©2017 Atomic Rules LLC
- 11. High-Level Block Diagram 11©2020 Atomic Rules LLC
- 12. Arkville IPI Component 12©2020 Atomic Rules LLC Select the optimum number of Queue Pairs for your application
- 13. Over 150 Gbps Throughput 13©2020 Atomic Rules LLC
- 14. 1.25 us RTT/2 Latency 14©2020 Atomic Rules LLC
- 15. About Arkville Latency • By Itself, Arkville contributes just 100ns to the ingress/egress latency budget • Software: Arkville DPDK PMD: – Constant Time 20ns per packet (e5-2630v4) – Zero-Copy – No GPP Cycles moving packet data! • Hardware: Arkville AXI RTL IP: – 20 Cycles at 250 MHz = 80ns + 4ns/64B – Deterministic, store-and-forward 15©2020 Atomic Rules LLC
- 16. No memcpy() • Arkville is unique among DPDK Poll Mode Drivers in that packet data is landed zero-copy exactly in user-land memory – Zero CPU cycles are used by net/ark PMD for packet data movement – Result is a constant O(1) time for all packets that fit in a single mbuf (See next slide) • More CPU cycles for your application • Fewer CPU cores needed for same amount of work 16©2020 Atomic Rules LLC
- 17. Zero-Copy DPDK Driver 17©2020 Atomic Rules LLC
- 18. Zero Packets Dropped 1/2 18©2020 Atomic Rules LLC • Other DPDK implementations drop packets on ingress if receive path can not keep up – Complicated to cope with bursts – No guarantee of delivery • Arkville prefetches descriptors and provides a hardware READY indication for each queue – User gets to decide the behavior that suits their application’s unique needs – Arkville provides a guarantee of delivery
- 19. Zero Packets Dropped 2/2 19©2020 Atomic Rules LLC
- 20. Arkville Release Roadmap CY2020/2021 20©2020 Atomic Rules LLC Status as of September 5, 2020 Arkville 20.05 was our 13th quarterly GA release (based on DPDK 20.05) Arkville 20.08 is our 14th quarterly GA release (based on DPDK 20.08) Arkville 20.11 will be our 15th quarterly GA release (based on DPDK 20.11)
- 21. Shipped Release: 20.08 21©2020 Atomic Rules LLC • Ship Date: September 4, 2020 • Support for DPDK 20.08 • Support for Vivado 2020.2 • New Features – Meson/Ninja Build System • New Architecture Support for RFSoC • Enhanced Board Support for RFSoC
- 22. Planned Release: 20.20 22©2020 Atomic Rules LLC • Ship Date (Planned): December 2020 • Support for DPDK 20.11 • Support for Vivado 2020.2 • New Features • New Applications • New Architecture Support • Enhanced Board Support
- 23. Arkville Evaluation 23©2020 Atomic Rules LLC • Performance Evaluation from Atomic Rules… • Evaluate Arkville on-site with your own system components – Measure your own actual system-level performance • Atomic Rules provides pre-compiled bitstreams for your FPGA platform – 100 GbE (x1) and 10 GbE (x4) example designs • Download trusted, unmodified DPDK from dpdk.org • Run DPDK “testpmd” unmodified to observe – Packet Throughput, Latency, Packet Loss – Compare results to DPDK Labs reports • Run supplied AR DPDK examples for deeper insights • Run your own DPDK programs on the example designs
- 24. Questions / Feedback • Is FPGA acceleration of packet-based DPDK workloads of interest? • Are there specific challenges you are facing that perhaps Arkville will help solve? • How do you measure success? • Do you have a target platform in mind? • How would you like to get started? 24©2020 Atomic Rules LLC
- 25. Why Atomic Rules? • Our Engineers are Passionate about our Code – We are obsessed with correctness – We are committed to our customers – Small enough to care about every detail – Mature enough to have likely seen it before • IP License include Support and Maintenance – Four quarters of updates included – Support from the design team leaders 25©2020 Atomic Rules LLC
- 26. Summary and Thank You! 26©2020 Atomic Rules LLC • Arkville is a GPP/FPGA DPDK-Aware Conduit – Software is an Open-Source DPDK Poll Mode Driver • http://doc.dpdk.org/guides/nics/ark.html – RTL IP Core Gateware is sold by Atomic Rules • Named-Project and Site-Based Licenses are Available • Arkville is Agnostic – Support for Contemporary FPGA Devices – Support for COTS and Custom FPGA Boards • Arkville is Supported – Ongoing developments to the DPDK/LF Community – AR offers both HW and SW services and support
- 27. Backup Material 27©2020 Atomic Rules LLC
- 28. Application on RFSoC 28©2020 Atomic Rules LLC About 20% of a ZCU49 RFSoC Device for a 4-Queue Arkville Core – Including the Xilinx PCIe Endpoint Ideal for DPDK 5G BBDEV workloads to move baseband and digital-IF between S/W and H/W.
- 29. Application on ZU+ 29©2020 Atomic Rules LLC
- 30. Core Beliefs and Axioms 30©2020 Atomic Rules LLC • Our Customer’s Success is Key • Separation of Concerns • Divide and Conquer • Automate or Die • Write Things Once • Interface Before Implementation • Functional Correctness First • Performance Correctness Improved Iteratively • Components Must Compose • Components Must Work as Expected • IP Should be Portable, Vendor-Agnostic if possible
- 31. Partner Roster 31©2020 Atomic Rules LLC • 25G / 50G Ethernet Consortium • 25-50-100 Ethernet Alliance • Accellera/OCP-IP Community Member • Amazon F1 Instance Partner • ARM Connected Community Member • BittWare Solution Partner • Bluespec Technology Partner • DPDK Project Corporate Member • FPGA, FCCM and FPL ‘F’ Conference Sponsors • Intel Network Builders • Linux Foundation Corporate Member • MathWorks Connections Partner • NetFPGA Infrastructure Developer • OpenCPI Infrastructure Developer • P4 Language Consortium Member • PCI-SIG Corporate Member • VITA Trade Association Member • Xilinx Alliance Member Partner