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An Architecture Example A quick background review and one architecture example by Glen Wilson
Agenda Background review 10 min Architecture at DAFCA 35 min
Background review Boston University 1987 -1991 BS Computer Engineering BA Mathematics University Of Texas At Austin 1996 - 1997 MS Software Engineering Data General 1991 – 1993 Diagnostics Engineer Motorola 1993 – 1998 Verification Engineer PowerPC Chip Sets Verification Tools Developer Test case generator language Integrated verification and design system
Background review - Experience Ikos / Mentor Graphics 1998 – 2004 Mentor Emulator Division Member of Compiler Group Visibility Team Lead and Architect Architected complex runtime visibility system
Background review – Why Emulate Problem domain for emulation – SoC functional verification cost of silicon fabrication ~10M Speed of other solutions do not allow complex or large test cases Image from “The Value of Hardware Emulation” by Mitch Dale
Background review – Hardware Emulation SoC design is compiled into emulator ( large array of FPGAs ) Emulator is connected to a test board via the target chip IO Host machine connects to the emulator to load designs, set triggers, control the emulator, down load waveform data Test Board Host Machine Emulated chip IO HDL  description
Background review – Mentor Graphics What I worked on Architected complex runtime visibility system which includes:  Emulator raw data extraction software state replay  persistent and intermediate data caching Generic waveform display interface which included on demand and incremental waveform generation Trace data >1Tb Visibility Service
Background review – Combinational Replay All values of net in a combinational cloud are only dependent on current state and primary inputs. Therefore combinational nets can be recalculated and do not have to be captured in the emulator PI Combinational Cloud PO
Background review – Software State Replay Combinational replay predicts next state Therefore, given a state capture and the primary input values, only a fraction of the state values need to be stored on the emulator State Capture PI Cloud PO PI Cloud PO PI Cloud PO PI Cloud PO PI Cloud PO
Background review – Visibility Data Flow Data look up Retrieve from emulator or hit in cached data Decode Software state replay – sent to a compute server Feed to data requestor Visibility Service Cached data
Background review - Dafca DAFCA Inc.  2005 – 11/2008 Architect – Insertion Team Elevated the architecture from prototype to production. Atomic Architecture Command and template method patterns Critical abstraction, once done other concepts emerged Instruments and “wizards”
Background review – DAFCA Tool Flow Large customer design described in HDL is read in Specialized instruments are inserted into the design by ClearBlue Insertion Studio The design is synthesized and fabricated Instrumentation is controlled by ClearBlue Debug Studio through a standard test port HDL  description Insertion Studio HDL  description Debug Studio synthesis and fabrication
Architecture at DAFCA – Architecture Block Diagram Refined notion of command Implemented Command pattern Unified interface for all commands Used template method pattern to enforce pre and post condition checking Added layered architecture Atomic Actions Coordinators  Instruments Used the composite pattern Encapsulates the abstract instrument domain object Design Netlist Model Coordinator Commands TCL UI Atomic Commands Dispatcher GUI Instruments
Architecture At DAFCA ClearBlue Insertion Studio mission statement “ The purpose of the Insertion Studio is to  guide  and  enable  the user to  instrument  their  design  so that their desired validation and debug  capability  would be available post fabrication.” This mission statement evolved over time The highlighted domain concepts emerged along with the architecture.
DAFCA Insertion Mission Guide  and  Enable The user to  instrument  their  design Encapsulate and hide All of the DAFCA specific details Architecture was developed to address these two goals User Intent User Circuit DAFCA Circuit Guide  and  Enable encapsulate and hide
DAFCA Insertion Mission DAFCA Realized Circuit Access mechanism details Complicated instrument details Details of HDL manipulation User Intent User Circuit Guide  and  Enable encapsulate and hide DAFCA Circuit
Architecture at DAFCA – Command Pattern Command pattern Encapsulates an action into an object Ramifications of using the command pattern Encapsulates the command concept and provides a standard interface Is a natural concept in the domain Allows queuing of commands, or inverse commands for undo Inverse command, tcl command string all included in command object Coordinator Commands Atomic Commands Dispatcher DAFCA Circuit
Architecture at Dafca – Template Method Pattern We want our commands to follow assertion based design Commands need a guaranteed state prior to execution, which means both pre conditions and post conditions Template Method pattern embeds pre and post condition checking into the command execution class command { public: void execute ( ); virtual void exec ( ); } command::execute ( ) { check_preconditions ( ); exec ( ); check_postconditions ( ); }  DAFCA Circuit
Architecture at DAFCA – Template Method Pattern Ramifications of using the template method pattern Pre and post conditions were used heavily Important requirements were expressed Don’t connect power to ground Don’t create two drivers of one net The integrity of the pattern was self enforced by the team, it was a good fit in the domain The pre and post conditions enabled creation of very complex commands DAFCA Circuit
Architecture at DAFCA – Atomic Actions Has a closed set of atomic commands all atomic commands have inverses Coordinator commands have atomic actions and other coordinator actions enables a way for composing the inverse of complicated commands and enabling undo. Coordinator commands were created to encapsulate the details of DAFCA implementation Design Netlist Model Coordinator Commands Atomic Commands DAFCA Circuit
DAFCA Insertion Mission User intent 10 – 60 million gate SoC designs Multi core, multi team 3 rd  party cores Signal probe sizes up to 10,000 Trade off between functionality and chip real estate Debug strategy User Intent User Circuit DAFCA Circuit Guide  and  Enable encapsulate and hide
DAFCA Insertion Mission User circuit Intent is mapped onto abstract instruments Identified probe signals get muxed down to an on chip logic analyzer (osciliscope) Real estate feedback User Intent DAFCA Circuit Guide  and  Enable encapsulate and hide User Circuit
Architecture at DAFCA – Instruments Instrument objects emerged that encapsulated:  Properties Construction Insertion Connection Used commands to accomplish the above Composite pattern used Enabled composition of instruments Common interface listed above User Circuit
Architecture at DAFCA – Instruments Ramifications of using the Composite pattern  A library of instruments sprang up Simple instruments were reused to build up more complicated instruments that represented user level concepts Instruments added the domain knowledge Properties, build, insert, connect User Circuit
DAFCA Insertion Mission Guide  and  Enable Instruments, Composite  Encapsulate and hide Commands Template Methods Atomic Action layered architecture User Intent User Circuit DAFCA Circuit Guide  and  Enable encapsulate and hide
Architecture at DAFCA – Domain Objects Highlighted in the GUI Benefit derived from new architecture Domain concepts and ideas are plainly and powerfully presented in the GUI: design, instruments, commands
Architecture at DAFCA – Design Domain Object in GUI Tree browser view of the design netlist with search and display pane showing
Architecture at DAFCA – Design Domain Object in GUI Schematic view of the design netlist
Architecture at DAFCA – Wrap Group Wizard Inserts one of three different wrappers Uses a coordinator command Creates an instrument Calls several other commands Relies on preconditions Can be undone TCL equivalent command is logged I developed this GUI
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Background And An Architecture Example

  • 1. An Architecture Example A quick background review and one architecture example by Glen Wilson
  • 2. Agenda Background review 10 min Architecture at DAFCA 35 min
  • 3. Background review Boston University 1987 -1991 BS Computer Engineering BA Mathematics University Of Texas At Austin 1996 - 1997 MS Software Engineering Data General 1991 – 1993 Diagnostics Engineer Motorola 1993 – 1998 Verification Engineer PowerPC Chip Sets Verification Tools Developer Test case generator language Integrated verification and design system
  • 4. Background review - Experience Ikos / Mentor Graphics 1998 – 2004 Mentor Emulator Division Member of Compiler Group Visibility Team Lead and Architect Architected complex runtime visibility system
  • 5. Background review – Why Emulate Problem domain for emulation – SoC functional verification cost of silicon fabrication ~10M Speed of other solutions do not allow complex or large test cases Image from “The Value of Hardware Emulation” by Mitch Dale
  • 6. Background review – Hardware Emulation SoC design is compiled into emulator ( large array of FPGAs ) Emulator is connected to a test board via the target chip IO Host machine connects to the emulator to load designs, set triggers, control the emulator, down load waveform data Test Board Host Machine Emulated chip IO HDL description
  • 7. Background review – Mentor Graphics What I worked on Architected complex runtime visibility system which includes: Emulator raw data extraction software state replay persistent and intermediate data caching Generic waveform display interface which included on demand and incremental waveform generation Trace data >1Tb Visibility Service
  • 8. Background review – Combinational Replay All values of net in a combinational cloud are only dependent on current state and primary inputs. Therefore combinational nets can be recalculated and do not have to be captured in the emulator PI Combinational Cloud PO
  • 9. Background review – Software State Replay Combinational replay predicts next state Therefore, given a state capture and the primary input values, only a fraction of the state values need to be stored on the emulator State Capture PI Cloud PO PI Cloud PO PI Cloud PO PI Cloud PO PI Cloud PO
  • 10. Background review – Visibility Data Flow Data look up Retrieve from emulator or hit in cached data Decode Software state replay – sent to a compute server Feed to data requestor Visibility Service Cached data
  • 11. Background review - Dafca DAFCA Inc. 2005 – 11/2008 Architect – Insertion Team Elevated the architecture from prototype to production. Atomic Architecture Command and template method patterns Critical abstraction, once done other concepts emerged Instruments and “wizards”
  • 12. Background review – DAFCA Tool Flow Large customer design described in HDL is read in Specialized instruments are inserted into the design by ClearBlue Insertion Studio The design is synthesized and fabricated Instrumentation is controlled by ClearBlue Debug Studio through a standard test port HDL description Insertion Studio HDL description Debug Studio synthesis and fabrication
  • 13. Architecture at DAFCA – Architecture Block Diagram Refined notion of command Implemented Command pattern Unified interface for all commands Used template method pattern to enforce pre and post condition checking Added layered architecture Atomic Actions Coordinators Instruments Used the composite pattern Encapsulates the abstract instrument domain object Design Netlist Model Coordinator Commands TCL UI Atomic Commands Dispatcher GUI Instruments
  • 14. Architecture At DAFCA ClearBlue Insertion Studio mission statement “ The purpose of the Insertion Studio is to guide and enable the user to instrument their design so that their desired validation and debug capability would be available post fabrication.” This mission statement evolved over time The highlighted domain concepts emerged along with the architecture.
  • 15. DAFCA Insertion Mission Guide and Enable The user to instrument their design Encapsulate and hide All of the DAFCA specific details Architecture was developed to address these two goals User Intent User Circuit DAFCA Circuit Guide and Enable encapsulate and hide
  • 16. DAFCA Insertion Mission DAFCA Realized Circuit Access mechanism details Complicated instrument details Details of HDL manipulation User Intent User Circuit Guide and Enable encapsulate and hide DAFCA Circuit
  • 17. Architecture at DAFCA – Command Pattern Command pattern Encapsulates an action into an object Ramifications of using the command pattern Encapsulates the command concept and provides a standard interface Is a natural concept in the domain Allows queuing of commands, or inverse commands for undo Inverse command, tcl command string all included in command object Coordinator Commands Atomic Commands Dispatcher DAFCA Circuit
  • 18. Architecture at Dafca – Template Method Pattern We want our commands to follow assertion based design Commands need a guaranteed state prior to execution, which means both pre conditions and post conditions Template Method pattern embeds pre and post condition checking into the command execution class command { public: void execute ( ); virtual void exec ( ); } command::execute ( ) { check_preconditions ( ); exec ( ); check_postconditions ( ); } DAFCA Circuit
  • 19. Architecture at DAFCA – Template Method Pattern Ramifications of using the template method pattern Pre and post conditions were used heavily Important requirements were expressed Don’t connect power to ground Don’t create two drivers of one net The integrity of the pattern was self enforced by the team, it was a good fit in the domain The pre and post conditions enabled creation of very complex commands DAFCA Circuit
  • 20. Architecture at DAFCA – Atomic Actions Has a closed set of atomic commands all atomic commands have inverses Coordinator commands have atomic actions and other coordinator actions enables a way for composing the inverse of complicated commands and enabling undo. Coordinator commands were created to encapsulate the details of DAFCA implementation Design Netlist Model Coordinator Commands Atomic Commands DAFCA Circuit
  • 21. DAFCA Insertion Mission User intent 10 – 60 million gate SoC designs Multi core, multi team 3 rd party cores Signal probe sizes up to 10,000 Trade off between functionality and chip real estate Debug strategy User Intent User Circuit DAFCA Circuit Guide and Enable encapsulate and hide
  • 22. DAFCA Insertion Mission User circuit Intent is mapped onto abstract instruments Identified probe signals get muxed down to an on chip logic analyzer (osciliscope) Real estate feedback User Intent DAFCA Circuit Guide and Enable encapsulate and hide User Circuit
  • 23. Architecture at DAFCA – Instruments Instrument objects emerged that encapsulated: Properties Construction Insertion Connection Used commands to accomplish the above Composite pattern used Enabled composition of instruments Common interface listed above User Circuit
  • 24. Architecture at DAFCA – Instruments Ramifications of using the Composite pattern A library of instruments sprang up Simple instruments were reused to build up more complicated instruments that represented user level concepts Instruments added the domain knowledge Properties, build, insert, connect User Circuit
  • 25. DAFCA Insertion Mission Guide and Enable Instruments, Composite Encapsulate and hide Commands Template Methods Atomic Action layered architecture User Intent User Circuit DAFCA Circuit Guide and Enable encapsulate and hide
  • 26. Architecture at DAFCA – Domain Objects Highlighted in the GUI Benefit derived from new architecture Domain concepts and ideas are plainly and powerfully presented in the GUI: design, instruments, commands
  • 27. Architecture at DAFCA – Design Domain Object in GUI Tree browser view of the design netlist with search and display pane showing
  • 28. Architecture at DAFCA – Design Domain Object in GUI Schematic view of the design netlist
  • 29. Architecture at DAFCA – Wrap Group Wizard Inserts one of three different wrappers Uses a coordinator command Creates an instrument Calls several other commands Relies on preconditions Can be undone TCL equivalent command is logged I developed this GUI
  • 30. Q&A