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An Introduction to Teseda
Fast and Intuitive Scan Defect Isolation




               Teseda Confidential
Who Is Teseda?
     Ensuring rapid diagnosis of design, process, or use
     related failures is the core of our business!
 •   Teseda’s products accelerate first silicon debug and shorten failure
     analysis and yield improvement turn-around time




 •   Teseda Solutions deliver:
       Fast Silicon Debug (Time To Market)
       Rapid Failure Analysis - Impacts time to production release and yield
        improvement




                                   Teseda Confidential
V520 Engineering Test System
 •   348 I/O pins
       50Mhz force and compare
       300 I/O pins, 32 clock pins,
        16 scan enable pins
       Full per-pin timing capability
 •   32M Per Pin Vector Depth
 •   DC Parametric
     Source/Measure Option
         Continuity, Leakage and Voltage
          measurements
         Fully automated SW control
 •   4 Internal DUT Power
     Supplies
         2 High Current (2A)
         2 Low Current (100mA)
 •   Driven by Teseda’s powerful
     Teseda WorkBench (TWB)
     DFT-Enabled Software



                                            Teseda Confidential
V550 Engineering Test System
•   512 I/O pins
      100Mhz force and compare
      Higher clock and data rates can be
       created with multiple edges per cycle
      Any pin can be I, O, I/O or Clock
      Full per-pin timing capability
•   64M Per Pin Vector Depth
•   DC Parametric Source/Measure Option
        Continuity, Leakage and Voltage
         measurements
        Fully automated SW control
•   7 Internal DUT Power Supplies
        4 High Current (4A)
        2 Low Current (250mA)
        1 High Voltage (25V)
•   Driven by Teseda’s powerful Teseda
    WorkBench (TWB) DFT-Enabled
    Software



                                           Teseda Confidential
Capabilities of Teseda Workbench
         Create New Tests Quickly                Execute Tests
         •    Import STIL files                  •       Functional or Scan Tests
         •    Set DC values                      •       Map failing scan cells to chain
         •    Compile and download tests                 and design instance
         •    Manage projects                    •       DC Tests (Continuity, IiL, VoH)
         •    Interactive, easy-to use           •       Iddq Tests
                                                 •       Shmoo Plots and Test Flows




     Perform Failure Analysis                        Export Scan Fail Logs
     •       Compare expect with actual              •   Save cycle or pattern format
     •       Loop on specific vectors                •   Synopsys or Mentor format
     •       Trigger output on events                •   Feed fail result logs to
     •       Designed to interface with                  diagnosis tools like NetXY,
             Emission Microscopes, LADA,                 YieldAssist and TetraMAX
             and other SDA tools




                                           Teseda Confidential
Teseda Workbench Features
•   Manages V550 or V520 hardware
•   STIL compiler
•   Set DC and AC timing values
•   Vector and timing waveform
    display
•   Run test settings – P/F mode, fail
    capture mode, full capture mode,
    loop vectors, set triggers, run with
    timing scale, etc.
•   Scan fail results processing and
    logging
•   Debug / Characterization Tools
        Chain plot tool
        Scan view / design view tool
        Shmoo plot tool
        DC measurement screen
        Iddq measurement screen
•   Manage test projects, archive,
    delete, etc.




                                           Teseda Confidential
Diagnostic Manager NetXY
      LEF/
      DEF



  STIL


 STIL - Test Pattern


 Failures


Scan Failures- From
 Test Pattern results


  • Diagnostic Manager NetXY diagnoses the cause of scan-captured failures within
         the physical design of the device
              Analyzes design, STIL vectors and scan failures
              Identifies the location of the fault on the physical layout
  •          Utilizes industry standards
                Standard Test Interface Language (STIL)
                Design Exchange Format (DEF)
                Library Exchange Format (LEF)
  • Interoperable with all major EDA DFT and diagnostic tools and flows

                                                   Teseda Confidential
Real Customer Example
Mapping Logical Fails to Physical
•   Four scan cells failing frequently
        A few neighboring infrequent failures
        Scan cells located in same logic block




                    TWB
                                                                    Diagnostic Manager NetXY


                                              Teseda Confidential
Scan Fail Diagnosis with NetXY
•   Show scan chain stitching order on the
    physical layout
•   Overlay scan flip flops capturing failures
    on the physical scan chain along with
    color map of fail density
•   Pathfinder design navigation tool -
    enables logic trace back from failing scan
    flip flops
•   Automated logic cone tracing back from
    failing scan flip flop
•   Automated scan chain tracing of the
    physical nets that connect between scan
    flip flops (useful in diagnosing chain fails)
•   Automated cone convergence
        identify the common intersection of multiple failing
         logic cones
•   Automated identification of the failing net

               Rapidly find the root cause of scan fails regardless of EDA vendor.
               Diagnose failures without requiring support from the design team.


                                                      Teseda Confidential
Teseda in Failure Analysis
Diagnose = Localize + Isolate + Confirm

     Defect Localization


                                       V550                    V520




                                      Defect Isolation                           Teseda Workbench (TWB)
                                                                                    Fault Localization


Map test fail logs onto the
                                                                                                                    Diagnostic Manager
physical design                                                            Defect Confirmation                            NetXY
                                                                       Emission, LIVA, TIVA, OBIRCH, LADA
Identify scan cells with                                                                                               Fault Isolation
highest failure rates

Trace circuit cones of
selected scan cells
                                                                                                                Physical (destructive)
                              Find cone intersections                                                              Confirmation
                                                                                                                    FIB, SEM, TEM
                              Prune nets off non relevant
                              fan outs

                              Correlate state transitions to
                                                                      V550 or V520 coupled with FA
                              test results and test patterns
                                                                      imaging equipment to
                              in isolated circuits
                                                                      dynamically confirm isolated
                                                                      defects - ideal for soft defects

                                                                                                            Use Diagnostic Manager NetXY
                                                                                                            to determine probe points for
                                                                                                            FIB physical confirmation




                                                         Teseda Confidential

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Brief Introduction To Teseda

  • 1. An Introduction to Teseda Fast and Intuitive Scan Defect Isolation Teseda Confidential
  • 2. Who Is Teseda? Ensuring rapid diagnosis of design, process, or use related failures is the core of our business! • Teseda’s products accelerate first silicon debug and shorten failure analysis and yield improvement turn-around time • Teseda Solutions deliver:  Fast Silicon Debug (Time To Market)  Rapid Failure Analysis - Impacts time to production release and yield improvement Teseda Confidential
  • 3. V520 Engineering Test System • 348 I/O pins  50Mhz force and compare  300 I/O pins, 32 clock pins, 16 scan enable pins  Full per-pin timing capability • 32M Per Pin Vector Depth • DC Parametric Source/Measure Option  Continuity, Leakage and Voltage measurements  Fully automated SW control • 4 Internal DUT Power Supplies  2 High Current (2A)  2 Low Current (100mA) • Driven by Teseda’s powerful Teseda WorkBench (TWB) DFT-Enabled Software Teseda Confidential
  • 4. V550 Engineering Test System • 512 I/O pins  100Mhz force and compare  Higher clock and data rates can be created with multiple edges per cycle  Any pin can be I, O, I/O or Clock  Full per-pin timing capability • 64M Per Pin Vector Depth • DC Parametric Source/Measure Option  Continuity, Leakage and Voltage measurements  Fully automated SW control • 7 Internal DUT Power Supplies  4 High Current (4A)  2 Low Current (250mA)  1 High Voltage (25V) • Driven by Teseda’s powerful Teseda WorkBench (TWB) DFT-Enabled Software Teseda Confidential
  • 5. Capabilities of Teseda Workbench Create New Tests Quickly Execute Tests • Import STIL files • Functional or Scan Tests • Set DC values • Map failing scan cells to chain • Compile and download tests and design instance • Manage projects • DC Tests (Continuity, IiL, VoH) • Interactive, easy-to use • Iddq Tests • Shmoo Plots and Test Flows Perform Failure Analysis Export Scan Fail Logs • Compare expect with actual • Save cycle or pattern format • Loop on specific vectors • Synopsys or Mentor format • Trigger output on events • Feed fail result logs to • Designed to interface with diagnosis tools like NetXY, Emission Microscopes, LADA, YieldAssist and TetraMAX and other SDA tools Teseda Confidential
  • 6. Teseda Workbench Features • Manages V550 or V520 hardware • STIL compiler • Set DC and AC timing values • Vector and timing waveform display • Run test settings – P/F mode, fail capture mode, full capture mode, loop vectors, set triggers, run with timing scale, etc. • Scan fail results processing and logging • Debug / Characterization Tools  Chain plot tool  Scan view / design view tool  Shmoo plot tool  DC measurement screen  Iddq measurement screen • Manage test projects, archive, delete, etc. Teseda Confidential
  • 7. Diagnostic Manager NetXY LEF/ DEF STIL STIL - Test Pattern Failures Scan Failures- From Test Pattern results • Diagnostic Manager NetXY diagnoses the cause of scan-captured failures within the physical design of the device  Analyzes design, STIL vectors and scan failures  Identifies the location of the fault on the physical layout • Utilizes industry standards  Standard Test Interface Language (STIL)  Design Exchange Format (DEF)  Library Exchange Format (LEF) • Interoperable with all major EDA DFT and diagnostic tools and flows Teseda Confidential
  • 8. Real Customer Example Mapping Logical Fails to Physical • Four scan cells failing frequently  A few neighboring infrequent failures  Scan cells located in same logic block TWB Diagnostic Manager NetXY Teseda Confidential
  • 9. Scan Fail Diagnosis with NetXY • Show scan chain stitching order on the physical layout • Overlay scan flip flops capturing failures on the physical scan chain along with color map of fail density • Pathfinder design navigation tool - enables logic trace back from failing scan flip flops • Automated logic cone tracing back from failing scan flip flop • Automated scan chain tracing of the physical nets that connect between scan flip flops (useful in diagnosing chain fails) • Automated cone convergence  identify the common intersection of multiple failing logic cones • Automated identification of the failing net Rapidly find the root cause of scan fails regardless of EDA vendor. Diagnose failures without requiring support from the design team. Teseda Confidential
  • 10. Teseda in Failure Analysis Diagnose = Localize + Isolate + Confirm Defect Localization V550 V520 Defect Isolation Teseda Workbench (TWB) Fault Localization Map test fail logs onto the Diagnostic Manager physical design Defect Confirmation NetXY Emission, LIVA, TIVA, OBIRCH, LADA Identify scan cells with Fault Isolation highest failure rates Trace circuit cones of selected scan cells Physical (destructive) Find cone intersections Confirmation FIB, SEM, TEM Prune nets off non relevant fan outs Correlate state transitions to V550 or V520 coupled with FA test results and test patterns imaging equipment to in isolated circuits dynamically confirm isolated defects - ideal for soft defects Use Diagnostic Manager NetXY to determine probe points for FIB physical confirmation Teseda Confidential