Abraham q3 2008
- 1. Nanometer Testing: Challenges and Solutions Jais Abraham AMD India Design Centre
- 2. Characteristics of Nanometer Devices Design trends Increasing corners of operation (multiple frequencies, voltage, power scenarios) Increasing integration (SOCs, SIPs) Permeation of high bandwidth serial/ differential interfaces Process issues Process variations becoming key concern Increasing wiring densities leading to complex signal integrity problems Dominance of new kinds of defects based on the metal subsystem
- 3. Test Challenges – Increased Parametric Variations Source : “Parametric Failures in CMOS ICs- A Defect Based Analysis”, Hawkins et al., ITC2002
- 4. At Least Test will Find It? e- e- L TARGET L EFFECTIVE Minor bridging defects etc. Current vs. Speed Limit Current L EFFECTIVE = L TARGET - X e- e- X : Lot1 L TARGET O : Lot2 L EFFECTIVE L EFFECTIVE = L TARGET + X Source: Madge, et. al., 2004 Speed
- 5. Test Challenges – New Failure Mechanisms Cu Voids Open Shorts
- 6. Test Challenges - Cost of Test Source : International Technology Roadmap for Semiconductors, 2001
- 7. Test Challenges – Power Test power could be more than functional power – more regions of the device operating than in functional mode – switching of logic during scan shift With increasing design frequencies & integration – Can the tester supply the power required in the test mode – Can the package support the power required in the test mode – Will the part be able to withstand the power consumption during high voltage testing
- 8. Test Challenges - Yield Learning Defect sizes scale as quickly or faster than the device features Difficulty in localizing faults increases one order of magnitude every six years Defective chips offer significant information on these failure mechanisms Yield learning is becoming increasingly important To tune the manufacturing processes to achieve higher profits To reduce the time for volume production since product life cycles are coming down
- 9. SOLUTIONS
- 10. New Fault Models - Bridge Fault Testing Bridge fault testing detects shorts between interconnects 0 A 0 0 1 1 B 0
- 11. Bridge Fault Testing Number of possible bridges in a design is exponential to the number of nets Bridge node pair extraction is done from layout based on proximity analysis Critical Area Analysis Four possible bridge fault tests exist for a pair of nodes Could lead to a large test vector count
- 12. High resistance bridging faults Bridge Resistance Data* Source: “Test challenges in nanometer”, Kundu et al., ITC2000
- 13. Delay Fault DC tests (eg based on stuck-at, logic bridge model) are no longer adequate AC tests which ensure that the design works at the rated speed are required
- 14. Delay Fault Testing Delay fault tests check if any node in the design is slower to rise or fall than it should Requires design techniques to obtain high coverage On-chip PLL based clocking Support for multiple clock domains Knowledge of device timing exceptions Consume 2x-5x times the number of test patterns for stuck-at fault testing
- 15. Small Delay Defects Source: “Test Method Evaluation Experiments and Data”, Nigh et al., ITC2000
- 16. Small Delay Fault Testing small delay test 0.4 0.1 transition test 0.3 0.3 0.2 0.5
- 17. Reducing the Cost of Scan Tests Scan in 1 Scan out 1 Scan in 2 Scan out 2 Scan in 3 Scan out 3 Scan in 4 Scan out 4 Scan in 5 Scan out 5 Test time = length of scan chain x #patterns x (1/frequency of shifting) Test volume = length of scan chain x #patterns x 2
- 18. Scan Compression Scan chain group 1 Scan chain group N Scan chain group 2 Scan in 1 C E o x m Scan in 2 p p a r n e d s e s Scan in N r o r
- 19. Reducing Power During Test Divide and conquer Switch lesser logic while reducing test time Prevent the functional logic from switching during scan shift using data gating Power aware ATPG patterns which prevent transitions that don’t result in additional coverage
- 20. What is the Problem? Design 1 Design 2 • Same Die Size • Same Complexity • Same Foundry • Same Process
- 21. What is the Problem? Design 1 Design 2 77% Yield 42% Yield Interactions Between Design and Manufacturing
- 22. Scan based diagnostics To enable effective use of scan patterns for yield learning, the patterns should have Capability to identify failures – Requires high test coverage Capability to isolate the failures – Accurately map the failures to the physical location of the failures
- 23. Scan based diagnostics Layout Defect mapping suspect coordinates Physical Failure Analysis Failure Diagnostics Information Defect information ATPG based failure diagnostics Manufacture Wafer Failure Information Test
- 24. Economics $$$$ Yield Accelerated Yield Learning Standard Yield Improvement Time
- 25. Conclusion Nanometer testing presents new challenges not seen hitherto Without a single-eyed focus on test, either of the following scenarios are likely: Low Test Quality : High escape rates of defective devices High Test Cost : Affecting profitability Slow ramp to volume : Missing critical time-to-market windows The solution to these problems requires a tight interaction between the test experts, silicon technology experts and ATE experts