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BSIM4 AND MOSFET
MODELING FOR
IC SIMULATION

International Series on Advances in Solid State Electronics and Technology
(ASSET)
Founding Editor: Chih-Tang Sah
Published:
Modern Semiconductor Quantum Physics
by Li Ming-Fu
Ionizing Radiation Effects in MOS Oxides
by Timothy R. Oldham
MOSFET Modeling for VLSI Simulation: Theory and Practice
by Narain Arora
MOSFET Modeling for Circuit Analysis and Design
by Carlos Galup-Montoro and Márcio Cherem Schneider
The Physics and Modeling of MOSFETs: Surface-Potential Model HiSIM
by Mitiko Miura-Mattausch, Hans Jürgen Mattausch & Tatsuya Ezaki
Invention of the Integrated Circuits: Untold Important Facts
by Arjun N Saxena
Electromigration in ULSI Interconnections
by Cher Ming Tan
Compact Hierarchical Bipolar Transistor Modeling with HICUM
by Michael Schroter and Anjan Chakravorty
BSIM4 and MOSFET Modeling for IC Simulation
by Weidong Liu and Chenming Hu
KwangWei - BSIM4 and MOSFET.pmd 9/14/2011, 5:18 PM
1

NEW JERSEY • LONDON • SINGAPORE • BEIJING • SHANGHAI • HONG KONG • TAIPEI • CHENNAI
World Scientific
Weidong Liu
Synopsys, USA
Chenming Hu
University of California, Berkeley, USA
Founding Editor: Chih-Tang Sah
BSIM4 AND MOSFET
MODELING FOR
IC SIMULATION
ASSET

British Library Cataloguing-in-Publication Data
A catalogue record for this book is available from the British Library.
For photocopying of material in this volume, please pay a copying fee through the Copyright
Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, USA. In this case permission to
photocopy is not required from the publisher.
ISBN-13 978-981-256-863-2
ISBN-10 981-256-863-8
Disclaimer: This book was prepared by the authors. Neither the Publisher nor its Series Editor
thereof, nor any of their employees, assumes any legal liability or responsibility for the accuracy,
completeness, or usefulness of any information. The contents, views, and opinions of the authors
expressed herein do not necessarily state or reflect those of the Publisher, its Series Editor, and their
employees.
All rights reserved. This book, or parts thereof, may not be reproduced in any form or by any means,
electronic or mechanical, including photocopying, recording or any information storage and retrieval
system now known or to be invented, without written permission from the Publisher.
Copyright © 2011 by World Scientific Publishing Co. Pte. Ltd.
Published by
World Scientific Publishing Co. Pte. Ltd.
5 Toh Tuck Link, Singapore 596224
USA office: 27 Warren Street, Suite 401-402, Hackensack, NJ 07601
UK office: 57 Shelton Street, Covent Garden, London WC2H 9HE
Printed in Singapore.
BSIM4 AND MOSFET MODELING FOR IC SIMULATION
KwangWei - BSIM4 and MOSFET.pmd 9/14/2011, 5:18 PM
2

Dedication
The authors dedicate this book to their families for their love and
support, and the BSIM users of the past, present and future.

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This page intentionally left blank

vii
Foreword
This monograph is the seventh book in this series on modeling of
integrated-circuit devices. The purpose of this series is to provide archival references,
described by the model originators or authorities, on the mathematically compact and
computationally efficient engineering models of transistors and devices that are
interconnected on a small, about a square centimeter or smaller area, silicon
semiconductor wafer, die, dice, or chip, containing many integrated transistor circuits,
which is the ‘brain’ of the equipment used in our daily activities today.
The monograph series idea came about six years ago in 2005 when I was asked by
colleagues of Compact Modeling Council and Compact Model Community (CMC) to
join them and give a keynote at their 4th annual international Workshop on Compact
Modeling on May 10, 2005. I had been absent on transistor modeling research for 40
years since my first PhD student, Henry Pao, finished his PhD thesis in 1966 on the
analytical model of the surface-channel silicon field-effect transistor (FET) with the
Metal-Oxide gate on Silicon body (MOS). The prerequisite was to talk about a subject
of their prime interest. But, I had not heard the term “compact model” and had the
faintest idea of its meaning due to 40 years of absence. While searching the literature
for references to write the keynote address, it became evident that there were many
compact models and originators, but few books had provided descriptions sufficiently
detailed for the professionals who must use the compact transistor models to execute a
computer-aided-design of the integrated circuits that contain thousands to millions,
now more than a billion transistors. A second purpose of this device modeling series is
to provide state-of-the-art textbooks for graduate students and reference books for
practicing engineers who are the users but may not be the designers of the latest
integrated circuits.
After editing six compact modeling monograph volumes in this ASSET
(Advances in Solid-State Electronics and Technology) series and reading literature on
the faster-than-exponential rise of progresses in other areas of sciences and
engineering, it seemed suddenly becoming obvious, if not already a common
knowledge, that the word ‘Model” is the buzz word everywhere. So perhaps it is
timely to add a few words in this “Foreword of Opportunity” about “Model”, because
in the two 60+year-old transistors which dominate everything of our life today, and
even earlier devices, “model” has been the key to their discoveries and inventions.
Quantitative modeling was certainly used even earlier in all engineering; even earlier,
in evolution, in qualitative and habitual learning, and in the basics of the most basics of
foundation of physics, explored by man about his origin and universe.
Our past, present and future are all model based. Some are more quantitative,
others more qualitative; some more deterministic, others more statistical; some local,
others global; some experience based, others more science (scientific method) based.
Weather, archeology, evolution, particles and materials, societal and custom-habit,
stock market, biology and medicine, are some of the examples, in addition to the
engineering feat, the invention on paper, of the two transistors by Shockley (see

viii BSIM4 AND MOSFET MODELING FOR IC SIMULATION by Weidong Liu and Chenming Hu
Foreword by Chih-Tang Sah
below). Most were compact or incomplete models based on a limited set of inventors’
then current and latest knowledge, idea, notion, and imagination. All were already
abbreviated or compact, compacted from the ‘complete’ theory based on intuitive
physics, but most were further compacted to meet mathematical tractability by the
inventor’s own mathematical skill if not more so the inventor’s desire to popularize
the invention in laymen or more common language rather than abstract-obscure. But
the compact models or compact-compact (compact2
) models are increasingly less
compact or increasingly more complicated because of increased computer capability
to numerically solve them fast, due to better models that help design faster computers,
creating still better models, a regenerative positive feedback loop. Such a loop fuels
the increasingly faster than exponential rate of technology growth and advances,
which would extrapolate to reach infinity at some finite future time, if not for some
unseen, not modeled missing resistive-damping.
This book volume on the MOS transistor compact model BSIM exemplifies the
development of a compact model, in this case, the one most used by man in its
successful engineering applications on the design of computing, communication, and
control circuits, which process electrical signals. BSIM is a compact model on the
field effect transistor with insulated gate, the Insulated Gate Field-Effect Transistor
(IGFET), more commonly known as the Metal-Oxide-Silicon field effect transistor
(MOSFET) or just MOS Transistor (MOST which drives home the fact that it is the
most abundant artificial device produced by man). The models or mathematical
models for transistors are based on the current knowledge in the physics and ‘model’
of matter, the condensed phase which semiconducts electricity by two species of
carriers or ‘elementary’ particles, electrons and holes, with exactly opposite unit of
electrical charge, but somewhat different in their inertia masses, not unexpected in this
imperfect world and asymmetrical, skewed universe, not unlike the two biological
genders of much larger size, containing many more molecular particles.
Field effect transistor (FET, 1952) is one of the two transistors invented by
William Shockley about sixty years ago. The other was the bipolar junction transistor
(BJT, 1949). In-between, he wrote his classic textbook, Electrons and Holes. The two
transistors have been the foundation devices of the electronic revolution. Shockley
invented them on paper using the simplest physics models, one current channel in
each, the diffusion current for the BJT and the drift current for the FET, both in the
bulk or bulk-channel of a semiconductor, the Germanium, because crystalline Silicon
was difficult to produce in the 1950’s due to its high melting point, 1420C, even at the
Bell Telephone Laboratories. The complete transistor model, which became obvious
to this author not until 60 years later, is the eight channel device, analyzed by this
author and his collaborator, Jie Binbin, both at Xiamen University, China, which is the
eight combinations of electrical current channels, the drift and diffusion currents of
electrons and holes in the surface and the bulk-or-body channels, giving 2 x 2 x 2 = 23
= 8 electrical current channels or electrical charge carrier transport pathways. The two
foundation transistors, BJT and FET, could not have been invented if Shockley had
not mentally visualized and singled out the two simplest (or most compact) models:

BSIM4 AND MOSFET MODELING FOR IC SIMULATION by Weidong Liu and Chenming Hu ix
bulk drift (for FET) and bulk diffusion (for BJT) by just one carrier species (electron
or hole), that enabled him to mathematically analyze and design the two transistors
and to predict their electrical characteristics and performance, all on paper, 60+ years
ago.
The comprehensive and authoritative compact modeling of the modern BJT was
covered by the latest prior volume of this compact transistor model series, known as
the HICUM, authored by Professor Michael Schroter of Germany and Dr. Anjan
Chakravorty of India, and published by WSPC of Singapore in the fall of 2010.
The compact modeling of the second transistor type, FET, invented by Shockley
in 1952, in the modern form, the silicon MOSFET or silicon MOST, is covered in this
volume. The model is known as BSIM, and is in its fourth generation, BSIM4. It is
authored by the founder-inventor of the BSIM, Professor Chenming Hu of China and
USA, and his able assistant, Dr. Weidong Liu of China and USA. It is published in
this ASSET series (this book) by WSPC one year later in the fall of 2011.
The publication sequence of these two volumes on the two transistors, 1949-BJT
and 1952-FET in the modern form of Si MOST, followed the invention and the
application histories of the two transistors. But this coincidental publication sequence
was not planned in this compact modeling monograph series; however, the publication
sequence does reflect the volume manufacturability determined by the advances of
fabrication technology, especially the equipment, which also determines the
application volumes and varieties.
I am especially thankful to the invited authors of the four startup volumes (Narain,
Carlos+Márco, Mitiko+Hans+Tatsuya, and Arjun), of the later volumes (Cherming,
Michael+Anjan, and Chenming+Weidong of this volume), and of the two to be
published volumes (Ching-Hsiang+Yuan-Tsai and Francisco+Adelmo.). They
concurred with my objectives and agreed to take up the chore of writing their books
during their very busy schedules. Some have delays of one, two or even three years.
Nevertheless, their monographs are still the archival records of the state of the art, and
the world’s authoritative contributions to the device modeling literature, because these
authors are the creators, inventors and/or authorities of the models, and because the
models are the industry-wide consensus models, used by all circuit designers of recent
generations, and expected to be used by the future generations.
The present volume is a detailed comprehensive description of the latest version
of the industrial consensus compact model for silicon MOSFET, the BSIM4, used by
90% if not 95% or more of the integrated circuit design and application engineers, and
learned by all the electrical and computer engineering graduate students, for
generations, two if not more decades. It also contains the historical development from
the first BSIM, narrated by its creator, innovator, custodian, and father, Hu Chenming
or Calvin Hu, the TSMC Distinguished Chair Professor at the University of California,
Berkeley. A most important and salient teaching feature of this book is that the
compact model of each of the electron-hole transport phenomena in the MOSFET is
developed from the basic device physics of charge carrier transport in semiconductors,
governed by the Shockley Equations. The compacted models are not only accurate in

x BSIM4 AND MOSFET MODELING FOR IC SIMULATION by Weidong Liu and Chenming Hu
device physics, but also in computational efficiency and accuracy to give the
numerical results for representing the characteristics of the transistor which must be
provided to the circuit simulator, such as SPICE, to analyze the performance of an
integrated circuit, which may contain hundreds to millions of transistors, exceeding
one billion recently. The fastest and largest (in memory capacity) computer would not
be able to give numerical results in a short enough turn-around time (say a day or even
a week) for manufacturability if the one million or more transistors were represented
by their original and not-compacted models.
The last chapter gives the current and latest compact model for the upcoming
generation of sub-quarter-100nm or 20-nm MOS transistor using the 3-dimensional
Fin-like geometry structure, known as the FinFET, invented by Professor Hu.
The notations and terminologies employed in this monograph follow the
industrial practice used by the design and manufacturing engineers of the MOSFETs.
The monograph descriptions provide the connection of the notations and
terminologies to the physics of semiconductors. For examples, silicon bandgap is
noted as electron energy gap in silicon; avalanche multiplication and breakdown, as
interband impact generation of electron-hole pairs by hot or energetic electron or hole;
flicker noise, as 1/f noise from the addition of many trapping noise sources each with a
different trapping time constant; white noise or Johnson noise, as random scattering
noise with a reciprocal scattering rate in femto second range so the ‘corner” or
noise-power drop-off frequency is in the THz range; and many others.
I would like to thank all the WSPC production staff members at Singapore and
their production editor of this monograph, Mr. Tjan Guangwei, and the acquisition
editor, VP Ms. Zhai Yubing in New Jersey, for their untiring and dedicated efforts and
supports. Special thanks are due NTU Physics Professor Kok-Khoo Phua, the Founder
and Chairman of WSPC, for his farsights and foresights, one of which was pursuing
me into authoring and editing textbooks and monographs in 1990, when I was rather
discouraged if not also disgusted by the tactics of some publishers, which is a proof of
my thesis, the Evolutionary Intelligent Design. I also thank Dr. Jie Binbin, Professor
of Physics of Xiamen University, for editorial assistance. We also thank our
supporters, President Zhu Chongshi, School of Physics Dean Wu Chenxu, and
Department of Physics Chair Zhao Hong, all of Xiamen University, China. Finally,
the editorial efforts of both of us, Sah Chihtang and Jie Binbin of this ASSET series,
have been supported by the CTSAH Associates, Florida, USA, which was founded by
the late Linda Su-Nan Chang Sah in mid-1970 at Urbana, Illinois, and which was
reactivated on February 27, 2010, at Gainesville, Florida.
Sah Chihtang (Chih-Tang Sah)
Department of Physics, Xiamen University, China.
CTSAH Associates, Florida, USA.
Initial draft, July 1, 2011, near the North Pole on way to
Beijing and Xiamen from Seattle on Delta B767-300ER.
Final version, July 4, 2011 at Yi-Fu Hotel, Xiada campus.
Eighth year on August 13, 2011 and moving forwards.

xi
Preface
The compact models of semiconductor devices are the bridges between
design and manufacturing in the integrated circuit industry. As such,
compact models play an important and unique role in the IC technology,
which brings gigantic benefits to the world economy and the quality of
human life.
The compact models are as old as the computer simulation of
integrated circuits with models such as MOS Level 1 and Gummel-Poon
bipolar junction transistor models dating back to the 1970’s. In the
1990’s, the advent of the foundry-fabless partition in the IC industry
changed compact modeling in several ways. First, the compact models
were suddenly under the limelight because they became the bridge
between IC chip foundries and hundreds of design companies that use
these foundries. Second, the need for very accurate compact models was
heightened because the models would now serve as the “contract” on
transistor behaviors between the foundries and their many customers.
Third, the compact models became much more complex than MOS Level
1 and Gummel-Poon BJT for deep-submicron and nanometer process
technologies and, as a result, many major IC companies sought to reduce
the high cost of developing their own compact models by joining force to
seek, select, and support standard compact models under the banner of
Compact Model Council. The first international standard compact model
was BSIM (Berkeley Short-channel IGFET Model).
The authors have been honored and privileged to develop and support
the BSIM4 model for the IC industry worldwide. Following its
predecessor BSIM3v3, the industry’s first standard, BSIM4 has served
nearly all IC design and manufacturing companies from the 130-
nanometer technology node down to the 20-nanometer node as of the

By Weidong Liu and Chenming Hu
xii
date of this book publishing. Over the years, BSIM4 has contributed to
the development of IC products worth untold billions of dollars. During
that time, we communicated with innumerable BSIM4 users around the
globe. Often the same discussion topics would be brought up in those
communications. Thus, we set out to write this book to provide the
insights and comprehensive descriptions of BSIM4 and address those
topics.
Another aim of this book is to share the knowledge and experiences
we have gained from developing the BSIM models so as to further the art
of compact modeling for emerging IC technologies.
Behind this book are many unsung heros, counted in hundreds. It is
impossible for us to name them all. We would like to thank them
collectively. But we particularly would like to give special thanks to the
following.
We would like to acknowledge our fellow BSIM4 development team
members at the University of California at Berkeley for their invaluable
contributions to BSIM4 and to our knowledge. They are Xiaodong Jin,
Kanyu M. Cao, Xuemei (Jane) Xi, Wenwei (Morgan) Yang, Chung-
Hsun Lin, Mohan Dunga, Darsen Lu, Pin Su, Jin He, Tanvir Morshed,
Jeff J. Ou, Mansun Chan, and Ali M. Niknejad.
We acknowledge the discussions, testing, and improvements on
BSIM4 from Keith Green, Josef Watts, Judy An, William Liu, Britt
Brooks, Min-Chie Jeng, Sally Liu, Yu-Tai Chia, Bing Sheu, Ke-Wei Su,
Chung-Kai Lin, T. L. Tsai, C. S. Yeh, J. K. Chen, Jin-Shyong Jan, Annie
Kuo, Peiming Lei, Daniel Wan, Waisum Wong, Richard Williams,
Lawrence Wagner, Yoo-Mi Lee, Calvin Bittner, Peter Lee, Wenliang
Zhang, Takahiro Iizuka, Paul Humphries, Geoffrey Coram, Jean-Paul
Morin, Andre Juge, Peter Klein, Ali Icel, Jung-Suk Goo, Changhong Dai,
Shiuh-Wuu Lee, Anwen Liu, Susan Wu, Eugene Chen, Jeff Watt, Liping
Li, Tom Mahatdejkul, Sam Lo, Akira Ito, Ben Gu, Jushan Xie, Ahmed
Ramadan, Rick Poore, James Ma, Jonathan Sanders, John O'Donovan,
and other BSIM users.
The authors especially would like to acknowledge the colleagues at
the Analog Mixed-Signal group, Synopsys, Inc., for their invaluable

Preface
xiii
support and encouragement given to this book writing and their
contributions to making BSIM4 a successful compact model for the IC
industry over the past decade.
Special thanks are due to the editing and publishing staff at WSPC.
They are Professor Chih-Tang Sah, Ms. Yubing Zhai, Gregory Lee,
Jason Lim, Rajesh Babu, Yolande Koh, and Quek Yeow Hwa for their
year-long relentless efforts in numerous rounds of rigorous expert
review, editing and proofreading of the manuscript. The tremendous
attention by Professor Sah to every detail significantly improved the
quality of this book.
Weidong Liu
Silicon Valley, California
Chenming Hu
Berkeley, California
July 1, 2011

xv
Contents
Forword vii
Preface xi
Chapter 1 BSIM and IC Simulation 1
1.1 Circuit Simulation and Compact Models 1
1.2 BSIM – The Beginning 1
1.3 BSIM3 – A Compact Model Based on New MOSFET Physics 3
1.4 BSIM3v3 – World’s First MOSFET Standard Model 5
1.5 BSIM4 – Aimed for 130nm Down to 20nm Nodes 6
1.6 BSIM SOI 7
1.7 Impact of BSIM 7
1.8 Looking Towards the Future – The Multi-Gate MOSFET Model 8
1.9 The Intent of This Book 8
References 9
Chapter 2 Fundamental MOSFET Physical Effects and
Their Models for BSIM4 13
2.1 Introduction and Chapter Objectives 13
2.2 Gate and Channel Geometries and Materials 14
2.2.1 Gate and Channel Lengths and Widths 14
2.2.2 Model Card and Parameter Binning 16
2.2.3 Gate Stack and Substrate Material Model Options 18
2.3 Temperature-Dependence Model Options 21
2.4 Threshold Voltage 22
2.4.1 Long Channel with Uniform Substrate Doping 22
2.4.2 Short-Channel Effect: Vth Roll-Off and Drain Bias Effects 25
2.4.3 Narrow-Width Effects 31
2.4.4 Non-Uniform Substrate Doping 32
2.4.4.1 Non-Uniform Vertical Doping 33
2.4.4.2 Non-Uniform Lateral Doping: Pocket Implants 36
2.4.5 Vth Temperature Dependence 39
2.4.6 BSIM4 Vth Equation 40
2.5 Poly-Silicon Gate Depletion 42
2.6 Bulk-Charge Effects 45

xvi
2.7 LDD Resistances 46
2.8 Finite Charge Thickness 51
2.9 Effective Mobility 53
2.10 Layout-Dependent Effects: Mechanical Stress and Proximity Effects 58
2.11 Chapter Summary 66
2.12 Parameter Table 66
References 85
Chapter 3 Channel DC Current and Output Resistance 87
3.2 Channel Current Theory 88
3.3 Single Continuous Channel Charge Model 89
3.4 Channel Current in Subthreshold and Linear Operations 93
3.5 Velocity Saturation and Velocity Overshoot 95
3.6 Output Resistance in Saturation Region 98
3.6.1 CLM: Channel Length Modulation 100
3.6.2 DIBL: Drain-Induced Barrier Lowering 103
3.6.3 DITS: Drain-Induced Threshold Voltage Shift Due
to Non-Uniform Doping 104
3.6.4 SCBE: Substrate Current Induced Body-Bias Effect 105
3.6.5 Channel Current Model for All Regions of Operation 106
3.7 Source-End Velocity Limit 107
References 113
Chapter 4 Gate Direct-Tunneling and Body Currents 115
4.2 Gate Direct-Tunneling Current Theory and Model 116
4.2.1 Tunneling Mechanisms and Current Components 116
4.2.2 Gate Oxide Voltage 120
4.2.3 Gate-Body Tunneling Current Igb 121
4.2.4 Gate-Source/Drain Tunneling Through Overlap Regions 123
4.2.5 Gate-Channel Tunneling Current 125
4.2.5.1 Igc0: The Vds = 0 Bias Scenario 125
4.2.5.2 Igcs and Igcd Partitioning: The Non-Zero
Vds Scenario 127
4.2.6 Characterization and Parameter Extraction 137
4.3 Body Currents 138
4.3.1 Impact Ionization 139
4.3.2 Gate-Induced Source and Drain Leakage 143
4.4 Summary of BSIM4 Branch and Terminal DC Currents 147

Contents
xvii
References 152
Chapter 5 Charge and Capacitance Models 155
5.2 MOSFET Capacitance Theory 157
5.3 Intrinsic Charge and Capacitance Models 167
5.3.1 Charge-Thickness Model (CTM) 168
5.3.2 CAPMOD = 2 Charge Model Formulations 176
5.4 Fringing and Overlap Capacitances 180
5.4.1 Fringing Capacitances 180
5.4.2 Overlap Capacitances 181
5.6 Parameter Table l84
References 186
Chapter 6 Non-Quasi-Static and Parasitic Gate
and Body Resistances 189
6.2 Gate Electrode Resistance 190
6.3 Gate Intrinsic-Input Resistance for Non-Quasi-Static Modeling 193
6.4 Charge-Deficit Transient and AC NQS Models 201
6.4.1 Charge-Deficit Transient NQS Model 201
6.4.2 Charge-Deficit AC NQS Model 211
6.5 Body Resistance Network 214
6.5.1 RBODYMOD = 1: A Local Network 216
6.5.2 RBODYMOD = 2: A Scalable Network 218
6.5.2.1 The 5-R Model 219
6.5.2.2 The 3-R Model 224
6.5.2.3 The 1-R Model 225
References 233
Chapter 7 Noise Models 235
7.2 Noise Representations and Parameters 236
7.2.1 Noise and Power Spectral Intensity 236
7.2.2 SPICE Noise Representations 238
7.2.3 Noise Representation and Parameters of a
Two-Port Network 239
7.3 BSIM4 Flicker Noise Models 246
7.3.1 The FNOIMOD = 0 Simple Flicker Noise Model 248

xviii
7.3.2 The FNOIMOD = 1 Physics-Based, Unified
Flicker noise Model 248
7.4 BSIM4 Channel Thermal Noise Models 253
7.4.1 The TNOIMOD = 0 Charge-Based Model 254
7.4.2 The TNOIMOD = 1 Holistic Thermal Noise Model 255
7.5 Other Noise Sources 263
References 266
Chapter 8 Source and Drain Parasitics:
Layout-Dependence Model 269
8.2 Connections of a Multi-Transistor Stack 270
8.3 Source and Drain of a Transistor With Multiple Gate Fingers 273
8.4 GEOMOD: The End-Source and End-Drain of a
Multi-Finger Transistor 275
8.5 Source and Drain Area and Perimeter Calculation 276
8.6 Saturation Junction Leakage Current and Zero-Bias
Capacitance Models 290
8.7 Source and Drain Contact Scenarios and Diffusion Resistances 292
8.8 RGEOMOD: Selecting A Source and Drain
Contact Scenario for GEOMOD 296
Chapter 9 Junction Diode IV and CV Models 303
9.2 Physical Mechanisms of Diode DC Currents 303
9.2.1 Shockley-Read-Hall (SRH) Generation and Recombination 305
9.2.2 Trap-Assisted Tunneling (TAT) 307
9.2.3 Band-To-Band Tunneling (BTBT) 308
9.2.4 Diode Breakdown 309
9.3 BSIM4 Diode DC IV Model [4] 311
9.3.1 DIOMOD = 0 311
9.3.2 DIOMOD = 1 315
9.3.3 DIOMOD = 2 316
9.4 BSIM4 Junction Leakage Due to Trap-Assisted Tunneling [4] 321
9.5 BSIM4 Diode Charge and Capacitance [4] 322
9.5.1 BSIM4 Diode CV Model [4] 323
9.6 Diode Temperature-Dependence Model [4] 328
9.6.1 Temperature-Dependence Model for Diode IV 329
9.6.2 Diode CV Temperature-Dependence Model 332

Contents
xix
References 343
Chapter 10 SPICE Implementation Example:
The Methodology with BSIM4 Transient NQS 345
10.2 Review of the Charge-Deficit Transient NQS Model 346
10.3 Time Discretization, Equation Linearization and Matrix Stamping 347
10.3.1 Discretization and Linearization of ich_qs(t) 351
10.3.2 Stamping of ich_qs(t) 356
10.3.3 Linearization of iCτnqs
(t) 357
10.3.4 Stamping of iCτnqs
(t) 357
10.3.5 Linearization of iRτnqs
(t) 358
10.3.6 Stamping of iRτnqs
(t) 360
10.3.7 Linearization of ig (t) 361
10.3.8 Stamping of ig (t) 363
10.3.9 Linearization of id (t) 363
10.3.10 Stamping of id (t) 366
10.3.11 Linearization of is (t) 368
10.3.12 Stamping of is (t) 371
10.4 Composite Stamps for Transient NQS Model 373
10.5 Bypass 375
10.6 Convergence Checking 382
References 386
Chapter 11 Multi-Gate Transistor Model 387
11.2 Advantages of FinFETs Over Planar CMOS 388
11.3 BSIM-CMG 390
11.3.1 The Core Model: Surface Potential Modeling 390
11.3.2 Channel I-V Model 396
11.3.3 Charge and Capacitance Models 399
11.3.4 Modeling of Advanced Physical Effects 403
11.4 Model Validation 406
References 409
Index 411

1
Chapter 1
BSIM and IC Simulation
BSIM (Berkeley Short-channel IGFET Model) became the first
international industry standard compact model for the simulation of
CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuits
in 1997. It is believed that most of the ICs developed worldwide since
1998 were designed using BSIM. BSIM has served a wide range of
CMOS technologies and IC applications.
1.1 Circuit Simulation and Compact Models
An integrated circuit contains millions to billions of transistors. The
functionality and performance of the circuits must be verified by
computer simulation before it is committed to expensive fabrication.
Circuits are simulated by a method known as SPICE (Simulation
Program with Integrated Circuits Emphasis), which was first developed
by Professors Ron Rohrer and Don Pederson and their students at the
University of California, Berkeley, in the early 1970’s. In this method,
the differential and algebraic nodal and branch equations (DAE) of an
integrated circuit are solved by numerical analysis algorithms. The
circuits are usually nonlinear because transistors such as MOSFETs
(Metal-Oxide-Semiconductor Field Effect Transistors) are nonlinear
devices (in contrast to a bias-independent resistor or capacitor).
For MOSFET devices, the complex behavior of the transistor drain
current of the general form of Id(Vg, Vd, Vs, Vb, L, W) is accurately
represented by a group of analytical equations known as a compact
model. If these equations are printed on paper, they may occupy a few
pages. However, when they are implemented in SPICE, tens of
thousands of computer code lines result. The length and complexity of

2
the functions used in the equations have significant impact on the circuit
simulation time. It is therefore important to optimize both the
computational efficiency of the model and its accuracy. In addition to the
drain current, the device terminal charges and/or capacitances are also
represented by analytical equations.
The model equations inevitably contain many adjustable constants
known as model parameters. They are adjusted by modeling engineers to
fit the compact model to measured terminal currents, conductances,
charges and capacitances of the transistors — a process known as model
parameter extraction. This process is performed with the aid of extraction
software tools.
Large circuits are designed sometimes by using what is called cell
library methodology. A circuit is often assembled from a pre-selected
and characterized library of building blocks known as standard cells. A
standard cell library typically contains many hundreds or thousands of
standard cells such as inverters, NOR and NAND gates, flip flops, as
well as other more complex cells. Every cell is characterized with SPICE
simulation and compact models. The simulation results are reduced to a
macro model – Often an expression of input to output delay, power
dissipation, noise, and circuit gain as functions of input voltage ramp
rates, frequencies, load capacitances, device parameters, supply voltages,
and temperatures.
In other cases, circuits are simulated and designed with SPICE and
compact models directly. For instance, an entire memory chip may be
simulated with SPICE. Very often, large circuits are divided into smaller
blocks each containing hundreds or thousands of transistors for SPICE
simulation in order to complete the circuit simulation in hours rather than
days or even weeks. In order to speed up the simulation of even larger
circuits including SRAM memory circuits, another class of SPICE, “fast
SPICE simulators”, are utilized to obtain satisfactory accuracy but with
only a fraction of SPICE simulation time. This is accomplished with a
combination of techniques including circuit partitioning and building
table models of transistor characteristics rather than evaluating the
equations of the compact model for every iteration at every time point.
However, tables are still built from model equations. Therefore, nearly
all ICs are designed with the use of transistor compact models.

Chapter 1. BSIM and IC Simulation
Section 1.3 BSIM3 – A Compact Model Based on New MOSFET Physics
3
1.2 BSIM – The Beginning
BSIM stands for Berkeley Short-channel IGFET Model. IGFET
(Insulated-Gate Field Effect Transistors) is an older, more generic name
for MOSFET transistors. BSIM’s genesis can be traced back to 1984 [1 –
2]. This work produced BSIM1. Later Min-Chie Jeng working with Ping
Ko and Chenming Hu introduced a successor version BSIM2 [3].
Hu and Ko had a close research collaboration in MOSFET physics
and technology. The BSIM research was funded by the Semiconductor
Research Cooperation (SRC), a consortium of semiconductor companies
that funds university research projects deemed important to the IC
industry. Their research into the more fundamental device physics and
behaviors of advanced MOSFETs attracted additional industry supports.
In this way, they gradually built a collection of models for the Vth
(threshold voltage) dependence on biases and gate lengths, mobility
degradation, velocity saturation effects, output conductance, unified
flicker noise theory, SOI, and gate tunneling leakage. Eventually, these
models became the building blocks of later BSIM models.
1.3 BSIM3 – A Compact Model Based on New MOSFET Physics
Most IC simulations require the accuracy to be better than a few percent
from linear to saturation and from subthreshold to strong inversion
covering a current range from pA/µm to mA/µm. This accuracy is
achieved by painstaking modeling of many physical phenomena in a
modern MOSFET including electrostatic, materials, quantum, and
thermal effects. When another student Jian-Hui Huang started to work on
a new version of BSIM around 1991, it was decided that the new version
would incorporate some of the new original physical models mentioned
in the previous sub-section. This approach was a marked departure from
all previous compact models. Those models opted for simple equations
favoring the reliance on “fitting” the transistor data to simplistic model
equations over the use of physical, predictive, and complex models. The
decision was a gamble that physics-based models can justify the model
computational cost with their better accuracy and robustness. This new

4
approach began modestly with more accurate models of Vth and the drain
saturation voltage, Vdsat [4] and an accurate model of the output
conductance of MOSFETs [5]. The output conductance is very important
to the accurate simulation of analog circuits because it determines the
voltage gains of amplifying circuits. The result was BSIM3 [6]. BSIM3
was soon recognized as being far superior to the other compact models of
that time.
For example, the output conductance is no longer explained by just
channel length modulation but two additional mechanisms — drain-
induced barrier lowering (DIBL) and hot carrier induced body bias
effects [5]. Each of these three mechanisms in turn is modeled with
insights derived from research on the quasi-two-dimensional analysis of
the velocity saturation region near the drain [4], the effect of channel
length and drain voltage on the threshold voltage [7], and the hot-
electron current [8]. For the first time, a compact model can model the
output conductance in a way that is not only accurate but also predictive
of the effects of changing the gate oxide thickness, junction depth, and
the threshold voltage. On the other hand, Reference [7] is the basis of
BSIM3’s predictive Vth roll-off model, and Reference [8] is the basis of
the substrate current model.
Another example is the gate induced-drain leakage or GIDL [9], the
band-to-band tunneling current induced by the gate-to-drain voltage Vgd.
Once the mechanism was clearly understood, a simple analytical model
became obvious and proved to be accurate.
Yet another example is the flicker noise or 1/f noise. The unified
flicker noise model incorporates both the fluctuation in the number of
inversion layer charge carriers (the number fluctuation) and the
fluctuation in the Coulombic scattering mobility (the mobility
fluctuation). They are correlated because both are caused by the
fluctuation in the number of trapped charges in the SiO2 near the
silicon/SiO2 interface [10]. This model was characterized in detail using
the random telegraphic noise measurements that can only be observed in
transistors with very short lengths and narrow widths such that a
transistor may contain only one or two oxide traps [11]. These physics
studies led to an accurate compact model of the MOSFET flicker noise
[12].

Section 1.4 BSIM3v3 – World’s First MOSFET Standard Model
5
1.4 BSIM3v3 – World’s First MOSFET Standard Model
BSIM3 was released in 1993. In that year, Ko moved to Hong Kong but
stayed involved with BSIM for several more years. Hu continued to
improve the physical accuracy by modeling poly-silicon depletion,
universal mobility based on Vth and the gate voltage Vgs [13]. More
important, the subthreshold and inversion regions of operation are now
modeled with a single continuous function, Vgsteff. Verified with careful
split-capacitance measurements, this model was a major improvement
[14]. Similarly the linear and saturation regions are modeled with a
single function, rather than piecewise formulations in practice then,
through a continuous effective drain-to-source voltage Vdseff. These
changes eliminated glitches in high-order derivatives of MOSFET drain
current.
Encouraged by the early favorable reactions from the industry,
BSIM3 began to emphasize robustness and usability for various CMOS
technologies. BSIM was to be maintained and supported as a tool that
billion-dollar companies may depend on for operation. In other words,
impact to the industry joined creation of knowledge as an explicit goal of
the BSIM project. Efforts were made to scrub thousands of lines of C-
code for possible occurrences of numerical problems such as divide-by-
zero, square-root-of-negative, round-off, discontinuities and over/under-
flows that would cause circuit simulation to abort. It also meant
timely releases of bug fixes and active communications with users via
numerous emails and the BSIM release website, http://www-
device.eecs.berkeley.edu/~bsim3/. BSIM3v3 won the R&D 100 Award
from the R&D Magazine as one of the most significant R&D products of
1995. These efforts culminated in a robust productized release of
BSIM3v3 [15, 16, 17].
The semiconductor foundry industry was beginning to grow. A
foundry gives its customers, the circuit design companies, basically these
inputs to undertake the design process: Compact models such as BSIM, a
set of geometrical and electrical design rules, and reference design flows.
The foundry is then obligated to deliver working products of the designs
that the customers may create with these inputs. To both parties, a very
close agreement between the models and all the behavioral details of
transistors is of paramount importance. One practical way to eke out the

6
last few percents of accuracy is a pedestrian technique called binning,
making model parameters themselves functions of transistor channel
lengths and widths, such that a single set of model parameters can apply
to all transistors manufactured with the same process recipe.
Inspired by the success of BSIM3v3, several companies started to
organize a movement to standardize a compact model. The purpose was
to promote the adoption of a standard model by the IC industry. At that
time, most large semiconductor companies developed their own
transistor models. Often a single company would have many models in
active use at the same time. Smaller companies would license models
from CAD tool companies. There were many dozens of MOSFET
models in use and the resources expended by each company to maintain
these models and to fit each new generation of transistors to multiple
models were enormous. This problem was aggravated by the dual trends
of increasing inter-company and international collaborations and the
growing foundry-fabless business model. Both trends would be well
served if all the companies use the same model.
In 1996, Sematech, another semiconductor industry consortium,
organized a series of workshops to discuss whether and how to select a
standard model. This led to the formation of the Compact Model Council
(CMC) that defined and executed the year-long process of selecting an
industry standard MOSFET model. Several models competed in the
selection process. In 1997, BSIM3v3 was selected by CMC as the
world’s first standard transistor model for IC simulation. The industry
rallied around BSIM. Since then, BSIM3v3 has been employed for the
0.5µm, 0.35µm, 0.25µm, 0.18µm, and 0.15µm technology nodes.
1.5 BSIM4 – Aimed for 130nm Down to 20nm Nodes
BSIM continues. With the release of BSIM4 [18] in 2000 by Weidong
Liu, Xiaodong Jin, Kanyu M. Cao, and Chenming Hu, BSIM was able to
support the sub-130nm CMOS technologies and the growth of
high-speed analog, mixed-signal, as well as radio-frequency (RF)
CMOS integrated circuits that powered new lifestyle including wireless
applications of the 21st
century. A major new model is the physical

Section 1.7 Impact of BSIM
7
holistic noise model for the channel thermal noise and the induced gate
noise [19, 20]. The induced gate noise and its correlation with the
channel thermal noise are modeled. Accuracy at high frequencies up to
the cut-off frequency of transistors is achieved with a simple intrinsic
input resistance (Rii) model. A substrate resistance network was added.
A novel quantum effect model called the charge layer thickness model
was introduced [21]. The first gate direct-tunneling leakage current
model was also introduced to anticipate the rise of gate leakage currents
[22]. The pocket implant effect in advanced MOSFETs was introduced
[23]. The layout-dependent effects from mechanical stress and well
proximity were modeled. The modeling of high-k metal-gate stacks and
non-silicon materials became possible. BSIM4 has been used for the
0.13µm, 90nm, 65nm, 45/40nm, 32/28nm, and 22/20nm technology
nodes.
1.6 BSIM SOI
In parallel, the BSIM team developed a compact model for SOI-
MOSFETs, BSIMSOI. Naturally, BSIM SOI shares many features and
model modules from BSIM3 and BSIM4. It took major efforts to develop
a floating-body model [24] as well as a self-heating model [25, 26],
which required the use of a thermal sub-circuit to model the history
dependencies of the underlying physical phenomena. BSIM SOI has
served several major semiconductor companies for SOI-CMOS IC
products.
1.7 Impact of BSIM
Upon the selection of BSIM as the industry standard model in 1997, all
the foundry companies quickly adopted BSIM. This led to hundreds of
fabless companies to design all their products using BSIM since then.
Gradually, integrated design-manufacturing (IDM) companies gave up
their own proprietary compact models and migrated to BSIM. A few
companies continued to use their own proprietary models but also used
BSIM so as to facilitate the collaborations with other companies.

8
Most of the ICs using 0.5µm and newer technologies since 1997 were
designed with BSIM. That amounts to a trillion US dollars worth of ICs.
1.8 Looking Towards the Future – The Multi-Gate MOSFET Model
As the CMOS technology continues to scale down, the device drain
terminal is pulled closer to the middle of the channel. This increases the
capacitive coupling between the drain and the channel, producing
unwanted/unduly short-channel effects such as standby channel leakage
currents. This is the biggest problem facing the nearly five-decade long
planar CMOS transistor structure.
FinFETs [27] allow the gate to control the channel from three sides of
the channel, hence the term CMG (common multiple gates), which
increases the gate control and allowing the gate length to be further
scaled down. Since the introduction of FinFETs, this structure has set the
world’s records of the smallest gate length several times at various
research laboratories. The current record is held at three nanometers.
BSIM-CMG [28] is a compact model for the class of common multi-
gate FET devices. This model has been extensively validated with
advanced multi-gate CMOS technologies, both SOI and bulk. It is
reviewed as an example of a compact model to serve multi-gate CMOS
technologists and circuit designers to facilitate the transition from the
planar CMOS to the multi-gate vertical CMOS era.
1.9 The Intent of This Book
Modeling ideal prototypical CMOS devices well is one thing, but
modeling myriad real devices of numerous technology generations well
is the hallmark of BSIM. BSIM4 is no exception and it is by far the most
sophisticated and widely used compact MOSFET model. It has served
innumerable device technologists, design automation engineers as well
as IC designers around the world for half a dozen CMOS technology
nodes.

References
9
This book is intended to present and analyze in depth the BSIM4
theory, hands-on techniques, and methodology that can take a compact
model from its prototype into a production-worthy version. It covers
MOSFET device operation and physics, manufacturing process effects,
model formulations, parameter extraction, SPICE implementation, and
their implications to integrated circuit design.
This book is written for BSIM users, undergraduate and graduate
students in EE, and those that make their professions in those areas.
References
[1] Bing. J. Sheu, D. L. Scharfetter, Chenming Hu, and D. O. Pederson, “A compact
IGFET charge model,” IEEE Trans. Circuits and Systems, vol. CAS-31, no. 8, pp.
745-748, August 1984.
[2] Bing. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, “BSIM: Berkeley short-
channel IGFET model for MOS transistors,” IEEE Journal of Solid-State Circuits,
vol. 22, no. 4, pp. 558-566, August 1987.
[3] M. C. Jeng, P. K. Ko, and C. Hu, “A deep submicron MOSFET model for
analog/digital circuit simulations,” Tech. Dig. of IEDM, pp. 114-117, San
Francisco, December 1988.
[4] K. Y. Toh, P. K. Ko, and R. G. Meyer, “An engineering model for short-channel
MOS devices,” IEEE Journal of Solid-State Circuits, vol. 23, no. 4. pp. 950-958,
August 1988.
[5] J. H. Huang, Z. H. Liu, M. C. Jeng, P. K. Ko, and C. Hu, “A physical model for
MOSFET output resistance,” Tech. Dig. of IEDM, pp. 569-572, San Francisco,
December 1992.
[6] J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, M. Chan, P. K. Ko, and C. Hu, “BSIM3
Manual”, University of California, Berkeley, 1993.
[7] Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and Y. C. Cheng,
“Threshold voltage model for deep-submicrometer MOSFET's,” IEEE Trans. on
Electron Devices, vol. 40, no. 1, pp. 86-95, January 1993.
[8] Chenming Hu, Simon C. Tam, Fu-Chieh Hsu, Ping-Keung Ko; Tung-Yi Chan; K.
W. Terrill, “Hot-electron induced MOSFET degradation – Model, monitor, and
improvement,” IEEE Trans. Electron Devices, vol. ED-32, pp. 375-385, February
1985, and IEEE Journal Solid-State Circuits, vol. SC-20, pp. 295-305, February
l985.

10
[9] T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, “The impact of gate-induced drain
leakage current on MOSFET scaling,” Tech. Dig. of IEDM, pp. 718-721,
Washington D. C., December 1987.
[10] K. K. Hung, P. K. Ko, C. Hu, and Y.C. Cheng, “A unified model for the flicker
noise in metal-oxide-semiconductor field-effect transistors,” IEEE Trans. on
Electron Devices, vol. 37, no. 3, pp. 654-665, March 1990.
[11] P. Fang, K. K. Hung, P. K. Ko, and Chenming Hu, “Characterizing a single hot-
electron-induced trap in submicron MOSFET using random telegraph noise,”
Digest of Tech. Papers of Symp. on VLSI Technology, pp. 37-38, Honolulu,
Hawaii, June 1990.
[12] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A physics-based MOSFET noise
model for circuit simulators,” IEEE Trans. Electron Devices, vol. 37, no. 4, pp.
1323-1333, May 1990.
[13] Kai Chen, H. C. Wann, J. Dunster, P. K. Ko, Chenming Hu, and M. Yoshida,
“MOSFET carrier mobility model based on gate oxide thickness, threshold and
gate voltages,” Solid-State Electronics, pp. 1515-1518, October 1996.
[14] Yuhua Cheng, Kai Chen, K. Imai, and Chenming Hu, “A unified MOSFET channel
charge model for device modeling in circuit simulation,” IEEE Trans. on
Computer-Aided Design of Integrated Circuits and Systems, pp. 641-644, August
1998.
[15] Yuhau Cheng, Mie-Chie Jeng, Zhihong Liu, Mansun Chan, J. H. Huang, Kai Chen,
P. K. Ko, and Chenming Hu, “A physical and scalable I–V model in BSIM3v3 for
analog/digital circuit simulation,” IEEE Trans. Electron Devices, pp. 277-287,
1997.
[16] Yuhua Cheng and Chenming Hu, “MOSFET modeling and BSIM3 user's guide,”
Kluwer Academic Publishers, 1999.
[17] Weidong Liu, Xiaodong Jin, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua
Cheng, Kai Chen, Mansun Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K.
Ko, and Chenming Hu, “BSIM3v3.2 MOSFET model  Users’ manual”,
Memorandum No. UCB/ERL M98/51. Electronics Research Laboratory, College of
Engineering, University of California, Berkeley, August 21, 1998.
[18] Weidong Liu, Xiaodong Jin, Kanyu M. Cao, and Chenming Hu, “BSIM4.0.0
MOSFET model – User’s manual,” Memorandum No. UCB/ERL M00/38,
Electronics Research Laboratory, College of Engineering, University of California,
Berkeley. August 3, 2000.
[19] Xiaodong Jin, Jia-Jiunn Ou, Chin-Hung Chen, Weidong Liu, M. Deen, P. R. Gray,
and Chenming Hu , “An effective gate resistance model for CMOS RF and noise
modeling,” Tech. Dig. of IEDM, pp. 961-964, San Francisco, December 1998.
[20] Jia-Jiunn Ou, Xiaodong Jin, Chenming Hu, and P. R. Gray, “Submicron CMOS
thermal noise modeling from an RF perspective,” VLSI Technology Symposium,
pp.151-152, 1999.

References
11
[21] Weidong Liu, Xiaodong Jin, Ya-Chin King, and C. Hu, “An efficient and accurate
compact model for thin-oxide MOSFET intrinsic capacitance considering the finite
charge layer thickness,” IEEE Trans. Electron Devices, pp.1070-1072, May 1999.
[22] Kanyu M. Cao, W. C. Lee, Weidong Liu, Xiaodong Jin, Pin Su, S. K. H. Fung,
Judy X. An, B. Yu, and Chenming Hu, “BSIM4 gate leakage model including
source-drain partition,” Tech. Dig. of IEDM, pp. 815-818, San Francisco,
December 2000.
[23] Kanyu Mark Cao, Weidong Liu, Xiaodong Jin, Karthik Vasanth, Keith Green, John
Krick, Tom Vrotsos, and Chenming Hu, “Modeling of pocket implanted MOSFETs
for anomalous analog behavior,” Tech. Dig. of IEDM, pp. 171-174, Washington
D. C., December 1999.
[24] Mansun Chan, Pin Su, Hui Wan, C. H. Lin, Samuel K.-H. Fung, A. M. Niknejad,
Chenming Hu, and P. K. Ko, “Modeling the floating-body effects of fully depleted,
partially depleted, and body-grounded SOI MOSFETs, ” Solid State Electronics,
pp. 969-978, June 2004.
[25] Wei Jin, Weidong Liu, S. K. H. Fung, P. C. Chan, and Chenming Hu, “SOI thermal
impedance extraction methodology and its significance for circuit simulation,”
IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 730-736, April 2001.
[26] Hui Wan, Pin Su, Samuel K. H. Fung, A. Niknejad, and Chenming Hu, “RF
modeling for FDSOI MOSFET and self heating effect on RF parameter extraction,”
NanoTech Workshop on Compact Modeling, 2002.
[27] Xuejue Huang, Wen-Chin Lee, Charles Kuo, D. Hisamoto, Leland Chang,
J. Kedzierski, E. Anderson, H. Takeuchi, Yang-Kyu Choi, K. Asano, K, V.
Subramanian, Tsu-Jae King, J. Bokor, and Chenming Hu, ”Sub-50 nm FinFET:
PMOS ”, Tech. Dig. of IEDM, pp. 67-70, Washington D. C., December 1999.
[28] M. V. Dunga, Chung-Hsun Lin, D. D. Lu, Weize Xiong, C. R. Cleavelin, P.
Patruno, Jiunn-Ren Hwang, Fu-Liang, A. M. Niknejad, and Chenming Hu “BSIM-
MG: A versatile multi-gate FET model for mixed-signal design,” VLSI Technology
Symposium, pp. 60-61, Kyoto, June 2007.

13
Chapter 2
Fundamental MOSFET Physical Effects and
Their Models for BSIM4
2.1 Introduction and Chapter Objectives
This chapter presents and analyzes the fundamental physical effects in
the modern MOSFET transistor and their mathematical formulations in
BSIM4. In order to make this task easy, Section 2.1 will first introduce to
the readers the basic terminologies, definitions, and geometry, and the
material model options of BSIM4. The model options are intended to
facilitate the customization of BSIM4 for various gate and channel
geometries, model card and parameter binning, and gate and channel
building materials such as high-k metal gate stacks and silicon/non-
silicon substrates.
Following this, in the subsequent sections of this chapter, will be the
detailed presentations and discussions of the fundamental physical
effects found in a modern MOSFET device structure and the modeling
methodology of these physical effects in BSIM4. The topics herein
include the device channel surface potential and threshold voltage, poly-
silicon gate depletion, bulk-charge effects, LDD (Lightly-Doped
Drain/source) resistance, inversion charge layer thickness owing to the
quantum mechanical effects, carrier mobility, and layout-dependent
mechanical stress and well-proximity effects.
Accurate modeling of these effects is of paramount importance for
circuit simulation. This is because these effects are so fundamental that
they determine how a MOSFET transistor operates. This is also because
they serve as the foundation for the accurate modeling of the various
device charges (Q), currents (I), trans-conductances (G) and trans-
capacitances (C), which are the constituents of the circuit equations that a
SPICE simulator solves. Thus, this chapter also serves to prepare the

14
readers to understand the presentation of the chapters to follow in this
book.
Robust convergence in numerical computations is prerequisite for
successful circuit simulation. Fast simulation improves the turnaround
time of circuit design and tapeout. The SPICE implementation of BSIM4
pays unparalleled attention to the details and optimization of numerical
robustness and computational efficiency, which leads to up to ten times
speedup of a BSIM4 C-code implementation over its Verilog-A
implementation. Some of these implementation techniques will be
exemplified and discussed in this chapter as well as the subsequent chapters.
2.2 Gate and Channel Geometries and Materials
2.2.1 Gate and Channel Lengths and Widths
BSIM4 defines several different gate and channel lengths and widths.
These parameters are needed to represent advanced CMOS process
implementations and circuit design practices. The first is the drawn
length (Ldrawn) and width (Wdrawn) of the gate. They are specified in the
instance statement cards of SPICE MOSFET elements to designate the
drawn geometries. Their values are sometimes scaled by a unit-
conversion (for instance, from micrometers to meters in the MKS unit
system) or a size-scaling factor. An example is the shrinking from one
technology node to its half node or to the next full node of process
technologies. This mechanism is used to facilitate the reuse of existing
circuit netlists by applying a multiplying factor to Ldrawn and Wdrawn to
obtain Ldesigned and Wdesigned, instead of regenerating a new netlist from
scratch. These are the gate geometries that designers want to use with a
particular process technology.
The actual size of the fabricated or physical gate (Lphysical and Wphysical)
can deviate from Ldesigned and Wdesigned, either because of unintentional
process variations and/or from intentional gate size reduction performed
to achieve better performance as a result of a larger device driving
current. To model this important process effect within SPICE, BSIM4
introduces two new model parameters XL and XW such that the physical
gate length and width become

Chapter 2. Fundamental MOSFET Physical Effects and Their Models for BSIM4
Section 2.2 Gate and Channel Geometries and Materials
15
= + XL (2.1a)
and
=

NF
+ XW (2.1b)
where NF (default value = 1) represents the number of fingers of a multi-
finger MOSFET structure, which is preferred over a wider single finger
in high-speed circuits such as RF ICs. XL and XW have default values of
zero. They are extracted from silicon test transistor data and typically
have negative values with a magnitude of a few nanometers resulting
from intentional trimming of the gate size.
Yet another set of channel length and width are their effective values.
They differ from their physical values, owing to the overlap or underlap
between the gate and the source and drain diffusions (∆L) and the gate
control over the channel edge adjacent to the shallow trench isolation
(∆W). BSIM4 models these dimensions as
∆ = LINT +
LL
!#$%'
LLN +
LW
#$%'
LWN +
LWL
!#$%'
LLN
∙#$%'
LWN
(2.2a)
and
∆ = WINT +
WL
!#$%'
WLN +
WW
#$%'
WWN +
WWL
!#$%'
WLN
∙#$%'
WWN
(2.2b)
LINT and WINT are the delta L and delta W of large devices, those with
large Lphysical and Wphisical. LINT can be extracted from the measured
Vds/Ids versus Ldesigned of a few large devices. Likewise, WINT can be
extracted from measured data of Ids/Vds versus Wdesigned. Other parameters
of the above formulas are the length and width dependence model
parameters that improve the model accuracy over a wide range of the
gate length and width.
The effective channel length and width used for the BSIM4 DC IV
models are
)) = − 2 ∙ ∆ (2.3a)
and
)) = − 2 ∙ ∆ (2.3b)

16
The junction diode IV and CV and the gate-induced drain/source
leakage (GIDL/GISL) current models use a different effective width
because of subtle corner effects at the width-ends of the channel. It is
)),-. = − 2 ∙ ∆,-. (2.4)
where
∆,-. = DWJ +
WLC
!#$%'
WLN +
WWC
#$%'
WWN +
WWLC
!#$%'
WLN∙#$%'
WWN
(2.5)
with DWJ being the overlap length in the width direction. Other
parameters are the length and width dependence model parameters to
improve the model scalability.
The MOSFET intrinsic and overlap capacitances are determined by
the region between the source-body and drain-body junctions. BSIM4
uses yet another set of effective channel length and width for these
capacitance models
))-1 = − 2 ∙ ∆-1 (2.5a)
and
))-1 = − 2 ∙ ∆-1 (2.5b)
where the gate-channel overlaps are
∆-1 = DLC +
LLC
!#$%'
LLN +
LWC
#$%'
LWN +
LWLC
!#$%'
LLN
∙#$%'
LWN
(2.6a)
and
∆-1 = DWC +
WLC
!#$%'
WLN +
WWC
#$%'
WWN +
WWLC
!#$%'
WLN
∙#$%'
WWN
(2.6b)
with DLC being the overlap length and width and other parameters being
the length and width dependence model parameters.
2.2.2 Model Card and Parameter Binning
SPICE model parameter extraction tools can be configured to generate
two different types of SPICE model parameter cards from a group of test
devices with varying channel lengths and widths. They are global models
and binned models.

17
A global model uses a single model card, i.e., a single set of model
parameters, relying only on the model equations to accurately reproduce
the nuanced electrical characteristics of transistors of any combinations
of Ldesigned and Wdesigned. Building a global model requires significant
extraction efforts aided by specialized software tools in order to attain
satisfactory accuracies. Success depends on the quality of a model, i.e.,
its equation formulations and the expertise applied in parameter
extractions. A global model produces smoother dependence of device
behaviors on device geometries than a binned model.
In contrast, a binned model uses multiple, perhaps dozens model
parameter cards, i.e., sets of model parameters, to model different ranges
of geometries. For example, one model card is used for L 1 µm and W
1 µm, a second model card is used for 1 µm L 0.3 µm and W 1
µm, and a third model card is used for another range. Each of these
parameter cards is called a bin. Since each model card needs to represent
only a small range of L and W combination, parameter extraction can be
easier for a model card but many model cards need to be generated. One
shortcoming is that the binned model is not a smooth function of L and
W. Moreover, the size of a model library increases with the number of
bins, leading to extra overhead in library maintenance as well as
repetitive parameter parsing/setup and more memory usage during
SPICE simulations.
In either of these two scenarios, model card selection parameters,
such as LMIN, LMAX, WMIN and WMAX in the case of BSIM4, are
required to clarify the range of designed gate lengths and widths, for
which the model cards provide adequate accuracy. Note that for multi-
finger devices, the length and width values here refer to those of one
transistor finger.
In either a global or binned model, a subset of the model parameters
are formulated as simple functions of Leff and Weff. This practice improves
model accuracy and makes parameter extraction easier, particularly in
the case of generating a global model. In binned models, usually only
this same subset of model parameters are binned and the rest of the
model parameter are not binned. This subset is known as the binnable
parameters.
Take the BSIM4 VTH0 parameter as an example. This base
parameter is given three binning parameters: LVTH0, WVTH0, and
PVTH0. They are provided to improve the accuracy of threshold voltage
fitting over all combinations of channel length and width. BSIM4 and

18
BSIM3v3 have used the same parameter binning scheme successfully for
many technology nodes. The formulation of this scheme is simple and it
computes the value of the binned VTH0 as
VTH07899:; = VTH0 +
LVTH0
!
+
WVTH0

+
PVTH0
!∙
(2.7)
These binning parameters default to zero. Their dimensions are chosen
such that every term in Eq. (2.7) has the same unit as that of the base
parameter VTH0.
In the above equation, the effective channel length and width are
given in the unit of micrometers. BSIM4 provides a binning parameter
value scaling selector, BINUNIT. When it is set to 0, Eq. (2.7) is used.
When it is set to 1 (the default case), Eq. (2.7) changes to
VTH07899:; = VTH0 +
LVTH0∙?@A
!
+
WVTH0∙?@A

+
PVTH0∙?@BC
!∙
(2.8)
This means that device channel lengths and widths used in model card
extraction are given in meters. Eqs. (2.7) and (2.8) must give the same
value regardless of which unit is used in extraction and circuit net-listing.
The value of BINUNIT (in model libraries) is set by model extraction
engineers.
2.2.3 Gate Stack and Substrate Material Model Options
The continual scaling of CMOS technologies needs to keep the power
consumption issue contained. Power consumption includes the dynamic
(proportional to Vdd squared) and the static (due to leakage currents
through the channel as well as the tunneling current between the gate and
other terminals). Power supplies (Vdd) have been reduced aggressively
below 1 volt. However, lower power supply voltages lead to lower
transistor and circuit speed and weaken the gate control over turning on
and off MOSFET devices. In fact, reduced gate voltage requires thinner
gate oxide thickness (about 1 nanometer or three molecular layers of
SiO2) in order to keep transistor current and circuit speed high. One
drawback of the thin oxide is that it degrades the mobilities of channel
charge carriers. As counter measures, techniques such as strained silicon
and non-silicon channel material have been employed or are being
developed for advanced planar CMOS process technologies. Another

19
drawback of thin SiO2 is excessive gate tunneling currents and static
leakage. The counter measure is to employ a high-k gate dielectric to
increase the gate insulator thickness in order to reduce the gate tunneling
current and to employ a metal gate material in order to reduce or
eliminate the poly-silicon gate depletion effect. This section will discuss
the BSIM4 modeling of non-Si channel and high-k metal gate
technologies. The modeling of the mechanical stress effect will be
presented later in this chapter.
Inside an n+
-poly/oxide/p-Si (NMOS) or p+
-poly/oxide/n-Si (PMOS)
transistor structure, there exist two physical effects that make the
electrical gate oxide thickness (TOXE) thicker than the physical oxide
thickness, TOXP. One is the poly-Si gate depletion when the gate bias is
high. The other is the significant channel charge layer thickness that is a
quantum mechanical effect. Both effects will be analyzed shortly. They
bring about a difference, DTOX, between TOXE and TOXP. TOXE or
DTOX is bias dependent. In practice, however, TOXE is usually taken as
a constant and determined from measured gate capacitance Cgg data at Vg
= Vdd [1], [2].
In the BSIM4 implementation, when all these three model parameters
(given in the unit of meters) are specified in model card libraries, DTOX
will be ignored. If TOXE is given but not TOXP, then TOXP is
computed to be (TOXE – DTOX), and vice versa. The electrical gate
oxide capacitance is
EFG =
HIJ
TOXE
=
K.KLMK×?@BC∙EPSROX
TOXE
(2.9)
where EPSROX is the model parameter for the relative dielectric
constant of SiO2 and has a default value of 3.9. If the gate dielectric layer
is not SiO2, say an oxynitride SiOxNy layer, then EPSROX can be
explicitly specified to be different from 3.9 and an equivalent TOXE can
again be extracted from Cgg with the given EPSROX. Coxe is used to
compute the threshold voltage, subthreshold swing factor, mobilities,
bulk-charge effect coefficient Abulk, effective and smoothing gate (Vgsteff)
and drain (Vdseff) voltages, and CAPMOD = 0 and 1 capacitance models
of BSIM4. Similarly, the physical gate oxide capacitance is
EFG =
HIJ
TOXP
=
K.KLMK×?@BC∙EPSROX
TOXP
(2.10)

20
It is used to compute the BSIM4 effective gate oxide capacitance Coxeff
for the channel current and CAPMOD = 2 capacitance models, which
take into account the finite channel charge layer thickness effect.
Note that in the case of poly-Si/oxide/Si device structures, the
permittivity of the silicon substrate is εsub = 1.03594 ⋅ 10-10
Farad/meter.
This quantity is used to compute other BSIM4 parameter values in the
sections and chapters to follow in this book.
In order to account for all material cases other than poly-Si/oxide/Si,
BSIM4 provides a new-material model selector MTRLMOD. It has two
possible settings, 0 (the default) and 1. MTRLMOD = 0 applies to the
classical poly-Si/SiO2/Si scenario. When MTRLMOD = 1 is chosen,
device structures other than poly-Si/Oxide/Si, such as a high-k metal gate
stack, and a non-Si substrate material, such as germanium or SiGe, can
be modeled. In the latter case, one needs to extract, from measured gate
capacitance Cgg an equivalent oxide thickness (EOT) relative to SiO2
with EPSROX = 3.9. EOT can be specified explicitly or can be
substituted for TOXE in BSIM4 model card libraries. EOT needs to be
obtained under the inversion condition with a gate bias of VDDEOT, a
model parameter denoting the power supply voltage designated for a
particular manufacturing process. With this, the electrical gate dielectric
capacitance is calculated in the same way as Coxe above. The same holds
true for the physical gate dielectric capacitance Coxp as MTRLMOD = 0.
Note that in the case of MTRLMOD = 1, TOXP does not need to be
specified because BSIM4 provides an auxiliary code snippet to have it
computed automatically. It subtracts from TOXE or EOT the
contributions from poly gate depletion and channel charge layer
thickness effects. In order to do so, a few model parameters of
MTRLMOD = 1 have to be supplied to specify the condition at which
TOXP is extracted. They are the temperature (TEMPEOT), the effective
channel length (LEFFEOT) and width (WEFFEOT), and VDDEOT.
For a non-Si channel material, the substrate permittivity now
becomes εsub = (8.85418 ⋅ 10-12
⋅ EPSRSUB) in the unit of Farad/meter,
where EPSRSUB is the substrate relative dielectric constant of a non-Si
substrate material. EPSRSUB has a default value of 11.7 for a silicon
substrate.

Section 2.3 Temperature-Dependence Model Options
21
There are a few other device parameters, such as the energy-band
gap, Eg, the intrinsic carrier concentration ni, and the flat-band voltage,
on which MTRLMOD has effects. They will be discussed in the ensuing
sections and chapters.
2.3 Temperature-Dependence Model Options
BSIM4 provides four options for modeling the temperature dependencies
of multiple device parameters, such as the energy-band gap (Eg), intrinsic
carrier concentration (ni), thermal voltage, surface potential, threshold
voltage, flat-band voltage, carrier velocity and mobility, parasitic
resistances, junction built-in potential, junction leakage current and
capacitances. Each option is turned on by specifying a model parameter
selector TEMPMOD in model cards. TEMPMOD has four possible
values, which are 0 (the default), 1, 2 and 3. The temperature
dependencies of these parameters will be presented throughout this book.
In this section, only Eg and ni are discussed.
For the silicon substrate (MTRLMOD = 0), the energy band gap in
the unit of volt at nominal (TNOM) and operating (Temp) temperatures is
P ?(TNOM) = 1.16 −
Q.?R∙?@S∙TNOM
C
T??.LU?K
(2.11)
and
P VW XY = 1.16 −
Q.?R∙?@S∙.Z
C
.ZU?K
(2.12)
The intrinsic carrier concentration in the unit of cm-3
at TNOM is
[(TNOM) = 1.45 ∙ 10?
∙
TNOM
T??.L
]
T/R
∙ exp bc ∙
d(T??.L)edf(TNOM)
R∙gh∙TNOM
i
(2.13)
where kB = 1.3806226⋅10-23
in the unit of J⋅K-1
is the Boltzmann constant.
For a non-silicon substrate (MTRLMOD = 1), a few material
parameters are introduced. The energy-band gap at nominal (TNOM) and
operating (Temp) temperatures is
P ?(TNOM) = BG0SUB −
TBGASUB∙TNOM
C
T??.LUTBGBSUB
(2.14)
and

22
P VW XY = BG0SUB −
TBGASUB∙.Z
C
.ZUTBGBSUB
(2.15)
The intrinsic carrier concentration at TNOM is
[(TNOM) = NI0SUB ∙
TNOM
T??.L
]
T/R
∙ exp bc ∙
d(T??.L)edf(TNOM)
R∙gh∙TNOM
i
(2.16)
Here BG0SUB is the energy-band gap at 0 degree Kelvin, TBGASUB
and TBGBSUB are the temperature-dependence parameters of the
energy-band gap, and NI0SUB is the intrinsic carrier concentration at
300.15 degree Kelvin. Note that 300.15 (= 273.15 + 27) degree Kelvin is
the reference ambient temperature of SPICE3. Both TNOM and Temp
default to 300.15 degree Kelvin. Commercial SPICE simulators may
have different default values for these two temperatures.
2.4 Threshold Voltage
The threshold voltage Vth of a MOS transistor is a very important and
useful parameter for CMOS and BSIM4. It determines how the transistor
operates and behaves. Circuit designers can choose a high-performance
(HP; low Vth), low-power (LP; high Vth) process technology (flavor) or
something inbetween that differs mostly in Vth. For each type of these
processes, the designers are also given the choices of two or three
different Vth’s to further optimize their chip speed and power
consumption. Therefore, accurate modeling of Vth is a must, regardless of
whatever compact modeling approach is to be taken.
BSIM4 does this by formulating the process and physical effects in a
comprehensive manner. This section will present and analyze the
formulations and the thinking behind them.
2.4.1 Long Channel with Uniform Substrate Doping
Take a large NMOS transistor with uniform channel doping NSUB for
example. When a positive and large enough gate-to-body voltage Vgb is
applied such that the energy-band bending in the channel surface region

Section 2.4 Threshold Voltage
23
reaches 2jk, the surface region is depleted of holes and an inversion
layer of electrons starts to form with a surface electron density equal to
that of the holes found in the bulk substrate. According to the charge
neutrality requirement, the charge density per unit area at any location y
in the surface inversion layer is
cl(m) = −Eno: ∙ pq r − VFB − s(m)t − cr(m) (2.17)
Note that the first term bracketed without the minus sign on the right-
hand side denotes the gate charge density qg(y) and the voltage/potential
terms in the square brackets give the voltage drop Vox across the gate
dielectric/oxide layer. VFB is the flat-band voltage. qb(y) in the above
equation is the density of the body charge in the body depletion region. It
is obtained by solving the Poisson equation for the surface region
cr(m) = −EFG ∙ u ∙ vs(m) (2.17a)
γ is the process technology-dependent body-bias coefficient of the body
charge model
u =
vR∙Hwx∙y∙NSUB
-IJ
(2.17b)
Φs(y) of the above equations is the surface potential relative to the
bulk. It is equal to zj(m) + qr{, where j(m) also denotes the surface
potential, but with the source terminal voltage as the reference. In the
modeling and analysis of MOSFET device operation, this is an important
distinction to note. When the source-body voltage Vsb is zero, these two
surface potentials will be the same. Fig. 2.1 gives a graphical illustration.
With these, Eq. (2.17) is transformed into the following
cl(m) = −EFG pq − (VFB + 2jk) − q(m) − γv2jk − qr + q(m)t
(2.18)
Under inversion, the surface potential is taken as
s(m) = j − qr + q(m) = 2jk − qr + q(m) (2.18a)
Here ϕs takes on twice the Fermi potential, i.e., 2ϕB. ϕs and 2ϕB will be
used interchangeably in the remainder of this book. A refined definition
for them is given in Eq. (2.38) after the non-uniform channel doping
effect is introduced.

24
Fig. 2.1 Graphical illustration of the flat-band voltage VFB, oxide voltage Vox and surface
potentials ϕs and Φs in a MOSFET device structure. Open circles denote these voltages
and surface potentials. Grayed circles represent the device terminals. The black dot
designates the location y in the channel.
In the above equations, V(y) is the channel voltage at y with respect to
the source end and ranges from 0 to the source-drain voltage Vds. In order
to simplify the model formulations, Taylor series expansions are
performed for the square-root term of Eq. (2.18). Keeping only the first-
order term yields
cl(m) = −EFG ∙ pq − q€ − r‚ g ∙ q(m)t (2.19)
where
q€ = VTH0 + u ∙ Vv2jk − qr − v2jkY (2.19a)
is the threshold voltage of a long and wide-channel MOS transistor and
VTH0 is the long and wide-channel zero body-bias threshold voltage.
VTH0 is bias independent. It is extracted as a process technology model
parameter
VTH0 = VFB + 2jk + u ∙ v2jk (2.19b)
S
x
G
B
p-Type: NSUB
D
y
Vox
Φs(y)
VFB
ϕs(y)
Vsb
Location y
0

25
Abulk of Eq. (2.19) is called the bulk charge coefficient. It is
r‚ g = 1 +
„
R∙vR he1x
(2.19c)
which is always greater than 1. The second term on the right-hand side of
Eq. (2.19c) is the derivative of the bulk charge qb(y) with respect to the
channel potential V(y) at Vds = 0. The bulk charge effect reduces the
channel inversion charge density as a consequence of the reduced gate
oxide voltage drop nearing the drain end. As will be shown later, a more
accurate Abulk model needs to take into account the channel length, width
and gate-bias dependencies.
2.4.2 Short-Channel Effect: Vth Roll-Off and Drain Bias Effects
At a given drain-source voltage Vds, the threshold voltage of a MOSFET
device Vth decreases with decreasing channel length, a phenomenon
known as Vth roll-off. This is caused by the increased influence of the
drain voltage on the channel potential and charge density when the
channel length becomes shorter. In the case of NMOS transistors, where
the inverted channel carriers are electrons, the energy barrier (for
electrons) will become lower at the source end. As a result, more
electrons can be pulled into the channel inversion layer.
On the other hand, for a given channel length, the source-end energy
barrier becomes lower as Vds increases, which further reduces Vth. This
drain bias effect is known as DIBL (drain-induced barrier lowering). The
BSIM3v3 and BSIM4 Vth roll-off and DIBL models are based upon the
work published in [3] with useful modifications that improve the model
accuracy and SPICE simulation robustness.
Vth is defined as the gate-source voltage Vgs at which the channel
surface potential ϕs is made equal to 2jk. ϕs is determined by process
parameters such as channel doping and gate dielectric thickness, device
geometries and biases. The modeling of roll-off and DIBL effects then
becomes a task of solving Poisson equation for ϕs in the channel
depletion layer. In order to obtain a closed-form equation for compact

26
modeling, a quasi two-dimensional analysis is often utilized to find ϕs
under proper boundary conditions. By applying Gauss’ law, the analyses
start out by relating the net electric field flux entering a finite region of
the depletion layer to the charge densities in that region (often a
rectangular box, known as the Gaussian box as shown in Fig. 2.2). The
relation under the quasi two-dimensional approximations is
‡‚r
ˆ
‰
∙
d()

+ ‡FG
1eVFBe1()
TOXE
= q∙ NDEP ∙ ‹ (2.20)
where Xdep is the depletion layer thickness, εsub and εox are the
permittivities of the substrate and gate dielectric layer, respectively, and
NDEP is the doping concentration of the channel region (whose physical
meaning is to be defined in the next subsection), Es(y) and Vs(y) are the
lateral electric field and surface potential at the interface, respectively.
When the surface is depleted of mobile carriers, the depletion layer is
formed and has a thickness of
‹ = Œ
RHwx∙( e1x)
y∙NDEP∙?A (2.21a)
This expression does not take into account the dependencies on the
channel length and the drain bias. One may approximate this term in Eq.
(2.20) with an average thickness by introducing a fitting parameter η. In
the following, the zero-bias depletion layer thickness will be referred to
frequently. It is given here
‹ ? = Œ
RHwx∙
y∙NDEP∙?A (2.21b)
The first term on the left-hand side of Eq. (2.20) represents the net
field flux entering the box in the lateral direction. The second term is a
familiar expression representing the net field flux entering the box from
the top. Both of the lateral and vertical net fluxes are terminated inside
the box by the needed amount of ionized dopants given on the right-hand
side. At the bottom edge of the depletion layer, the electrical potential is
fixed to the body terminal voltage and the field becomes zero.

27
Fig. 2.2 Gaussian box in the MOSFET depletion layer as part of the quasi 2-D problem
that determines the surface potential profile. The average doping concentration in the
surface area is NDEP and that in the bulk is NSUB. This approximates the retrograde
doping profiles found in modern CMOS process technologies, where the depletion layer
hardly extends into the NSUB region.
From Eq. (2.20), the solution of the surface potential Vs(y) under the
boundary conditions Vs(0) = Vbi and Vs(Leff) = Vbi + Vds is
q
(m) = q − VTH0 + j + Vqr − q + VTH0 − j + q Y ∙
89Ž( %
⁄ )
89ŽV! %
⁄ Y
+ Vqr − q + VTH0 − jY ∙
89ŽpV!eY %
⁄ t
89ŽV! %
⁄ Y
(2.22)
VTH0 is the long-channel zero body-bias threshold voltage. lc is the
characteristic length of MOSFET short-channel effects (SCE). It is
proportional to the square root of the product of the gate oxide thickness
and the depletion layer thickness. The smaller lc is, the less the device is
prone to SCE. Therefore, thinner gate oxides and higher channel dopings
are desired for reducing SCE. In the surface potential model above, Vbi is
the built-in potential of the source-body and drain-body junctions
qr =
gh∙TNOM
y
∙ log “
NSD∙NDEP

C ” (2.23)
where ni is the intrinsic carrier concentration at temperature TNOM.
In order to obtain the threshold voltage reduction caused by the roll-
off (L dependence) and DIBL (Vds and L dependence) effects, one needs
S
x
G
Xdep
B (p-Type): NSUB
D
y
NDEP

28
to find the minimum value of the surface potential along the channel,
which is
qX = q − VTH0 + j + p2 ∙ Vqr − q + VTH0 − jY + q t ∙
89ŽV! R %
⁄ Y
89ŽV! %
⁄ Y
(2.24)
Equating Vsmin and 2ϕB and letting Vth = Vgs yield
q€ = VTH0 − •
1xe
–nŽV! R %
⁄ Ye
+
?.L∙1
–nŽV! R %
⁄ Ye
— ≡ VTH0 − Δq€
(2.25)
The first term in the brackets represents a Vth reduction ∆Vth(roll-off)
attributed to short-channel Vth roll-offs, whereas the second represents
the reduction owing to DIBL, denoted by ∆Vth(DIBL). [Note that in a
coincidence, these powerful terms were also illustrated in Professor
Chih-Tang Sah’s 1991 book Fundamentals of Solid-State Electronics –
Study Guide. See the two energy-band diagrams given in Figs. B1.1 and
B1.2 on pages 386 and 387, respectively, of that book.]
In BSIM4, ∆Vth(roll-off) and ∆Vth(DIBL) are enhanced with the body-
bias dependencies and by incorporating more parameters for ease of
parameter extractions and better accuracy of the channel-length
dependencies. The enhanced version of ∆Vth(roll-off) is
Δq€Vroll-offY = •
0.5∙DVT0
–nŽVDVT1∙! %B
⁄ Ye
— ∙ (qr − j) (2.26)
where DVT0 and DVT1 are the model parameters for the Vth roll-off
dependencies on the channel length. For uniform channel doping, the
body-bias effects on the characteristic length are partially determined by
the depletion layer thickness Xdep. For MOSFETs with non-uniform
channel doping, Xdep is no longer a simple square-root function of (ϕs -
Vbs). The characteristic length is found to have a different body-bias
dependence than the uniform doping case. As the reverse body bias
increases, the characteristic length becomes larger and the device has
stronger short-channel effects. In Eq. (2.26), the characteristic length is
modeled

29
= Œ
Hwx∙TOXE∙ˆ
HIJ
∙ V1 + DVT2 ∙ qr ))Y (2.26a)
where DVT2 is the body-bias coefficient parameter.
The enhanced version of ∆Vth(DIBL) of BSIM4 is
Δq€(DIBL) =
?.L
–nŽVDSUB∙! %f
⁄ Ye
∙ VETA0 + ETAB ∙ qr ))Y ∙ q
(2.27)
where ETA0 is the DIBL coefficient parameter, DSUB models the
length dependencies of DIBL and ETAB is a parameter to model the
body-bias dependence. The characteristic length in ∆Vth(DIBL) is found
to be bias independent
? = Œ
Hwx∙TOXE∙ˆf
HIJ
(2.27a)
It should be noted that when Vds is large, the DIBL-induced Vth
reduction will no longer be the linear function of Vds. It is actually
proportional to
Δq€(DIBL)~V ∙ q + £ ∙ vq Y (2.27b)
This deviation comes from the assumption used in deriving Eq. (2.25)
that when Vds is small, the minimum surface potential Vsmin is located at y
= 0.5Leff [3]. In fact, as Vds increases, Vsmin will move closer to the source
end of the channel and the barrier lowering will be less affected by the
drain bias. The coefficient B above is negative.
In SPICE implementation, BSIM4 uses many useful numerical
techniques, including smoothing and limiting functions, elimination of
potential numerical round-off and divide-by-zero errors, and use of
computationally efficient mathematical functions and floating-point
operations to improve the model evaluation performance and
convergence robustness. Some of these techniques are applied to the Vth
model implementation as well. They will be discussed below and
throughout the book.
For old process technologies where the ratio of the channel length to
the characteristic length is usually large, the cosh(x) term in the above
formulations can be approximated by
1
–nŽ(G)e
≈ 2 ∙ (¥eG
+ 2 ∙ ¥eRG) (2.28)

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