Bu 64843

®
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FEATURES
• Fully Integrated 3.3 Volt, 1553 A/B
Notice 2 Terminal
• Worlds first all 3.3 Volt terminal (No
other power supplies required)
• Transceiver power-down option (64K
RAM Versions Only)
• Smallest 0.88" X 0.88", 0.130" Max
Height CQFP
• 80-pin Ceramic Flat pack or Gull
Wing Package
• Enhanced Mini-ACE Architecture
• Multiple Configurations:
- RT-only, 4K RAM
- BC/RT/Monitor, 4K RAM
- BC/RT/Monitor, 64K RAM
• Supports 1553A/B Notice 2, McAir,
STANAG 3838 Protocols
• MIL-STD-1553, McAir, and MIL-STD-1760
Transceiver Options
• Highly Flexible Host Side Interface
• Compatible With Mini-ACE and ACE
Generations
• Highly Autonomous BC with Built-In
Message Sequence Controller
• Choice of Single, Double, and
Circular RT Buffering Options
• Selective Message Monitor
• Comprehensive Built-In Self-Test
• Choice Of 10, 12, 16, or 20 MHz Clock
Inputs
• Software Libraries and Drivers
available for Windows® 9x/2000/XP,
Windows NT®,VxWorks® and Linux
• Available with Full Military
Temperature Range and Screening
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7234
DESCRIPTION
The Mini-ACE Mark3 is the world's first MIL-STD-1553 terminal pow-ered
entirely by 3.3 volts, thus eliminating the need for a 5 volt power
supply. With a package body of 0.88 inches square and a gull wing
"toe-to-toe" dimension of 1.13 inches max, the Mark3 is the industry's
smallest ceramic gull-lead 1553 terminal, enabling its use in applica-tions
where PC board space is at a premium.
The Mark3 integrates dual transceiver, protocol logic, and either 4K or
64K words of internal RAM. The Mark3's architecture is identical to
that of the Enhanced Mini-ACE, and most features are functionally
and software compatible with the previous Mini-ACE (Plus) and ACE
generations.
A salient feature of the Mark3 is its advanced bus controller architec-ture.
This provides methods to control message scheduling, the
means to minimize host overhead for asynchronous message inser-tion,
facilitate bulk data transfers and double buffering, and support
various message retry and bus switching strategies.
The Mark3's remote terminal architecture provides flexibility in meet-ing
all common MIL-STD-1553 protocols. The choice of RT data
buffering and interrupt options provides robust support for synchro-nous
and asynchronous messaging, while ensuring data sample
consistency and supporting bulk data transfers. The Mark3's monitor
mode provides true message monitoring, and supports filtering on an
RT address/T-R bit/subaddress basis.
The Mark3 incorporates fully autonomous built-in self-tests of its
internal protocol logic and RAM. The Mark3 terminals provide the
same flexibility in host interface configurations as the ACE/Mini-ACE,
along with a reduction in the host processor's worst case holdoff time.
© 2002 Data Device Corporation
BU-64743/64843/64863
Mini-ACE™ MARK3
Make sure the next
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has...
All trademarks are the property of their respective owners.

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2
BU-64743/64843/64863
C-03/03-300
TRANSCEIVER
A
DATA BUS D15-D0
+3.3V
(1:2.7)
+3.3V
(1:2.7)
RTAD4-RTAD0, RTADP, RTADD_LAT
FIGURE 1. MINI-ACE MARK3 BLOCK DIAGRAM
CH. A
TRANSCEIVER
B
CH. B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
RT ADDRESS
SHARED
RAM (1)
ADDRESS BUS
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
A15-A0
DATA
BUFFERS
ADDRESS
BUFFERS
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
MISCELLANEOUS
INCMD/MCRST
CLK_IN, TAG_CLK,
MSTCLR, SSFLAG/EXT_TRG, TX-INH_A, TX-INH_B,
SLEEPIN/UPADDREN
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
TX/RX_A
TX/RX_A
TX/RX_B
TX/RX_B
NOTE 1: See Ordering Information for Available Memory Options.
NOTE 2: Transformer-coupled ratio shown.
+3.3V
(Note 2)
(Note 2)

3
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS
PARAMETER MIN TYP MAX UNITS
www.ddc-web.com
SPECIFICATIONS (CONT.)
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
A
mA
mA
mA
mA
A
mA
mA
3.46
3.46
95
310
525
955
69
110
325
540
970
95
332
583
1.041
69
110
347
598
1.056
40
55
BU-64743/64843/64863
C-03/03-300
3.14
3.14
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances (Note 12)
• +3.3 V Logic
• +3.3 V Transceivers
Current Drain (Total Hybrid) (Note 14)
BU-64743X8/9-XX0,
BU-64843X8/9-XX0 (1553&McAir)
• Idle
• 25% Duty Transmitter Cycle
BU-64863X8/9-XX0 (1553&McAir)
• Idle w/ transceiver SLEEPIN enabled
• Idle w/ transceiver SLEEPIN disabled
BU-64743X8-XX2,
BU-64843X8-XX2 (1760)
• Idle
BU-64863X8-XX2 (1760)
BU-64743X0-XX0,
BU-64843X0-XX0 (Xcvrless)
3.3
3.3
W
W
W
W
W
W
W
W
W
W
W
W
W
0.31
0.67
1.02
1.72
0.23
0.36
0.72
1.07
1.78
0.31
0.74
1.16
2.01
POWER DISSIPATION
(NOTES 14 AND 15)
Total Hybrid
BU-64743X8/9-XX0,
BU-64843X8/9-XX0 (1553&McAir)
• Idle
BU-64863X8/9-XX0 (1553&McAir)
BU-64743X8-XX2,
BU-64843X8-XX2 (1760)
• Idle
V
V
V
V
V
V
μA
μA
μA
μA
μA
V
V
mA
mA
pF
pF
0.7
0.2•Vcc
10
-33
-33
10
10
0.4
-3.4
50
50
2.1
0.8•Vcc
0.4
1.0
-10
-350
-350
-10
-10
2.4
3.4
LOGIC
VIH
All signals except CLK_IN
CLK_IN
VIL
CLK_IN
Schmidt Hysteresis
CLK_IN
IIH, IIL
IIH (Vcc=3.6V, VIN=Vcc)
IIH (Vcc=3.6V, VIN=2.7V)
IIL (Vcc=3.6V, VIN=0.4V)
CLK_IN
IIH
IIL
VOH (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOL (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOL=max)
IOL
IOH
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
Vp-p
Vp-p
Vp-p
mVp-p
mVp
nsec
nsec
9
27
27
10
250
300
300
7
20
22
150
250
6
18
20
-250
100
200
TRANSMITTER
Differential Output Voltage
• Direct Coupled Across 35 Ω,
Measured on Bus
• Transformer Coupled Across
70 Ω, Measured on Bus
(BU-64XX3XX-XX0,
BU-64XX3X8-XX2) (Note 13)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 Ω
Rise/Fall Time
(BU-64XX3X8,
BU-64XX3X9)
kΩ
pF
Vp-p
Vpeak
5
0.860
10
2.5
0.200
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common-Mode Voltage (Note 7)
V
V
V
6.0
6.0
4.5
-0.3
-0.3
-0.3
ABSOLUTE MAXIMUM RATING
Supply Voltage (Note 12)
• Logic (Voltage Input Range)
• Transceivers (not during Transmit)
• Transceivers (during Transmit)

4
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°C/W
°C
°C
°C
°C
°C
°C
in.
(mm)
in.
(mm)
oz
(g)
11
+125
+85
+70
+155
+155
+300
BU-64743/64843/64863
C-03/03-300
9
0.88 X 0.88 X 0.13
(22.3 X 22.3 X 3.3)
1.13
(28.7)
0.6
(17)
-55
-40
0
-55
-65
THERMAL
Thermal Resistance,
Ceramic Flat pack / Gull Wing Package
Junction-to-Case, Hottest Die (θJC) Note 16
Operating Case Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Package Body Size
80-pin Ceramic Flat pack or Gull Wing
Lead Toe-to-Toe Distance
80-pin Gull Wing
Weight
Ceramic Flat pack / Gull Wing
Package
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0.23
0.36
0.79
1.21
2.06
0.132
0.182
0.02
0.09
0.45
0.80
1.51
0.02
0.09
0.54
0.95
1.80
0.13
POWER DISSIPATION (CONT)
(NOTES 14 AND 15)
BU-64863X8-XX2 (1760)
BU-64743X0-XX0, BU-64843X0-XX0
(Xcvrless)
Hottest Die
BU-64XX3X8/9-XX0 (1553&McAir)
(BU-64863 only)
BU-64XX3X8-XX2 (1760)
(BU-64863 only)
BU-64XX3X0-XX0 (Xcvrless)
MHz
MHz
MHz
MHz
%
%
%
%
%
-0.01
-0.10
0.001
0.01
60
0.01
0.10
-0.001
-0.01
40
CLOCK INPUT
• Frequency:
Nominal Values
Default Mode
Option
Option
Option
• Long Term Tolerance
1553A Compliance
1553B Compliance
• Short Term Tolerance, 1 second
1553A Compliance
1553B Compliance
Duty Cycle
16.0
12.0
10.0
20.0
μs
μs
μs
μs
μs
μs
μs
μs
μs
19.5
23.5
51.5
131
7
17.5
21.5
49.5
127
4
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of First
Message for Non-enhanced BC Mode
BC Intermessage Gap (Note 8)
Non-enhanced (Mini-ACE compatible)
BC mode
Enhanced BC mode (Note 9)
BC/RT/MT Response Timeout (Note 10)
• 18.5 nominal
• 22.5 nominal
• 50.5 nominal
• 128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
2.5
9.5
10
to 10.5
18.0
22.5
50.5
129.5
660.5
TABLE 1 Notes:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Receiver Differential Input Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Impedance parameters are specified directly between pins
TX/RX_A(B) and TX/RX_A(B) of the Mini-ACE Mark3 hybrid.
(3) It is assumed that all power and ground inputs to the hybrid are con-nected.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-soidal
input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7) Assumes a common-mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, this may be lengthened (to 65,535 ms - message time) in
increments of 1 μs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-message
gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6 clock
cycles. Since there are 7 internal transfers during SOM and 5 dur-ing
EOM, this could theoretically lengthen the intermessage gap by
up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock, 6.0 μs
with a 12 MHz clock, 4.5 μs with a 16 MHz clock, or 3.6 μs with a
20 MHz clock.

5
TABLE 1 Notes: (Cont’d)
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The Mini-ACE Mark3 includes a 3.3 volt voltage source trans-ceiver
for improved line driving capability, with options for MIL-STD-
1760 and McAir compatibility. Mark3 versions with 64K x 17
RAM offer an additional transceiver power-down (SLEEPIN)
option to further reduce device power consumption. To provide
further flexibility, the Mini-ACE Mark3 may operate with a choice
of 10, 12, 16, or 20 MHz clock inputs.
One of the new salient features of the Mark3 is its Enhanced bus
controller architecture. The Enhanced BC's highly autonomous
message sequence control engine provides a means for offload-ing
the host processor for implementing multiframe message
scheduling, message retry schemes, data double buffering, and
asynchronous message insertion. For the purpose of performing
messaging to the host processor, the Enhanced BC mode
includes a General Purpose Queue, along with user-defined
interrupts.
A second major new feature of the Mark3 is the incorporation of
a fully autonomous built-in self-test. This test provides compre-hensive
testing of the internal protocol logic. A separate test ver-ifies
the operation of the internal RAM. Since the self-tests are
fully autonomous, they eliminate the need for the host to write
and read stimulus and response vectors.
The Mini-ACE Mark3 RT offers the same choices of single, dou-ble,
and circular buffering for individual subaddresses as the
ACE, Mini-ACE (Plus) and Enhanced Mini-ACE. New enhance-ments
to the RT architecture include a global circular buffering
option for multiple (or all) receive subaddresses, a 50% rollover
interrupt for circular buffers, an interrupt status queue for logging
up to 32 interrupt events, and an option to automatically initialize
to RT mode with the Busy bit set. The interrupt status queue and
50% rollover interrupt features are also included as improve-ments
BU-64743/64843/64863
C-03/03-300
to the Mark3's Monitor architecture.
To minimize board space and "glue" logic, the Mini-ACE Mark3
terminals provide the same wide choice of host interface config-urations
as the ACE, Mini-ACE (Plus) and Enhanced Mini-ACE.
This includes support of interfaces to 16-bit or 8-bit processors,
memory or port type interfaces, and multiplexed or non-multi-plexed
address/data buses. In addition, with respect to
ACE/Mini-ACE (Plus), the worst case processor wait time has
been significantly reduced. For example, assuming a 16 MHz
clock, this time has been reduced from 2.8 μs to 632 ns for read
accesses, and to 570 ns for write accesses.
The Mini-ACE Mark3 series terminals operate over the full mili-tary
temperature range of -55 to +125°C and are available
screened to MIL-PRF-38534C. The terminals are ideal for mili-tary
and industrial processor-to-1553 applications powered by
3.3 volts only.
(9) For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-enhanced
BC mode. That is, an addition of 1.0 μs at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) External 10 μF tantalum and 0.1 μF capacitors should be located as
close as possible to +3.3 Vdc input pins 10, 30, 51, and 69.
(13) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub con-nection.
(14) Current drain and power dissipation specs are preliminary and sub-ject
to change.
(15) Power dissipation specifications assume a transformer coupled
configuration with external dissipation (while transmitting) of:
• 0.14 watts for the active isolation transformer,
• 0.08 watts for the active bus coupling transformer,
• 0.45 watts for EACH of the two bus isolation resistors and
• 0.15 watts for EACH of the two bus termination resistors.
(16) θJC is measured to bottom of ceramic case.
INTRODUCTION
The Mini-ACE Mark3 is the world's first MIL-STD-1553 terminal
powered entirely by 3.3 volts, thus eliminating the need for a
5 volt power supply. The BU-64743 RT only, and BU-
64843/64863 BC/RT/MT Mini-ACE Mark3 family of MIL-STD-
1553 terminals comprise a complete integrated interface
between a host processor and a MIL-STD-1553 bus. The Mini-
ACE Mark3 is available in a 0.88 square inch flat pack or gull
wing package with a "toe-to-toe" dimension of 1.13 inches max-imum.
The Mark3 is the industry's smallest ceramic gull-lead
1553 terminal, enabling its use in applications where PC board
space is at a premium. The Mark3's architecture is identical to
that of the Enhanced Mini-ACE, and most features are function-ally
and software compatible with the previous Mini-ACE (Plus)
and ACE generations.
The Mini-ACE Mark3 provides complete multiprotocol support of
MIL-STD-1553A/B/McAir and STANAG 3838. The Mark3 inte-grates
dual transceiver, protocol logic, and either 4K or 64K
words of internal RAM. The BU-64843 and BU-64863 BC/RT/MT
terminals include 64K words of internal RAM, with built-in parity
checking.

6
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TABLE 2. ADDRESS MAPPING
A4 A3 A2 A1 A0
0 0 0 0 0 Interrupt Mask Register #1 (RD/WR)
0 0 0 0 1 Configuration Register #1 (RD/WR)
0 0 0 1 1 Start/Reset Register (WR)
0 0 1 0 1 Time Tag Register (RD/WR)
0 0 1 1 0 Interrupt Status Register #1 (RD)
0 1 0 1 0 RT / Monitor Data Stack Address Register (RD)
0 1 0 1 1 BC Frame Time Remaining Register (RD)
0 1 1 1 0 RT Status Word Register (RD)
0 1 1 1 1 RT BIT Word Register (RD)
1 0 0 0 0 Test Mode Register 0
Test Mode Register 1
1
0
1
0
0
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
1 0 1 1 1 Test Mode Register 7
Configuration Register #7 (RD/WR)
BC Condition Code Register (RD)
BIT Test Status Register (RD)
BU-64743/64843/64863
C-03/03-300
TRANSCEIVERS
The transceivers in the Mini-ACE Mark3 series terminals are fully
monolithic, requiring only a +3.3 volt power input. The transmit-ters
are voltage sources, providing improved line driving capabil-ity
over current sources. This serves to improve performance on
long buses with many taps. Mark3 versions with 64K x 17 RAM
offer an additional transceiver power-down (SLEEPIN) option to
further reduce device power consumption. The transmitters also
offer an option that satisfies the MIL-STD-1760 requirement for a
minimum of 20 volts peak-to-peak, transformer coupled output.
Besides eliminating the demand for an additional power supply,
the use of a +3.3 volt only transceiver requires the use of a step-up,
rather than a step-down, isolation transformer. This provides
the advantage of a higher terminal input impedance than is pos-sible
for a 15V, 12V or 5V transmitter. As a result, there is a
greater margin for the input impedance test, mandated for the
1553 validation test. This allows for longer cable lengths between
a system connector and the isolation transformers of an embed-ded
1553 terminal.
To provide compatibility to McAir specs, the Mini-ACE Mark3 is
available with an option for transmitters with increased rise and
fall times.
The receiver sections of the Mini-ACE Mark3 are fully compliant
with MIL-STD-1553B Notice 2 in terms of front end overvoltage
protection, threshold, common-mode rejection, and word error
rate.
REGISTER AND MEMORY ADDRESSING
The software interface of the Mini-ACE Mark3 to the host proces-sor
consists of 24 internal operational registers for normal oper-ation,
an additional 24 test registers, plus 64K words of shared
memory address space. The Mini-ACE Mark3's 4K X 16 or 64K X
17 internal RAM resides in this address space.
For normal operation, the host processor only needs to access
the lower 32 register address locations (00-1F). The next 32
locations (20-3F) should be reserved, since many of these are
used for factory test.
INTERNAL REGISTERS
The address mapping for the Mini-ACE Mark3 registers is illus-trated
in TABLE 2.
RESERVED
BC General Purpose Queue Pointer /
RT-MT Interrupt Status Queue Pointer Register
(RD/WR)
1
0
0
1
0
0
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1 1 1 1 1
BC General Purpose Flag Register (WR)
Interrupt Mask Register #2 (RD/WR)
1
1
1
0
0
1
1
1
1
1
Interrupt Status Register #2 (RD)
0
1
1
1
1
0
1
1
0
1
1
0
1
0
1
Non-Enhanced BC Frame Time / Enhanced BC
Initial Instruction Pointer / RT Last Command /
MT Trigger Word Register(RD/WR)
0 1 1 0 1
BC Time Remaining to Next Message Register
(RD)
0 1 1 0 0
BC Control Word /
RT Subaddress Control Word Register (RD/WR)
0 0 1 0 0
Non-Enhanced BC/RT Command Stack Pointer /
Enhanced BC Instruction List Pointer Register
(RD)
0 0 0 1 1
REGISTER
DESCRIPTION/ACCESSIBILITY
ADDRESS LINES

7
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BU-64743/64843/64863
C-03/03-300
TABLE 3. INTERRUPT MASK REGISTER #1
(READ/WRITE 00H)
BIT DESCRIPTION
15(MSB) RESERVED
14 RAM PARITY ERROR
13 BC/RT TRANSMITTER TIMEOUT
12 BC/RT COMMAND STACK ROLLOVER
11 MT COMMAND STACK ROLLOVER
10 MT DATA STACK ROLLOVER
9 HANDSHAKE FAIL
8 BC RETRY
7 RT ADDRESS PARITY ERROR
6 TIME TAG ROLLOVER
5 RT CIRCULAR BUFFER ROLLOVER
4 BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
3 BC END OF FRAME
2 FORMAT ERROR
1 BC STATUS SET/RT MODE CODE/MT PATTERN TRIGGER
0(LSB) END OF MESSAGE
TABLE 4. CONFIGURATION REGISTER #1
(READ/WRITE 01H)
BIT
BC FUNCTION (Bits
11-0 Enhanced Mode Only)
RT WITHOUT ALTERNATE
STATUS
RT WITH ALTERNATE
STATUS (Enhanced Only)
MONITOR FUNCTION
(Enhanced mode only bits 12-0)
15 (MSB) RT/BC-MT (logic 0) (logic 1) (logic 1) (logic 0)
14 MT/BC-RT (logic 0) (logic 0) (logic 0) (logic 1)
13 CURRENT AREA B/A CURRENT AREA B/A CURRENT AREA B/A CURRENT AREA B/A
12 MESSAGE STOP-ON-ERROR MESSAGE MONITOR ENABLED
(MMT)
MESSAGE MONITOR
ENABLED
MESSAGE MONITOR ENABLED
11 FRAME STOP-ON-ERROR S10 TRIGGER WORD ENABLED
10 STATUS SET
STOP-ON-MESSAGE
BUSY S09 START-ON-TRIGGER
9 STATUS SET
STOP-ON-FRAME
SERVICE REQUEST S08 STOP-ON-TRIGGER
8 FRAME AUTO-REPEAT SSFLAG S07 NOT USED
7 EXTERNAL TRIGGER ENABLED RTFLAG (Enhanced Mode Only) S06 EXTERNAL TRIGGER ENABLED
6 INTERNAL TRIGGER ENABLED NOT USED S05 NOT USED
5 INTERMESSAGE GAP TIMER
ENABLED
NOT USED S04 NOT USED
4 RETRY ENABLED NOT USED S03 NOT USED
3 DOUBLED/SINGLE RETRY NOT USED S02 NOT USED
2 BC ENABLED (Read Only) NOT USED S01 MONITOR ENABLED(Read Only)
1 BC FRAME IN PROGRESS
(Read Only)
NOT USED S00 MONITOR TRIGGERED
(Read Only)
0 (LSB) BC MESSAGE IN PROGRESS
(Read Only)
RT MESSAGE IN PROGRESS
(Enhanced mode only,Read Only)
RT MESSAGE IN
PROGRESS (Read Only)
MONITOR ACTIVE
(Read Only)
DYNAMIC BUS CONTROL
ACCEPTANCE

8
(READ/WRITE 02H)
BIT DESCRIPTION
15(MSB) ENHANCED INTERRUPTS
14 RAM PARITY ENABLE
13 BUSY LOOKUP TABLE ENABLE
12 RX SA DOUBLE BUFFER ENABLE
11 OVERWRITE INVALID DATA
10 256-WORD BOUNDARY DISABLE
9 TIME TAG RESOLUTION 2
6 CLEAR TIME TAG ON SYNCHRONIZE
5 LOAD TIME TAG ON SYNCHRONIZE
4 INTERRUPT STATUS AUTO CLEAR
3 LEVEL/PULSE INTERRUPT REQUEST
2 CLEAR SERVICE REQUEST
1 ENHANCED RT MEMORY MANAGEMENT
13
RESERVED
11
10
9
CLEAR RT HALT
CLEAR SELF-TEST REGISTER
INITIATE RAM SELF-TEST
TABLE 7. BC/RT COMMAND STACK POINTER REG.
(READ 03H)
BIT DESCRIPTION
15(MSB) COMMAND STACK POINTER 15
• •
• •
• •
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TABLE 8. BC CONTROL WORD REGISTER
(READ/WRITE 04H)
BIT DESCRIPTION
TRANSMIT TIME TAG FOR SYNCHRONIZE MODE COM-15(
TABLE 9. RT SUBADDRESS CONTROL WORD
(READ/WRITE 04H)
BIT DESCRIPTION
15(MSB) RX: DOUBLE BUFFER ENABLE
14 TX: EOM INT
13 TX: CIRC BUF INT
12 TX: MEMORY MANAGEMENT 2 (MM2)
TX: MEMORY MANAGEMENT 1 (MM1)
11
10 TX: MEMORY MANAGEMENT 0 (MM0)
9 RX: EOM INT
8 RX: CIRC BUF INT
7 RX: MEMORY MANAGEMENT 2 (MM2)
4 BCST: EOM INT
3 BCST: CIRC BUF INT
2 BCST:MEMORY MANAGEMENT 2 (MM2)
1 BCST: MEMORY MANAGEMENT 1 (MM1)
TABLE 10. TIME TAG REGISTER
(READ/WRITE 05H)
BIT DESCRIPTION
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0(LSB) SEPARATE BROADCAST DATA
TABLE 6. START/RESET REGISTER
(WRITE 03H)
BIT DESCRIPTION
15(MSB) RESERVED
14 RESERVED
12
RESERVED
8
RESERVED
7 INITIATE PROTOCOL SELF-TEST
6 BC/MT STOP-ON-MESSAGE
5 BC STOP-ON-FRAME
4 TIME TAG TEST CLOCK
3 TIME TAG RESET
2 INTERRUPT RESET
1 BC/MT START
0(LSB) RESET
0(LSB) COMMAND STACK POINTER 0
MSB) MAND
14 MESSAGE ERROR MASK
13 SERVICE REQUEST BIT MASK
12 BUSY BIT MASK
SUBSYSTEM FLAG BIT MASK
11
10 TERMINAL FLAG BIT MASK
9 RESERVED BITS MASK
8 RETRY ENABLED
7 BUS CHANNEL A/B
6 OFF-LINE SELF-TEST
5 MASK BROADCAST BIT
4 EOM INTERRUPT ENABLE
3 1553A/B SELECT
2 MODE CODE FORMAT
1 BROADCAST FORMAT
0(LSB) RT-to-RT FORMAT
0(LSB) BCST: MEMORY MANAGEMENT 0 (MM0)
15(MSB) TIME TAG 15
• •
• •
• •
0(LSB) TIME TAG 0

9
TABLE 11. INTERRUPT STATUS REGISTER #1
(READ 06H)
BIT DESCRIPTION
15(MSB) MASTER INTERRUPT
14 RAM PARITY ERROR
13 TRANSMITTER TIMEOUT
12 BC/RT COMMAND STACK ROLLOVER
MT COMMAND STACK ROLLOVER
11
10 MT DATA STACK ROLLOVER
9 HANDSHAKE FAIL
8 BC RETRY
7 RT ADDRESS PARITY ERROR
6 TIME TAG ROLLOVER
5 RT CIRCULAR BUFFER ROLLOVER
4 BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
3 BC END OF FRAME
2 FORMAT ERROR
BC STATUS SET / RT MODE CODE /
MT PATTERN TRIGGER
1
(READ/WRITE 07H)
BIT DESCRIPTION
15(MSB) ENHANCED MODE ENABLE
14 BC/RT COMMAND STACK SIZE 1
13 BC/RT COMMAND STACK SIZE 0
12 MT COMMAND STACK SIZE 1
MT COMMAND STACK SIZE 0
11
10 MT DATA STACK SIZE 2
7 ILLEGALIZATION DISABLED
6 OVERRIDE MODE T/R ERROR
5 ALTERNATE STATUS WORD ENABLE
4 ILLEGAL RX TRANSFER DISABLE
3 BUSY RX TRANSFER DISABLE
2 RTFAIL / RTFLAG WRAP ENABLE
1 1553A MODE CODES ENABLE
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(READ/WRITE 08H)
BIT DESCRIPTION
15(MSB) EXTERNAL BIT WORD ENABLE
14 INHIBIT BIT WORD IF BUSY
13 MODE COMMAND OVERRIDE BUSY
12 EXPANDED BC CONTROL WORD ENABLE
BROADCAST MASK ENA/XOR
11
10 RETRY IF -A AND M.E.
9 RETRY IF STATUS SET
8 1ST RETRY ALT/SAME BUS
7 2ND RETRY ALT/SAME BUS
6 VALID M.E./NO DATA
5 VALID BUSY/NO DATA
4 MT TAG GAP OPTION
3 LATCH RT ADDRESS WITH CONFIG #5
2 TEST MODE 2
1 TEST MODE 1
0(LSB) TEST MODE 0
(READ/WRITE 09H)
BIT DESCRIPTION
15(MSB) 12 / 16 MHZ CLOCK SELECT
14 SINGLE-ENDED SELECT
13 EXTERNAL TX INHIBIT A
12 EXTERNAL TX INHIBIT B
EXPANDED CROSSING ENABLED
11
10 RESPONSE TIMEOUT SELECT 1
9 RESPONSE TIMEOUT SELECT 0
8 GAP CHECK ENABLED
7 BROADCAST DISABLED
6 RT ADDRESS LATCH/TRANSPARENT
TABLE 15. RT / MONITOR DATA STACK ADDRESS
REGISTER
(READ/WRITE 0AH)
BIT DESCRIPTION
15(MSB) RT / MONITOR DATA STACK ADDRESS 15
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0(LSB) END OF MESSAGE
0(LSB) ENHANCED MODE CODE HANDLING
5 RT ADDRESS 4
4 RT ADDRESS 3
3 RT ADDRESS 2
2 RT ADDRESS 1
1 RT ADDRESS 0
0(LSB) RT ADDRESS PARITY
• •
• •
• •
0(LSB) RT / MONITOR DATA STACK ADDRESS 0

10
TABLE 16. BC FRAME TIME REMAINING REGISTER
(READ/WRITE 0BH)
BIT DESCRIPTION
15(MSB) BC FRAME TIME REMAINING 15
• •
• •
• •
TABLE 17. BC MESSAGE TIME REMAINING
REGISTER
(READ/WRITE 0CH)
BIT DESCRIPTION
15(MSB) BC MESSAGE TIME REMAINING 15
• •
• •
• •
TABLE 18. BC FRAME TIME / RT LAST COMMAND /
MT TRIGGER REGISTER (READ/WRITE 0DH)
BIT DESCRIPTION
15(MSB) BIT 15
• •
• •
• •
BIT DESCRIPTION
15(MSB) LOGIC “0”
14 LOGIC “0”
13 LOGIC “0”
12 LOGIC “0”
LOGIC “0”
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TABLE 20. RT BIT WORD REGISTER
(READ 0FH)
BIT DESCRIPTION
15(MSB) TRANSMITTER TIMEOUT
14 LOOP TEST FAILURE B
13 LOOP TEST FAILURE A
12 HANDSHAKE FAILURE
TRANSMITTER SHUTDOWN B
11
10 TRANSMITTER SHUTDOWN A
9 TERMINAL FLAG INHIBITED
8 BIT TEST FAIL
7 HIGH WORD COUNT
6 LOW WORD COUNT
5 INCORRECT SYNC RECEIVED
4 PARITY / MANCHESTER ERROR RECEIVED
3 RT-to-RT GAP / SYNC / ADDRESS ERROR
2 RT-to-RT NO RESPONSE ERROR
1 RT-to-RT 2ND COMMAND WORD ERROR
(READ/WRITE 18H)
BIT DESCRIPTION
15(MSB) ENHANCED BUS CONTROLLER
14 ENHANCED CPU ACCESS
COMMAND STACK POINTER INCREMENT ON EOM
(RT, MT)
13
12 GLOBAL CIRCULAR BUFFER ENABLE
GLOBAL CIRCULAR BUFFER SIZE 2
11
10 GLOBAL CIRCULAR BUFFER SIZE 1
9 GLOBAL CIRCULAR BUFFER SIZE 0
DISABLE INVALID MESSAGES TO INTERRUPT STATUS
QUEUE
DISABLE VALID MESSAGES TO INTERRUPT STATUS
QUEUE
8
7
6 INTERRUPT STATUS QUEUE ENABLE
5 RT ADDRESS SOURCE
4 ENHANCED MESSAGE MONITOR
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0(LSB) BC FRAME TIME REMAINING 0
Note: resolution = 100 μs per LSB
0(LSB) BC MESSAGE TIME REMAINING 0
Note: resolution = 1 μs per LSB
0(LSB) BIT 0
TABLE 19. RT STATUS WORD REGISTER
(READ/WRITE 0EH)
11
10 MESSAGE ERROR
9 INSTRUMENTATION
8 SERVICE REQUEST
7 RESERVED
6 RESERVED
5 RESERVED
4 BROADCAST COMMAND RECEIVED
3 BUSY
2 SSFLAG
1 DYNAMIC BUS CONTROL ACCEPT
0(LSB) TERMINAL FLAG
0(LSB) COMMAND WORD CONTENTS ERROR
3 RESERVED
2 64-WORD REGISTER SPACE
1 CLOCK SELECT 1
0(LSB) CLOCK SELECT 0

11
(READ/WRITE 19H)
BIT DESCRIPTION
15(MSB) MEMORY MANAGEMENT BASE ADDRESS 15
14 MEMORY MANAGEMENT BASE ADDRESS 14
MEMORY MANAGEMENT BASE ADDRESS 11
11
9 RESERVED
8 RESERVED
7 RESERVED
6 RESERVED
5 RESERVED
4 RT HALT ENABLE
3 1553B RESPONSE TIME
2 ENHANCED TIMETAG SYNCHRONIZE
1 ENHANCED BC WATCHDOG TIMER ENABLED
TABLE 23. BC CONDITION REGISTER
(READ 1BH)
BIT DESCRIPTION
15(MSB) LOGIC “1”
14 RETRY 1
13 RETRY 0
12 BAD MESSAGE
MESSAGE STATUS SET
11
10 GOOD BLOCK TRANSFER
9 FORMAT ERROR
8 NO RESPONSE
7 GENERAL PURPOSE FLAG 7
1 EQUAL FLAG / GENERAL PURPOSE FLAG 1
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TABLE 24. BC GENERAL PURPOSE FLAG REGISTER
(WRITE 1BH)
BIT DESCRIPTION
15(MSB) CLEAR GENERAL PURPOSE FLAG 7
14 CLEAR GENERAL PURPOSE FLAG 6
CLEAR GENERAL PURPOSE FLAG 3
11
7 SET GENERAL PURPOSE FLAG 7
TABLE 25. BIT TEST STATUS FLAG REGISTER
BIT DESCRIPTION
15(MSB) PROTOCOL BUILT-IN TEST COMPLETE
14 PROTOCOL BUILT-IN TEST IN-PROGRESS
13 PROTOCOL BUILT-IN TEST PASSED
12 PROTOCOL BUILT-IN TEST ABORT
PROTOCOL BUILT-IN-TEST COMPLETE / IN-PROGRESS
11
10 LOGIC “0”
9 LOGIC “0”
8 LOGIC “0”
7 RAM BUILT-IN TEST COMPLETE
6 RAM BUILT-IN TEST IN-PROGRESS
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0(LSB) MODE CODE RESET / INCMD SELECT
0(LSB) LESS THAN FLAG / GENERAL PURPOSE FLAG 1
0(LSB) SET GENERAL PURPOSE FLAG 0
5 RAM BUILT-IN TEST IN-PASSED
4 LOGIC “0”
3 LOGIC “0”
2 LOGIC “0”
1 LOGIC “0”
0(LSB) LOGIC “0”
(READ 1CH)
Note: If the Mini-ACE Mark3 is not online in enhanced BC mode (i.e., processing
instructions), the BC condition code register will always return a value of 0000.

12
TABLE 26. INTERRUPT MASK REGISTER #2
BIT DESCRIPTION
15(MSB) NOT USED
14 BC OP CODE PARITY ERROR
RT ILLEGAL COMMAND/MESSAGE MT MESSAGE
RECEIVED
GENERAL PURPOSE QUEUE /
INTERRUPT STATUS QUEUE ROLLOVER
CALL STACK POINTER REGISTER ERROR
13
12
11
10 BC TRAP OP CODE
9 RT COMMAND STACK 50% ROLLOVER
8 RT CIRCULAR BUFFER 50% ROLLOVER
7 MONITOR COMMAND STACK 50% ROLLOVER
6 MONITOR DATA STACK 50% ROLLOVER
5 ENHANCED BC IRQ3
4 ENHANCED BC IRQ2
3 ENHANCED BC IRQ1
2 ENHANCED BC IRQ0
1 BIT TEST COMPLETE
TABLE 27. INTERRUPT STATUS REGISTER #2
(READ 1EH)
BIT DESCRIPTION
15(MSB) MASTER INTERRUPT
14 BC OP CODE PARITY ERROR
RT ILLEGAL COMMAND/MESSAGE MT MESSAGE
RECEIVED
GENERAL PURPOSE QUEUE /
INTERRUPT STATUS QUEUE ROLLOVER
CALL STACK POINTER REGISTER ERROR
13
12
11
10 BC TRAP OP CODE
9 RT COMMAND STACK 50% ROLLOVER
8 RT CIRCULAR BUFFER 50% ROLLOVER
7 MONITOR COMMAND STACK 50% ROLLOVER
6 MONITOR DATA STACK 50% ROLLOVER
5 ENHANCED BC IRQ3
4 ENHANCED BC IRQ2
3 ENHANCED BC IRQ1
2 ENHANCED BC IRQ0
1 BIT TEST COMPLETE
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TABLE 28. BC GENERAL PURPOSE QUEUE
POINTER REGISTER
RT, MT INTERRUPT STATUS QUEUE POINTER
REGISTER
(READ/WRITE1FH)
BIT DESCRIPTION
15(MSB) QUEUE POINTER BASE ADDRESS 15
14 QUEUE POINTER BASE ADDRESS 14
QUEUE POINTER BASE ADDRESS 11
11
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0(LSB) NOT USED
(READ/WRITE 1DH)
0(LSB) INTERRUPT CHAIN BIT
5 QUEUE POINTER ADDRESS 5
0(LSB) QUEUE POINTER ADDRESS 0

NOTE: TABLES 29 TO 35 ARE NOT REGISTERS, BUT THEY ARE WORDS STORED IN RAM.
13
TABLE 29. BC MODE BLOCK STATUS WORD
BIT DESCRIPTION
15(MSB) EOM
14 SOM
13 CHANNEL B/A
12 ERROR FLAG
STATUS SET
11
10 FORMAT ERROR
9 NO RESPONSE TIMEOUT
8 LOOP TEST FAIL
7 MASKED STATUS SET
6 RETRY COUNT 1
5 RETRY COUNT 0
4 GOOD DATA BLOCK TRANSFER
3 WRONG STATUS ADDRESS / NO GAP
2 WORD COUNT ERROR
1 INCORRECT SYNC TYPE
TABLE 30. RT MODE BLOCK STATUS WORD
BIT DESCRIPTION
15(MSB) EOM
14 SOM
13 CHANNEL B/A
12 ERROR FLAG
RT-to-RT FORMAT
11
10 FORMAT ERROR
8 LOOP TEST FAIL
7 DATA STACK ROLLOVER
6 ILLEGAL COMMAND WORD
5 WORD COUNT ERROR
4 INCORRECT DATA SYNC
3 INVALID WORD
1 RT-to-RT 2ND COMMAND ERROR
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BIT DESCRIPTION
15(MSB) REMOTE TERMINAL ADDRESS BIT 4
14 REMOTE TERMINAL ADDRESS BIT 3
REMOTE TERMINAL ADDRESS BIT 0
10 TRANSMIT / RECEIVE
9 SUBADDRESS / MODE BIT 4
4 DATA WORD COUNT / MODE CODE BIT 4
0(LSB) DATA WORD COUNT / MODE CODE BIT 0
TABLE 32. WORD MONITOR IDENTIFICATION
BIT DESCRIPTION
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15(MSB) GAP TIME (MSB)
• •
• •
• •
GAP TIME (LSB)
8
7 WORD FLAG
6 THIS RT
5 BROADCAST
4 ERROR
3 COMMAND / DATA
2 CHANNEL B/A
1 CONTIGUOUS DATA / GAP
0(LSB) MODE_CODE
WORD
11
TABLE 31. 1553 COMMAND WORD
0(LSB) INVALID WORD

14
TABLE 33. MESSAGE MONITOR MODE BLOCK
STATUS WORD
BIT DESCRIPTION
15(MSB) EOM
14 SOM
13 CHANNEL B/A
12 ERROR FLAG
RT-to-RT TRANSFER
11
10 FORMAT ERROR
8 GOOD DATA BLOCK TRANSFER
7 DATA STACK ROLLOVER
6 RESERVED
5 WORD COUNT ERROR
4 INCORRECT SYNC
3 INVALID WORD
1 RT-to-RT 2ND COMMAND ERROR
TABLE 34. RT/MONITOR INTERRUPT STATUS WORD
(FOR INTERRUPT STATUS QUEUE)
DEFINITION FOR MESSAGE
INTERRUPT EVENT
DEFINITION FOR
NON-MESSAGE
INTERRUPT EVENT
BIT
15 TRANSMITTER TIMEOUT NOT USED
14 ILLEGAL COMMAND NOT USED
MONITOR DATA STACK 50%
ROLLOVER
13 NOT USED
MONITOR DATA STACK
ROLLOVER
12 NOT USED
RT CIRCULAR BUFFER
ROLLOVER
11
10 NOT USED
MONITOR COMMAND
(DESCRIPTOR) STACK 50%
ROLLOVER
9 NOT USED
MONITOR COMMAND
(DESCRIPTOR) STACK
ROLLOVER
8 NOT USED
RT COMMAND (DESCRIPTOR)
STACK 50% ROLLOVER
7 NOT USED
5 HANDSHAKE FAIL NOT USED
4 FORMAT ERROR TIME TAG ROLLOVER
1 END-OF-MESSAGE (EOM) RAM PARITY ERROR
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TABLE 35. 1553B STATUS WORD
BIT DESCRIPTION
15(MSB) REMOTE TERMINAL ADDRESS BIT 4
REMOTE TERMINAL ADDRESS BIT 0
11
10 MESSAGE ERROR
9 INSTRUMENTATION
8 SERVICE REQUEST
7 RESERVED
6 RESERVED
5 RESERVED
4 BROADCAST COMMAND RECEIVED
3 BUSY
2 SSFLAG
1 DYNAMIC BUS CONTROL ACCEPTANCE
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
Users Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
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0(LSB) TERMINAL FLAG
NON-TEST REGISTER FUNCTION SUMMARY
A summary of the Mini-ACE Mark3 24 non-test registers follows.
INTERRUPT MASK REGISTERS #1 AND #2
Interrupt Mask Registers #1 and #2 are used to enable and dis-able
interrupt requests for various events and conditions.
CONFIGURATION REGISTERS #1 AND #2
Configuration Registers #1 and #2 are used to select the Mini-
ACE Mark3’s mode of operation, and for software control of RT
Status Word bits, Active Memory Area, BC Stop-On-Error, RT
Memory Management mode selection, and control of the Time
Tag operation.
START/RESET REGISTER
The Start/Reset Register is used for "command" type functions
such as software reset, BC/MT Start, Interrupt reset, Time Tag
Reset, Time Tag Register Test, Initiate protocol self-test, Initiate
RAM self-test, Clear self-test register, and Clear RT Halt. The
Start/Reset Register also includes provisions for stopping the BC
in its auto-repeat mode, either at the end of the current message
or at the end of the current BC frame.
“1” FOR MESSAGE INTERRUPT EVENT
”0” FOR NON-MESSAGE INTERRUPT EVENT
0
SUBADDRESS CONTROL
WORD EOM
PROTOCOL SELF-TEST
COMPLETE
2
RT CIRCULAR BUFFER 50%
ROLLOVER
NOT USED
MODE CODE INTERRUPT
RT ADDRESS PARITY
ERROR
3
RT COMMAND (DESCRIPTOR)
STACK ROLLOVER
6 NOT USED

15
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vidual receive (broadcast) subaddresses, and the alternate (fully
software programmable) RT Status Word. For MT mode, use of
the Enhanced Mode enables the Selective Message Monitor, the
combined RT/Selective Monitor modes, and the monitor trigger-ing
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capability.
RT/MONITOR DATA STACK ADDRESS REGISTER
The RT/Monitor Data Stack Address Register provides a
read/writable indication of the last data word stored for RT or
Monitor modes.
BC FRAME TIME REMAINING REGISTER
The BC Frame Time Remaining Register provides a read-only
indication of the time remaining in the current BC frame. In the
enhanced BC mode, this timer may be used for minor or major
frame control, or as a watchdog timer for the BC message
sequence control processor. The resolution of this register is
100 μs/LSB.
BC TIME REMAINING TO NEXT MESSAGE REGISTER
The BC Time Remaining to Next Message Register provides a
read-only indication of the time remaining before the start of the
next message in a BC frame. In the enhanced BC mode, this
timer may also be used for the BC message sequence control
processor's Delay (DLY) instruction, or for minor or major frame
control. The resolution of this register is 1 μs/LSB.
BC FRAME TIME/ RT LAST COMMAND /MT TRIGGER
WORD REGISTER
In BC mode, this register is used to program the BC frame time,
for use in the frame auto-repeat mode. The resolution of this reg-ister
is 100 μs/LS, with a range up to 6.55 seconds. In RT mode,
this register stores the current (or most previous) 1553
Command Word processed by the Mini-ACE Mark3 RT. In the
Word Monitor mode, this register is used to specify a 16-bit
Trigger (Command) Word. The Trigger Word may be used to
start or stop the monitor, or to generate interrupts.
BC INITIAL INSTRUCTION LIST POINTER REGISTER
The BC Initial Instruction List Pointer Register enables the host
to assign the starting address for the enhanced BC Instruction
List.
RT STATUS WORD REGISTER AND BIT WORD
REGISTERS
The RT Status Word Register and BIT Word Registers provide
read-only indications of the RT Status and BIT Words.
CONFIGURATION REGISTERS #6 AND #7:
Configuration Registers #6 and #7 are used to enable the Mini-
ACE Mark3 features that extend beyond the architecture of the
ACE/Mini-ACE (Plus). These include the Enhanced BC mode;
RT Global Circular Buffer (including buffer size); the RT/MT
Interrupt Status Queue, including valid/invalid message filtering;
enabling a software-assigned RT address; clock frequency
selection; a base address for the "non-data" portion of Mini-ACE
BC/RT COMMAND STACK REGISTER
The BC/RT Command Stack Register allows the host CPU to
determine the pointer location for the current or most recent
message.
BC INSTRUCTION LIST POINTER REGISTER
The BC Instruction List Pointer Register may be read to deter-mine
the current location of the Instruction List Pointer for the
Enhanced BC mode.
BC CONTROL WORD/RT SUBADDRESS CONTROL
WORD REGISTER
In BC mode, the BC Control Word/RT Subaddress Control Word
Register allows host access to the current word or most recent
BC Control Word. The BC Control Word contains bits that select
the active bus and message format, enable off-line self-test,
masking of Status Word bits, enable retries and interrupts, and
specify MIL-STD-1553A or -1553B error handling. In RT mode,
this register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message.
TIME TAG REGISTER
The Time Tag Register maintains the value of a real-time clock.
The resolution of this register is programmable from among 2, 4,
8, 16, 32, and 64 μs/LSB. The Start-of-Message (SOM) and
End-of-Message (EOM) sequences in BC, RT, and Message
Monitor modes cause a write of the current value of the Time Tag
Register to the stack area of the RAM.
INTERRUPT STATUS REGISTERS #1 AND #2
Interrupt Status Registers #1 and #2 allow the host processor to
determine the cause of an interrupt request by means of one or
two read accesses. The interrupt events of the two Interrupt
Status Registers are mapped to correspond to the respective bit
positions in the two Interrupt Mask Registers. Interrupt Status
Register #2 contains an INTERRUPT CHAIN bit, used to indi-cate
an interrupt event from Interrupt Status Register #1.
CONFIGURATION REGISTERS #3, #4, AND #5
Configuration Registers #3, #4, and #5 are used to enable many
of the Mini-ACE Mark3’s advanced features that were imple-mented
by the prior generation products, the ACE and Mini-ACE
(Plus). For BC, RT, and MT modes, use of the Enhanced Mode
enables the various read-only bits in Configuration Register #1.
For BC mode, Enhanced Mode features include the expanded
BC Control Word and BC Block Status Word, additional Stop-On-
Error and Stop-On-Status Set functions, frame auto-repeat, pro-grammable
intermessage gap times, automatic retries, expand-ed
Status Word Masking, and the capability to generate inter-rupts
following the completion of any selected message. For RT
mode, the Enhanced Mode features include the expanded RT
Block Status Word, combined RT/Selective Message Monitor
mode, automatic setting of the TERMINAL FLAG Status Word bit
following a loop test failure; the double buffering scheme for indi-

BC GENERAL PURPOSE QUEUE POINTER
The BC General Purpose Queue Pointer provides a means for
initializing the pointer for the General Purpose Queue, for the
Enhanced BC mode. In addition, this register enables the host to
determine the current location of the General Purpose Queue
pointer, which is incremented internally by the Enhanced BC
message sequence control engine.
RT/MT INTERRUPT STATUS QUEUE POINTER
The RT/MT Interrupt Status Queue Pointer provides a means for
initializing the pointer for the Interrupt Status Queue, for RT, MT,
and RT/MT modes. In addition, this register enables the host to
determine the current location of the Interrupt Status Queue
pointer, which is incremented by the RT/MT message processor.
BUS CONTROLLER (BC) ARCHITECTURE
The BC functionality for the Mini-ACE Mark3 includes two sepa-rate
architectures: (1) the older, non-Enhanced Mode, which pro-vides
complete compatibility with the previous ACE and Mini-
ACE (Plus) generation products; and (2) the newer, Enhanced
BC mode. The Enhanced BC mode offers several new powerful
architectural features. These include the incorporation of a high-ly
autonomous BC message sequence control engine, which
greatly serves to offload the operation of the host CPU.
OP CODE
FIGURE 2. BC MESSAGE SEQUENCE CONTROL
DATA BLOCK
MESSAGE
CONTROL/STATUS
PARAMETER
(POINTER)
BLOCK
BC INSTRUCTION
LIST
BC INSTRUCTION
LIST POINTER REGISTER
BC CONTROL
WORD
COMMAND WORD
(Rx Command for
RT-to-RT transfer)
DATA BLOCK POINTER
TIME-TO-NEXT MESSAGE
TIME TAG WORD
BLOCK STATUS WORD
LOOPBACK WORD
RT STATUS WORD
2nd (Tx) COMMAND WORD
(for RT-to-RT transfer)
2nd RT STATUS WORD
(for RT-to-RT transfer)
INITIALIZE BY REGISTER
0D (RD/WR); READ CURRENT
VALUE VIA REGISTER 03
(RD ONLY)
16
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Mark3 memory; LSB filtering for the Synchronize (with data) time
tag operations; and enabling a watchdog timer for the Enhanced
BC message sequence control engine.
BC CONDITION CODE REGISTER
The BC Condition Code Register is used to enable the host
processor to read the current value of the Enhanced BC
Message Sequence Control Engine's condition flags.
BC GENERAL PURPOSE FLAG REGISTER
The BC General Purpose Flag Register allows the host proces-sor
to be able to set, clear, or toggle any of the Enhanced BC
Message Sequence Control Engine's General Purpose condition
flags.
BIT TEST STATUS REGISTER
The BIT Test Status Register is used to provide read-only access
to the status of the protocol and RAM built-in self-tests (BIT).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Odd
OpCode Field 0 1 0 1 0 Condition Code Field
Parity
17
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The Enhanced BC's message sequence control engine provides
a high degree of flexibility for implementing major and minor
frame scheduling; capabilities for inserting asynchronous mes-sages
in the middle of a frame; to separate 1553 message data
from control/status data for the purpose of implementing double
buffering and performing bulk data transfers; for implementing
message retry schemes, including the capability for automatic
bus channel switchover for failed messages; and for reporting
various conditions to the host processor by means of four user-defined
interrupts and a general purpose queue.
In both the non-Enhanced and Enhanced BC modes, the Mini-
ACE Mark3 BC implements all MIL-STD-1553B message for-mats.
Message format is programmable on a message-by-mes-sage
basis by means of the BC Control Word and the T/R bit of
the Command Word for the respective message. The BC Control
Word allows 1553 message format, 1553A/B type RT, bus chan-nel,
self-test, and Status Word masking to be specified on an
individual message basis. In addition, automatic retries and/or
interrupt requests may be enabled or disabled for individual mes-sages.
The BC performs all error checking required by MIL-STD-
1553B. This includes validation of response time, sync type and
sync encoding, Manchester II encoding, parity, bit count, word
count, Status Word RT Address field, and various RT-to-RT
transfer errors. The Mini-ACE Mark3 BC response timeout value
is programmable with choices of 18, 22, 50, and 130 μs. The
longer response timeout values allow for operation over long
buses and/or the use of repeaters.
In its non-Enhanced Mode, the Mini-ACE Mark3 may be pro-grammed
to process BC frames of up to 512 messages with no
processor intervention. In the Enhanced BC mode, there is no
explicit limit to the number of messages that may be processed
in a frame. In both modes, it is possible to program for either sin-gle
frame or frame auto-repeat operation. In the auto-repeat
mode, the frame repetition rate may be controlled either inter-nally,
using a programmable BC frame timer, or from an external
trigger input.
ENHANCED BC MODE: MESSAGE SEQUENCE CONTROL
One of the major new architectural features of the Mini-ACE
Mark3 series is its advanced capability for BC message
sequence control. The Mini-ACE Mark3 supports highly
autonomous BC operation, which greatly offloads the operation
of the host processor.
The operation of the Mini-ACE Mark3’s message sequence
control engine is illustrated in FIGURE 2. The BC message
sequence control involves an instruction list pointer register;
an instruction list which contains multiple 2-word entries; a
message control/status stack, which contains multiple 8-word
or 10-word descriptors; and data blocks for individual mes-sages.
The initial value of the instruction list pointer register is initialized
by the host processor (via Register 0D), and is incremented by
the BC message sequence processor (host readable via
Register 03). During operation, the message sequence control
processor fetches the operation referenced by the instruction list
pointer register from the instruction list.
Note that the pointer parameter referencing the first word of a
message's control/status block (the BC Control Word) must con-tain
an address value that is modulo 8. Also, note that if the
message is an RT-to-RT transfer, the pointer parameter must
contain an address value that is modulo 16.
OP CODES
The instruction list pointer register references a pair of words in
the BC instruction list: an op code word, followed by a parameter
word. The format of the op code word, which is illustrated in FIG-URE
3, includes a 5-bit op code field and a 5-bit condition code
field. The op code identifies the instruction to be executed by the
BC message sequence controller.
Most of the operations are conditional, with execution dependent
on the contents of the condition code field. Bits 3-0 of the condi-tion
code field identifies a particular condition. Bit 4 of the condi-tion
code field identifies the logic sense ("1" or "0") of the select-ed
condition code on which the conditional execution is depen-dent.
TABLE 36 lists all the op codes, along with their respective
mnemonic, code value, parameter, and description. TABLE 37
defines all the condition codes.
FIGURE 3. BC OP CODE FORMAT

18
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Eight of the condition codes (8 through F) are set or cleared as
the result of the most recent message. The other eight are
defined as "General Purpose" condition codes GP0 through
GP7.There are three mechanisms for programming the values of
the General Purpose Condition Code bits: (1) They may be set,
cleared, or toggled by the host processor, by means of the BC
GENERAL PURPOSE FLAG REGISTER; (2) they may be set,
cleared, or toggled by the BC message sequence control
processor, by means of the GP Flag Bits (FLG) instruction; and
(3) GP0 and GP1 only (but none of the others) may be set or
cleared by means of the BC message sequence control proces-sor's
Compare Frame Timer (CFT) or Compare Message Timer
(CMT) instructions.
The host processor also has read-only access to the BC condi-tion
codes by means of the BC CONDITION CODE REGISTER.
Note that four (4) instructions are unconditional. These are
Compare to Frame Timer (CFT), Compare to Message Timer
(CMT), GP Flag Bits (FLG), and Execute and Flip (XQF). For
these instructions, the Condition Code Field is "don't care". That
is, these instructions are always executed, regardless of the
result of the condition code test.
All of the other instructions are conditional. That is, they will only be
executed if the condition code specified by the condition code field
in the op code word tests true. If the condition code field tests false,
the instruction list pointer will skip down to the next instruction.
As shown in TABLE 36, many of the operations include a single-word
parameter. For an XEQ (execute message) operation, the
parameter is a pointer to the start of the message’s Control /
Status block. For other operations, the parameter may be an
address, a time value, an interrupt pattern, a mechanism to set
or clear general purpose flag bits, or an immediate value. For
several op codes, the parameter is "don't care" (not used).
As described above, some of the op codes will cause the mes-sage
sequence control processor to execute messages. In this
case, the parameter references the first word of a message
Control/Status block. With the exception of RT-to-RT transfer
messages, all message status/control blocks are eight words
long: a block control word, time-to-next-message parameter,
data block pointer, command word, status word, loopback word,
block status word, and time tag word.
In the case of an RT-to-RT transfer message, the size of the
message control/status block increases to 16 words. However, in
this case, the last six words are not used; the ninth and tenth
words are for the second command word and second status
word.
The third word in the message control/status block is a pointer
that references the first word of the message's data word block.
Note that the data word block stores only data words, which are
to be either transmitted or received by the BC. By segregating
data words from command words, status words, and other con-trol
and "housekeeping" functions, this architecture enables the
use of convenient, usable data structures, such as circular
buffers and double buffers.
Other operations support program flow control; i.e., jump and call
capability. The call capability includes maintenance of a call
stack which supports a maximum of four (4) entries; there is also
a return instruction. In the case of a call stack overrun or under-run,
the BC will issue a CALL STACK POINTER REGISTER
ERROR interrupt, if enabled.
Other op codes may be used to delay for a specified time; start a
new BC frame; wait for an external trigger to start a new frame;
perform comparisons based on frame time and time-to-next mes-sage;
load the time tag or frame time registers; halt; and issue host
interrupts. In the case of host interrupts, the message control
processor passes a 4-bit user-defined interrupt vector to the host,
by means of the Mini-ACE Mark3's Interrupt Status Register.
The purpose of the FLG instruction is to enable the message
sequence controller to set, clear, or toggle the value(s) of any or
all of the eight general purpose condition flags.
The op code parity bit encompasses all sixteen bits of the op
code word. This bit must be programmed for odd parity. If the
message sequence control processor fetches an undefined op
code word, an op code word with even parity, or bits 9-5 of an op
code word do not have a binary pattern of 01010, the message
sequence control processor will immediately halt the BC's oper-ation.
In addition, if enabled, a BC TRAP OP CODE interrupt will
be issued. Also, if enabled, a parity error will result in an OP
CODE PARITY ERROR interrupt. TABLE 37 describes the
Condition Codes.

Conditional
(See Note)
Conditional
Conditional
Conditional
Conditional
Conditional
19
Execute
Message
XEQ
Jump
Subroutine
Call
Subroutine
Return
Halt
JMP
CAL
RTN
HLT
Delay
DLY
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Executes the message at the specified Message Control/Status
Block Address if the condition flag tests TRUE, otherwise con-tinue
execution at the next OpCode in the instruction list.
Jump to the OpCode specified in the Instruction List if the con-dition
flag tests TRUE, otherwise continue execution at the next
OpCode in the instruction list.
Jump to the OpCode specified by the Instruction List Address
and push the Address of the Next OpCode on the Call Stack if
the condition flag tests TRUE, otherwise continue execution at
the next OpCode in the instruction list. Note that the maximum
depth of the subroutine call stack is four.
Return to the OpCode popped off the Call Stack if the condition
flag tests TRUE, otherwise continue execution at the next
Stop execution of the Message Sequence Control Program until
a new BC Start is issued by the host if the condition flag tests
TRUE, otherwise continue execution at the next OpCode in the
instruction list.
Delay the time specified by the Time parameter before execut-ing
the next OpCode if the condition flag tests TRUE, otherwise
continue execution at the next OpCode without delay. The delay
generated will use the Time to Next Message Timer.
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TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL
INSTRUCTION MNEMONIC
OP CODE
(HEX)
PARAMETER
CONDITIONAL
OR
UNCONDITIONAL
DESCRIPTION
Interrupt
Request
IRQ
0001
0002
0003
0004
0006
Message Control /
Status Block
Address
Instruction List
Address
Instruction List
Address
Not Used
(Don’t Care)
Interrupt
Bit Pattern
in 4 LS bits
Conditional
Generate an interrupt if the condition flag tests TRUE, otherwise
continue execution at the next OpCode in the instruction list.
The passed parameter (Interrupt Bit Pattern) specifies which of
the ENHANCED BC IRQ bit(s) (bits 5-2) will be set in Interrupt
Status Register #2. Only the four LSBs of the passed parameter
are used. A parameter where the four LSBs are logic "0" will
not generate an interrupt.
Compare to
Frame Timer
CFT
0007
0008
000A
Not Used
(Don’t Care)
Delay Time Value
(Resolution = 1μS
/ LSB)
Delay Time Value
(Resolution
= 100μS / LSB)
Unconditional
Compare Time Value to Frame Time Counter. The LT/GP0 and
EQ/GP1 flag bits are set or cleared based on the results of the
compare. If the value of the CFT's parameter is less than the
value of the frame time counter, then the LT/GP0 and NE/GP1
flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will
be cleared. If the value of the CFT's parameter is equal to the
value of the frame time counter, then the GT-EQ/GP0 and
EQ/GP1 flags will be set, while the LT/GP0 and NE/GP1 flags
will be cleared. If the value of the CFT's parameter is greater
than the current value of the frame time counter, then the GT-EQ/
GP0 and NE/GP1 flags will be set, while the LT/GP0 and
EQ/GP1 flags will be cleared.
Compare to
Message
Timer
CMT
000B
Delay Time Value
(Resolution
= 1μS / LSB)
Unconditional
Compare Time Value to Message Time Counter. The LT/GP0 and
EQ/GP1 flag bits are set or cleared based on the results of the
compare. If the value of the CMT's parameter is less than the value
of the message time counter, then the LT/GP0 and NE/GP1 flags
will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared.
If the value of the CMT's parameter is equal to the value of the mes-sage
time counter, then the GT-EQ/GP0 and EQ/GP1 flags will be
set, while the LT/GP0 and NE/GP1 flags will be cleared. If the value
of the CMT's parameter is greater than the current value of the
message time counter, then the GT-EQ/GP0 and NE/GP1 flags will
be set, while the LT/GP0 and EQ/GP1 flags will be cleared.
Wait Until
Frame Timer
= 0
WFT
0009
Not Used
(Don’t Care)
Conditional
Wait until Frame Time counter is equal to Zero before continu-ing
execution of the Message Sequence Control Program if the
condition flag tests TRUE, otherwise continue execution at the
next OpCode without delay.
NOTE: While the XEQ (Execute Message) instruction is conditional, not all condition codes may be used to enable its use. The ALWAYS and NEVER condition codes
may be used. The eight general purpose flag bits, GP0 through GP7, may also be used. However, if GP0 through GP7 are used, it is imperative that the host processor
not modify the value of the specific general purpose flag bit that enabled a particular message while that message is being processed. Similarly, the LT, GT-EQ, EQ, and
NE flags, which the BC only updates by means of the CFT and CMT instructions, may also be used. However, these two flags are dual use. Therefore, if these are used, it
is imperative that the host processor not modify the value of the specific flag (GP0 or GP1) that enabled a particular message while that message is being processed. The
NORESP, FMT ERR, GD BLK XFER, MASKED STATUS SET, BAD MESSAGE, RETRY0, and RETRY1 condition codes are not available for use with the XEQ instruction
and should not be used to enable its execution.

TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL (CONT.)
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Push Block
Status Word
PBS 0011 Not Used
(Don't Care)
Conditional Push the Block Status Word for the most recent message on
the General Purpose Queue if the condition flag tests TRUE,
otherwise continue execution at the next OpCode in the
instruction list.
INSTRUCTION MNEMONIC
OP CODE
(HEX)
PARAMETER DESCRIPTION
Load Time Tag
Counter
LTT 000D Time Value.
Resolution
(μs/LSB) is
defined by bits 9,
8, and 7 of
Configuration
Register #2.
Conditional Load Time Tag Counter with Time Value if the condition flag
tests TRUE, otherwise continue execution at the next
Load Frame
Timer
LFT 000E Time Value
(resolution =
100 μs/LSB)
Conditional Load Frame Timer Register with the Time Value parameter
if the condition flag tests TRUE, otherwise continue execu-tion
at the next OpCode in the instruction list.
Start Frame
Timer
SFT 000F Not Used
(Don't Care)
Conditional Start Frame Time Counter with Time Value in Time Frame
register if the condition flag tests TRUE, otherwise continue
execution at the next OpCode in the instruction list.
Push Time Tag
Register
PTT 0010 Not Used
(Don't Care)
Conditional Push the value of the Time Tag Register on the General
Purpose Queue if the condition flag tests TRUE, otherwise
continue execution at the next OpCode in the instruction list.
Push Immediate
Value
PSI 0012 Immediate Value Conditional Push Immediate data on the General Purpose Queue if the
condition flag tests TRUE, otherwise continue execution at
the next OpCode in the instruction list.
Push Indirect PSM 0013 Memory
Address
Conditional Push the data stored at the specified memory location on
the General Purpose Queue if the condition flag tests TRUE,
otherwise continue execution at the next OpCode in the
instruction list.
Wait for
External
Trigger
WTG 0014 Not Used
(Don't Care)
Conditional Wait for a logic "0"-to-logic "1" transition on the EXT_TRIG
input signal before proceeding to the next OpCode in the
instruction list if the condition flag tests TRUE, otherwise
continue execution at the next OpCode without delay.
Execute and
Flip
XQF 0015 Message
Control /
Status Block
Address
Unconditional Execute (unconditionally) the message referenced by the
Message Control/Status Block Address. Following the pro-cessing
of this message, if the condition flag tests TRUE,
the BC will toggle bit 4 in the Message Control/Status Block
Address, and store the new Message Block Address as the
updated value of the parameter following the XQF instruc-tion
code. As a result, the next time that this line in the
instruction list is executed, the Message Control/Status
Block at the updated address (old address XOR 0010h),
rather than the old address, will be processed. If the condi-tion
flag tests FALSE, the value of the Message
Control/Status Block Address parameter will not change.
CONDITIONAL
OR
UNCONDITIONAL
GP Flag Bits FLG 000C Used to set,
clear, or toggle
GP
(General
Purpose)
Flag bits
(See descrip-tion)
Unconditional Used to set, toggle, or clear any or all of the eight general
purpose flags. The table below illustrates the use of the GP
Flag Bits instruction for the case of GP0 (General Purpose
Flag 0). Bits 1 and 9 of the parameter byte affect flag GP1,
bits 2 and 10 effect GP2, etc., according to the following
rules:
Bit 8
0
0
1
0
1
0
1 1
No Change
Set Flag
Clear Flag
Toggle Flag

9 FMT ERR FMT ERR FMT ERR indicates that the received portion of the most recent message contained one or more viola-tions
of the 1553 message validation criteria (sync, encoding, parity, bit count, word count, etc.), or the
RT's status word received from a responding RT contained an incorrect RT address field.
C BAD MESSAGE indicates either a format error, loop test fail, or no response error for the most recent
message. Note that a "Status Set" condition has no effect on the "BAD MESSAGE/GOOD MESSAGE"
condition code.
21
NAME
(BIT 4 = 0)
1
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TABLE 37. BC CONDITION CODES
BIT
CODE
LT/GP0
EQ/GP1
RETRY0
RETRY1
GP2
GP3
GP4
GP5
GP6
GP7
RESP
RETRY0
RETRY1
D
E
GP2
GP3
GP4
GP5
GP6
GP7
NORESP
GD BLK
XFER
FUNCTIONAL DESCRIPTION
These two bits reflect the retry status of the most recent message. The number of times that the mes-sage
was retried is delineated by these two bits as shown below:
RETRY COUNT 1 RETRY COUNT 0 Number of
(bit 14) (bit 13) Message Retries
0 0 0
0 1 1
1 0 N/A
1 1 2
INVERSE
(BIT 4 = 1)
GT-EQ/
GP0
NE/GP1
0
ALWAYS
Less than or GP0 flag. This bit is set or cleared based on the results of the compare. If the value of the
CMT's parameter is less than the value of the message time counter, then the LT/GP0 and NE/GP1
flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared. If the value of the CMT's
parameter is equal to the value of the message time counter, then the GT-EQ/GP0 and EQ/GP1 flags
will be set, while the LT/GP0 and NE/GP1 flags will be cleared. If the value of the CMT's parameter is
greater than the current value of the message time counter, then the GT-EQ/GP0 and NE/GP1 flags will
be set , while the LT/GP0 and EQ/GP1 flags will be cleared. Also, General Purpose Flag 1 may be also
be set or cleared by a FLG operation.
F NEVER
Equal Flag. This bit is set or cleared after CFT or CMT operation. If the value of the CMT's parameter is
equal to the value of the message time counter, then the EQ/GP1 flag will be set and the NE/GP1 bit
will be cleared. If the value of the CMT's parameter is not equal to the value of the message time
counter, then the NE/GP1 flag will be set and the EQ/GP1bit will be cleared. Also, General Purpose
Flag 1 may be also be set or cleared by a FLG operation.
GD BLK
XFER
BAD
MESSAGE
GOOD
MESSAGE
The ALWAYS flag should be set (bit 4 = 0) to designate an instruction as unconditional. The NEVER bit
(bit 4 = 1) can be used to implement a NOP or "skip" instruction.
MASKED
STATUS
BIT
MASKED
STATUS
BIT
B
General Purpose Flags may be set, cleared, or toggled by a FLG operation. The host processor can
set, clear, or toggle these flags in the same way as the FLG instruction by means of the BC GENERAL
PURPOSE FLAG REGISTER.
Indicates that one or both of the following conditions have occurred for the most recent message: (1) If
one (or more) of the Status Mask bits (14 through 9) in the BC Control Word is logic "0" and the corre-sponding
bit(s) is (are) set (logic "1") in the received RT Status Word. In the case of the RESERVED
BITS MASK (bit 9) set to logic "0," any or all of the 3 Reserved Status Word bits being set will result in
a MASKED STATUS SET condition; and/or (2) If BROADCAST MASK ENABLED/XOR (bit 11 of
Configuration Register #4) is logic "1" and the MASK BROADCAST bit of the message's BC Control
Word is logic "0" and the BROADCAST COMMAND RECEIVED bit in the received RT Status Word is
logic "1."
2
3
4
5
6
7
NORESP indicates that an RT has either not responded or has responded later than the BC No
Response Timeout time. The Mini-ACE Mark3's No Response Timeout Time is defined per
MIL-STD-1553B as the time from the mid-bit crossing of the parity bit of the last word transmitted by
the BC to the mid-sync crossing of the RT Status Word. The value of the No Response Timeout value
is programmable from among the nominal values 18.5, 22.5, 50.5, and 130 μs (±1 μs) by means of bits
10 and 9 of Configuration Register #5.
A For the most recent message, GD BLK XFER will be set to logic "1" following completion of a valid
(error-free) RT-to-BC transfer, RT-to-RT transfer, or transmit mode code with data message. This bit is
set to logic "0" following an invalid message. GOOD DATA BLOCK TRANSFER is always logic "0" fol-lowing
a BC-to-RT transfer, a mode code with data, or a mode code without data. The Loop Test has
no effect on GOOD DATA BLOCK TRANSFER. GOOD DATA BLOCK TRANSFER may be used to
determine if the transmitting portion of an RT-to-RT transfer was error free.

(part of) BC INSTRUCTION LIST MESSAGE
CONTROL/STATUS
MESSAGE
CONTROL/STATUS
BLOCK 1
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BC MESSAGE SEQUENCE CONTROL
The Mini-ACE Mark3 BC message sequence control capability
enables a high degree of offloading of the host processor. This
includes using the various timing functions to enable
autonomous structuring of major and minor frames. In addition,
by implementing conditional jumps and subroutine calls, the
message sequence control processor greatly simplifies the
insertion of asynchronous, or "out-of-band" messages.
EXECUTE AND FLIP OPERATION
The Mini-ACE Mark3 BC's XQF, or "Execute and Flip" operation,
provides some unique capabilities. Following execution of this
unconditional instruction, if the condition code tests TRUE, the
BC will modify the value of the current XQF instruction's pointer
parameter by toggling bit 4 of the pointer. That is, if the selected
condition flag tests true, the value of the parameter will be
updated to the value = old address XOR 0010h. As a result, the
next time that this line in the instruction list is executed, the
Message Control/Status Block at the updated address (old
address XOR 0010h) will be processed, rather than the one at
the old address. The operation of the XQF instruction is illustrat-ed
in FIGURE 4.
There are multiple ways of utilizing the "execute and flip" instruc-tion.
One is to facilitate the implementation of a double buffering
data scheme for individual messages. This allows the message
sequence control processor to "ping-pong" between a pair of
data buffers for a particular message. By doing so, the host
processor can access one of the two Data Word blocks, while the
BC reads or writes the alternate Data Word block.
A second application of the "execute and flip" capability is in con-junction
with message retries. This allows the BC to not only
switch buses when retrying a failed message, but to automati-cally
switch buses permanently for all future times that the same
message is to be processed. This not only provides a high
degree of autonomy from the host CPU, but saves BC band-width,
by eliminating the need for future attempts to process
messages on an RT's failed channel.
XQF
BLOCK 0
POINTER XX00h
DATA BLOCK 0
XX00h
DATA BLOCK 1
POINTER
POINTER
FIGURE 4. EXECUTE and FLIP (XQF) OPERATION

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GENERAL PURPOSE QUEUE
The Mini-ACE Mark3 BC allows for the creation of a general pur-pose
queue. This data structure provides a means for the mes-sage
sequence processor to convey information to the BC host.
The BC op code repertoire provides mechanisms to push vari-ous
items on this queue. These include the contents of the Time
Tag Register, the Block Status Word for the most recent mes-sage,
an immediate data value, or the contents of a specified
memory address.
FIGURE 5 illustrates the operation of the BC General Purpose
Queue. Note that the BC General Purpose Queue Pointer
Register will always point to the next address location (modulo
64); that is, the location following the last location written by the
BC message sequence control engine.
If enabled, a BC GENERAL PURPOSE QUEUE ROLLOVER
interrupt will be issued when the value of the queue pointer
address rolls over at a 64-word boundary. The rollover will always
occur at a modulo 64 address.
BC GENERAL
PURPOSE QUEUE
(64 Locations)
LAST LOCATION
BC GENERAL
PURPOSE QUEUE
POINTER
REGISTER
NEXT LOCATION
FIGURE 5. BC GENERAL PURPOSE QUEUE

24
TABLE 38. TYPICAL RT MEMORY MAP (SHOWN
FOR 4K RAM)
DESCRIPTION
ADDRESS
(HEX)
0000-00FF Stack A
Stack Pointer A
Global Circular Buffer A Pointer
0100
0101
0102-0103 RESERVED
Stack Pointer B
Global Circular Buffer B Pointer
RESERVED
0104
0105
0106-0107
0108-010F Mode Code Selective Interrupt Table
0110-013F Mode Code Data
0140-01BF Lookup Table A
01C0-023F Lookup Table B
0240-0247 Busy Bit Lookup Table
0248-025F (not used)
0260-027F Data Block 0
0280-02FF Data Block 1-4
0300-03FF Command Illegalizing Table
• •
• •
• •
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AREA A AREA B DESCRIPTION COMMENT
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REMOTE TERMINAL (RT) ARCHITECTURE
The Mini-ACE Mark3's RT architecture builds upon that of the
ACE and Mini-ACE. The Mini-ACE Mark3 provides multiprotocol
support, with full compliance to all of the commonly used data bus
standards, including MIL-STD-1553A, MIL-STD-1553B Notice 2,
STANAG 3838, General Dynamics 16PP303, and McAirA3818,
A5232, and A5690. For the Mini-ACE Mark3 RT mode, there is
programmable flexibility enabling the RT to be configured to fulfill
any set of system requirements. This includes the capability to
meet the MIL-STD-1553A response time requirement of 2 to 5 μs,
and multiple options for mode code subaddresses, mode codes,
RT status word, and RT BIT word.
The Mini-ACE Mark3 RT protocol design implements all of the
MIL-STD-1553B message formats and dual redundant mode
codes. The design has passed validation testing for MIL-STD-
1553B compliance. The Mini-ACE Mark3 RT performs compre-hensive
error checking including word and format validation, and
checks for various RT-to-RT transfer errors. One of the main fea-tures
of the Mini-ACE Mark3 RT is its choice of memory man-agement
options. These include single buffering by subaddress,
double buffering for individual receive subaddresses, circular
buffering by individual subaddresses, and global circular buffering
for multiple (or all) subaddresses.
Other features of the Mini-ACE Mark3 RT include a set of inter-rupt
conditions, a flexible status queue with filtering based on
valid and/or invalid messages, flexible command illegalization,
programmable busy by subaddress, multiple options on time tag-ging,
and an "auto-boot" feature which allows the RT to initialize
as an online RT with the busy bit set following power turn-on.
RT MEMORY ORGANIZATION
TABLE 38 illustrates a typical memory map for an Mini-ACE
Mark3 RT with 4K RAM. The two Stack Pointers reside in fixed
locations in the shared RAM address space: address 0100 (hex)
for the Area A Stack Pointer and address 0104 for the Area B
Stack Pointer. In addition to the Stack Pointer, there are several
other areas of the shared RAM address space that are designat-ed
as fixed locations (all shown in bold). These are for the Area
A and Area B lookup tables, the illegalization lookup table, the
busy lookup table, and the mode code data tables.
The RT lookup tables (reference TABLE 39) provide a mecha-nism
for allocating data blocks for individual transmit, receive, or
broadcast subaddresses. The RT lookup tables include subad-dress
control words as well as the individual data block pointers.
If command illegalization is used, address range 0300-03FF is
used for command illegalizing. The descriptor stack RAM area, as
well as the individual data blocks, may be located in any of the
non-fixed areas in the shared RAM address space.
Note that in TABLE 38, there is no area allocated for "Stack B".
This is shown for purpose of simplicity of illustration. Also, note
that in TABLE 38, the allocated area for the RT command stack is
256 words. However, larger stack sizes are possible. That is, the
RT command stack size may be programmed for 256 words (64
messages), 512, 1024, or 2048 words (512 messages) by means
of bits 14 and 13 of Configuration Register 3.
0FE0-0FFF Data Block 100
Subaddress
Control Word
Lookup Table
(Optional)
SACW SA0
•
•
•
SACW SA31
0220
•
•
•
023F
01A0
•
•
•
01BF
Broadcast
Lookup Pointer
Table
(Optional)
Bcst SA0
•
•
•
Bcst SA31
0200
•
•
•
021F
0180
•
•
•
019F
Transmit
Lookup Pointer
Table
Tx SA0
•
•
•
Tx SA31
01E0
•
•
•
01FF
0160
•
•
•
017F
Receive
(/Broadcast)
Lookup Pointer
Table
Rx(/Bcst) SA0
•
•
•
Rx(/Bcst) SA31
01C0
•
•
•
01DF
0140
•
•
•
015F
TABLE 39. RT LOOK-UP TABLES

TABLE 40. RT SUBADDRESS CONTROL WORD - MEMORY MANAGEMENT OPTIONS
SUBADDRESS CONTROL WORD BITS
0
0
0
0
0 0 0 1 128-Word
0 0 1 0 256-Word
0 0 1 1 512-Word
0 1 0 0 1024-Word
0 1 1 0 4096-Word
25
0
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Single Message
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RT MEMORY MANAGEMENT
The Mini-ACE Mark3 provides a variety of RT memory manage-ment
capabilities. As with the ACE and Mini-ACE, the choice of
memory management scheme is fully programmable on a trans-mit/
receive/broadcast subaddress basis.
In compliance with MIL-STD-1553B Notice 2, received data from
broadcast messages may be optionally separated from non-broadcast
received data. For each transmit, receive or broadcast
subaddress, either a single-message data block, a double
buffered configuration (two alternating Data Word blocks), or a
variable-sized (128 to 8192 words) subaddress circular buffer
may be allocated for data storage. The memory management
scheme for individual subaddresses is designated by means of
the subaddress control word (reference TABLE 40).
For received data, there is also a global circular buffer mode. In
this configuration, the data words received from multiple (or all)
subaddresses are stored in a common circular buffer structure.
Like the subaddress circular buffer, the size of the global circular
buffer is programmable, with a range of 128 to 8192 data words.
The double buffering feature provides a means for the host
processor to easily access the most recent, complete received
block of valid Data Words for any given subaddress. In addition
to helping ensure data sample consistency, the circular buffer
options provide a means for greatly reducing host processor
overhead for multi-message bulk data transfer applications.
End-of-message interrupts may be enabled either globally (fol-lowing
all messages), following error messages, on a
transmit/receive/broadcast subaddress or mode code basis, or
when a circular buffer reaches its midpoint (50% boundary) or
lower (100%) boundary. A pair of interrupt status registers allow
the host processor to determine the cause of all interrupts by
means of a single read operation.
Subaddress -
specific circular buffer
of specified size.
8192-Word
1
(for receive and / or broadcast subaddresses only)
Global Circular Buffer: The buffer size is specified by
Configuration Register #6, bits 11-9. The pointer to the global
circular buffer is stored at address 0101 (for Area A) or address
0105 (for Area B)
1
1
1
1
1
1
For Receive or Broadcast:
Double Buffered
For Transmit: Single Message
0
0
1
0
MM0
MEMORY MANAGEMENT SUBADDRESS
MM1 BUFFER SCHEME DESCRIPTION
DOUBLE-BUFFERED OR
GLOBAL CIRCULAR BUFFER
(bit 15) MM2
0 1 0 1 2048-Word

26
CONFIGURATION
REGISTER
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SINGLE BUFFERED MODE
The operation of the single buffered RT mode is illustrated in
FIGURE 6. In the single buffered mode, the respective lookup
table entry must be written by the host processor. Received data
words are written to, or transmitted data words are read from the
data word block with starting address referenced by the lookup
table pointer. In the single buffered mode, the current lookup
table pointer is not updated by the Mini-ACE Mark3 memory
management logic. Therefore, if a subsequent message is
received for the same subaddress, the same Data Word block
will be overwritten or overread.
SUBADDRESS DOUBLE BUFFERING MODE
The Mini-ACE Mark3 provides a double buffering mechanism for
received data, that may be selected on an individual subaddress
basis for any or all receive (and/or broadcast) subaddresses. This
is illustrated in FIGURE 7. It should be noted that the Subaddress
Double Buffering mode is applicable for receive data only, not for
transmit data. Double buffering of transmit messages may be
easily implemented by software techniques.
The purpose of the subaddress double buffering mode is to pro-vide
data sample consistency to the host processor. This is
accomplished by allocating two 32-word data word blocks for each
individual receive (and/or broadcast receive) subaddress. At any
given time, one of the blocks will be designated as the "active"
1553 block while the other will be considered as "inactive". The
data words for the next receive command to that subaddress will
be stored in the active block. Following receipt of a valid message,
the Mini-ACE Mark3 will automatically switch the active and inac-tive
blocks for that subaddress. As a result, the latest, valid, com-plete
data block is always accessible to the host processor.
CIRCULAR BUFFER MODE
The operation of the Mini-ACE Mark3's circular buffer RT mem-ory
management mode is illustrated in FIGURE 8. As in the sin-gle
buffered and double buffered modes, the individual lookup
table entries are initially loaded by the host processor. At the
start of each message, the lookup table entry is stored in the
third position of the respective message block descriptor in the
descriptor stack area of RAM. Receive or transmit data words
are transferred to (from) the circular buffer, starting at the loca-tion
referenced by the lookup table pointer.
In general, the location after the last data word written or read
(modulo the circular buffer size) during the message is written to
the respective lookup table location during the end-of-message
sequence. By so doing, data for the next message for the respec-tive
transmit, receive(/broadcast), or broadcast subaddress will
be accessed from the next lower contiguous block of locations in
the circular buffer.
For the case of a receive (or broadcast receive) message with a
data word error, there is an option such that the lookup table
pointer will only be updated following receipt of a valid message.
That is, the pointer will not be updated following receipt of a
message with an error in a data word. This allows failed mes-sages
in a bulk data transfer to be retried without disrupting the
circular buffer data structure, and without intervention by the
RT's host processor.
GLOBAL CIRCULAR BUFFER
Beyond the programmable choice of single buffer mode, double
buffer mode, or circular buffer mode, programmable on an individ-ual
subaddress basis, the Mini-ACE Mark3 RT architecture pro-
DESCRIPTOR
STACKS
FIGURE 6. RT SINGLE BUFFERED MODE
DATA
BLOCKS
DATA BLOCK
DATA BLOCK
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
LOOK-UP
TABLE ADDR
LOOK-UP TABLE
(DATA BLOCK ADDR)
15 13 0
CURRENT
AREA B/A
STACK
POINTERS
(See note)
Note: Lookup table is not used for mode commands when enhanced mode codes are enabled.

27
vides an additional option, a variable sized global circular buffer.
The Mini-ACE Mark3 RT allows for a mix of single buffered, dou-ble
buffered, and individually circular buffered subaddresses,
along with the use of the global double buffer for any arbitrary
group of receive(/broadcast) or broadcast subaddresses.
In the global circular buffer mode, the data for multiple receive
subaddresses is stored in the same circular buffer data structure.
The size of the global circular buffer may be programmed for 128,
256, 512, 1024, 2048, 4096, or 8192 words, by means of bits 11,
10, and 9 of Configuration Register #6. As shown in TABLE 40,
individual subaddresses may be mapped to the global circular
buffer by means of their respective subaddress control words.
Notes:
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DATA
BLOCK 0
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DATA BLOCK POINTER
FIGURE 7. RT DOUBLE BUFFERED MODE
15 13 0
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER
STACK
POINTERS
DESCRIPTOR
STACK
CURRENT
AREA B/A
DATA
BLOCKS
DATA
BLOCK 1
X..X 0 YYYYY
X..X 1 YYYYY
RECEIVE DOUBLE
BUFFER ENABLE
SUBADDRESS
CONTROL WORD
MSB
LOOK-UP
TABLES
FIGURE 8. RT CIRCULAR BUFFERED MODE
CIRCULAR
BUFFER
ROLLOVER
15 13 0
RECEIVED
(TRANSMITTED)
MESSAGE
DATA
(NEXT LOCATION)
128,
256
8192
WORDS
POINTER TO
CURRENT
DATA BLOCK
POINTER TO
NEXT DATA
BLOCK
LOOK-UP TABLE
ENTRY
CIRCULAR
DATA
BUFFER
LOOK-UP TABLES
LOOK-UP
TABLE
ADDRESS
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER
STACK
POINTERS
DESCRIPTOR
STACK
CURRENT
AREA B/A
1. TX/RS/BCST_SA look-up table entry is updated following valid receive (broadcast) message
or following completion of transit message
*
2. For the Global Circular Buffer Mode, the pointer is read from and re-written to Address 0101 (for Area A)
or Address 0105 (for Area B).
The pointer to the Global Circular Buffer will be stored in location
0101 (for Area A), or location 0105 (for Area B).
The global circular buffer option provides a highly efficient
method for storing received message data. It allows for frequent-ly
used subaddresses to be mapped to individual data blocks,
while also providing a method for asynchronously received mes-sages
to infrequently used subaddresses to be logged to a com-mon
area. Alternatively, the global circular buffer provides an
efficient means for storing the received data words for all subad-dresses.
Under this method, all received data words are stored
chronologically, regardless of subaddress.

28
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RT DESCRIPTOR STACK
The descriptor stack provides a chronology of all messages
processed by the Mini-ACE Mark3 RT. Reference FIGURES 6, 7,
and 8. Similar to BC mode, there is a four-word block descriptor
in the Stack for each message processed. The four entries to
each block descriptor are the Block Status Word, Time Tag Word,
the pointer to the start of the message's data block, and the 16-
bit received Command Word.
The RT Block Status Word includes indications of whether a par-ticular
message is ongoing or has been completed, what bus
channel it was received on, indications of illegal commands, and
flags denoting various message error conditions. For the double
buffering, subaddress circular buffering, and global circular
buffering modes, the data block pointer may be used for locating
the data blocks for specific messages. Note that for mode code
commands, there is an option to store the transmitted or
received data word as the third word of the descriptor, in place of
the data block pointer.
The Time Tag Word provides a 16-bit indication of relative time
for individual messages. The resolution of the Mini-ACE Mark3's
time tag is programmable from among 2, 4, 8, 16, 32, or 64
μs/LSB. There is also a provision for using an external clock input
for the time tag (consult factory). If enabled, there is a time tag
rollover interrupt, which is issued when the value of the time tag
rolls over from FFFF(hex) to 0. Other time tag options include the
capabilities to clear the time tag register following receipt of a
Synchronize (without data) mode command and/or to set the
time tag following receipt of a Synchronize (with data) mode
command. For the latter, there is an added option to filter the
"set" capability based on the LSB of the received data word
being equal to logic "0".
RT INTERRUPTS
The Mini-ACE Mark3 offers a great deal of flexibility in terms of
RT interrupt processing. By means of the Mini-ACE Mark3’s two
Interrupt Mask Registers, the RT may be programmed to issue
interrupt requests for the following events/conditions: End-of-
(every)Message, Message Error, Selected (transmit or receive)
Subaddress, 100% Circular Buffer Rollover, 50% Circular Buffer
Rollover, 100% Descriptor Stack Rollover, 50% Descriptor Stack
Rollover, Selected Mode Code, Transmitter Timeout, Illegal
Command, and Interrupt Status Queue Rollover.
Interrupts for 50% Rollovers of Stacks and Circular Buffers.
The Mini-ACE Mark3 RT and Monitor are capable of issuing host
interrupts when a subaddress circular buffer pointer or stack
pointer crosses its mid-point boundary. For RT circular buffers,
this is applicable for both transmit and receive subaddresses.
Reference FIGURE 9. There are four interrupt mask and inter-rupt
status register bits associated with the 50% rollover
function:
(1) RT circular buffer;
(2) RT command (descriptor) stack;
(3) Monitor command (descriptor) stack; and
(4) Monitor data stack.
The 50% rollover interrupt is beneficial for performing bulk data
transfers. For example, when using circular buffering for a partic-ular
receive subaddress, the 50% rollover interrupt will inform the
host processor when the circular buffer is half full. At that time,
the host may proceed to read the received data words in the
upper half of the buffer, while the Mini-ACE Mark3 RT writes
received data words to the lower half of the circular buffer. Later,
when the RT issues a 100% circular buffer rollover interrupt, the
host can proceed to read the received data from the lower half of
the buffer, while the Mini-ACE Mark3 RT continues to write
received data words to the upper half of the buffer.
Interrupt status queue. The Mini-ACE Mark3 RT, Monitor, and
combined RT/Monitor modes include the capability for generat-ing
an interrupt status queue. As illustrated in FIGURE 10, this
provides a chronological history of interrupt generating events
and conditions. In addition to the Interrupt Mask Register, the
Interrupt Status Queue provides additional filtering capability,
such that only valid messages and/or only invalid messages may
result in the creation of an entry to the Interrupt Status Queue.
Queue entries for invalid and/or valid messages may be disabled
by means of bits 8 and 7 of configuration register #6.
The interrupt status queue is 64 words deep, providing the capa-bility
to store entries for up to 32 messages. These events and
conditions include both message-related and non-message
related events. Note that the Interrupt Vector Queue Pointer
Register will always point to the next location (modulo 64) fol-lowing
the last vector/pointer pair written by the Mini-ACE Mark3
RT.
The pointer to the Interrupt Status Queue is stored in the
INTERRUPT VECTOR QUEUE POINTER REGISTER (register
address 1F). This register must be initialized by the host, and is
subsequently incremented by the RT message processor. The
interrupt status queue is 64 words deep, providing the capability
to store entries for up to 32 messages.
The queue rolls over at addresses of modulo 64. The events that
result in queue entries include both message-related and non-message-
related events. Note that the Interrupt Vector Queue
Pointer Register will always point to the next location (modulo 64)
following the last vector/pointer pair written by the Mini-ACE
Mark3 RT, Monitor, or RT/Monitor.
Each event that causes an interrupt results in a two-word entry
to be written to the queue. The first word of the entry is the inter-rupt
vector. The vector indicates which interrupt event(s)/condi-tion(
s) caused the interrupt.
The interrupt events are classified into two categories: message
interrupt events and non-message interrupt events. Message-

DATA POINTER
DESCRIPTOR STACK
FIGURE 9. 50% and 100% ROLLOVER INTERRUPTS
INTERRUPT STATUS QUEUE
(64 Locations)
INTERRUPT
VECTOR
29
Note
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FIGURE 10. RT (and MONITOR) INTERRUPT STATUS QUEUE
(shown for message Interrupt event)
DATA WORD
BLOCK
DESCRIPTOR
STACK
PARAMETER
(POINTER)
INTERRUPT VECTOR
QUEUE POINTER
REGISTER (IF)
BLOCK STATUS WORD
TIME TAG
DATA BLOCK POINTER
RECEIVED COMMAND
NEXT
VECTOR
CIRCULAR
BUFFER*
LOOK-UP TABLE (128,256,...8192 WORDS)
RECEIVED
(TRANSMITTED)
MESSAGE DATA
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND WORD
50%
ROLLOVER
INTERRUPT
50%
The example shown is for an RT Subaddress Circular Buffer.
The 50% and 100% Rollover Interrupts are also applicable to
the RT Global Circulat Buffer, RT Command Stack,
Monitor Command Stack, and Monitor Data Stack.
100%
ROLLOVER
INTERRUPT
100%

DESCRIPTION
Brdcst / Rx, SA 0. MC15-0
Brdcst / RX, SA 0. MC31-16
Brdcst / Rx, SA 1. WC15-0
Brdcst / Rx, SA 1. WC31-16
•
•
•
Brdcst / Rx, SA 31. MC31-16
Brdcst / Tx, SA 0. MC15-0
Brdcst / Tx, SA 0.MC31-16
Brdcst / Tx, SA 1. WC15-0
•
•
•
Brdcst / Tx, SA 30. WC31-16
Own Addr / Rx, SA 0. MC15-0
Own Addr / Rx, SA 1. WC15-0
Own Addr / Rx, SA 1. WC31-16
•
•
•
Own Addr / Tx, SA 0. MC15-0
Own Addr / Tx, SA 1. WC15-0
30
ADDRESS
300
301
302
303
•
•
•
33F
340
341
342
•
•
•
37D
37E
37F
380
381
382
383
•
•
•
3BE
3BF
3C0
3C1
3C2
3C3
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TABLE 41. ILLEGALIZATION TABLE MEMORY MAP
3FC
3FD
3FE
•
•
•
3FF
•
•
•
based interrupt events include End-of-Message, Selected mode
code, Format error, Subaddress control word interrupt, RT
Circular buffer Rollover, Handshake failure, RT Command stack
rollover, transmitter timeout, MT Data Stack rollover,
MT Command Stack rollover, RT Command Stack 50% rollover,
MT Data Stack 50% rollover, MT Command Stack 50% rollover,
and RT Circular buffer 50% rollover. Non-message interrupt
events/conditions include time tag rollover, RT address parity
error, RAM parity error, and BIT completed.
Bit 0 of the interrupt vector (interrupt status) word indicates
whether the entry is for a message interrupt event (if bit 0 is logic
"1") or a non-message interrupt event (if bit 0 is logic "0"). It is not
possible for one entry on the queue to indicate both a message
interrupt and a non-message interrupt.
As illustrated in FIGURE 10, for a message interrupt event, the
parameter word is a pointer. The pointer will reference the first
word of the RT or MT command stack descriptor (i.e., the Block
Status Word).
For a RAM Parity Error non-message interrupt, the parameter
will be the RAM address where the parity check failed. For the
RT address Parity Error, Protocol Self-test Complete, and Time
Tag rollover non-message interrupts, the parameter is not used;
it will have a value of 0000.
If enabled, an INTERRUPT STATUS QUEUE ROLLOVER inter-rupt
will be issued when the value of the queue pointer address
rolls over at a 64-word address boundary.

31
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RT AUTO-BOOT OPTION
If utilized, the RT pin-programmable auto-boot option allows the
Mini-ACE Mark3 RT to automatically initialize as an active
remote terminal with the Busy status word bit set to logic "1"
immediately following power turn-on. This is a useful feature for
MIL-STD-1760 applications, in which the RT is required to be
responding within 150 ms after power-up. This feature is avail-able
for versions of the Mini-ACE Mark3 with 4K words of RAM.
OTHER RT FEATURES
The Mini-ACE Mark3 includes options for the Terminal flag sta-tus
word bit to be set either under software control and/or auto-matically
following a failure of the loopback self-test. Other soft-ware
programmable RT options include software programmable
RT status and RT BIT words, automatic clearing of the Service
Request bit following receipt of a Transmit vector word mode
command, options regarding Data Word transfers for the Busy
and Message error (illegal) Status word bits, and options for the
handling of 1553A and reserved mode codes.
MONITOR ARCHITECTURE
The Mini-ACE Mark3 includes three monitor modes:
(1) A Word Monitor mode
(2) A selective message monitor mode
(3) A combined RT/message monitor mode
For new applications, it is recommended that the selective mes-sage
monitor mode be used, rather than the word monitor mode.
Besides providing monitor filtering based on RT address, T/R bit,
and subaddress, the message monitor eliminates the need to
determine the start and end of messages by software.
TABLE 42. RT BIT WORD
BIT DESCRIPTION
15(MSB) TRANSMITTER TIMEOUT
14 LOOP TEST FAILURE B
13 LOOP TEST FAILURE A
12 HANDSHAKE FAILURE
TRANSMITTER SHUTDOWN B
11
10 TRANSMITTER SHUTDOWN A
9 TERMINAL FLAG INHIBITED
8 BIT TEST FAILURE
7 HIGH WORD COUNT
6 LOW WORD COUNT
5 INCORRECT SYNC RECEIVED
4 PARITY / MANCHESTER ERROR RECEIVED
3 RT-to-RT GAP / SYNC ADDRESS ERROR
2 RT-to-RT NO RESPONSE ERROR
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RT COMMAND ILLEGALIZATION
The Mini-ACE Mark3 provides an internal mechanism for RT
Command Word illegalizing. By means of a 256-word area in
shared RAM, the host processor may designate that any mes-sage
be illegalized, based on the command word T/R bit, sub-address,
and word count/mode code fields. The Mini-ACE Mark3
illegalization scheme provides the maximum in flexibility, allow-ing
any subset of the 4096 possible combinations of broad-cast/
own address, T/R bit, subaddress, and word count/mode
code to be illegalized.
The address map of the Mini-ACE Mark3's illegalizing table is
illustrated in TABLE 41.
BUSY BIT
The Mini-ACE Mark3 RT provides two different methods for set-ting
the Busy status word bit: (1) globally, by means of
Configuration Register #1; or (2) on a T/R-bit/subaddress basis,
by means of a RAM lookup table. If the host CPU asserts the
BUSY bit to logic “0“ in Configuration Register #1, the Mini-ACE
Mark3 RT will respond to all non-broadcast commands with the
Busy bit set in its RT Status Word.
Alternatively, there is a Busy lookup table in the Mini-ACE Mark3
shared RAM. By means of this table, it is possible for the host
processor to set the busy bit for any selectable subset of the 128
combinations of broadcast/own address, T/R bit, and subad-dress.
If the busy bit is set for a transmit command, the Mini-ACE
Mark3 RT will respond with the busy bit set in the status word,
but will not transmit any data words. If the busy bit is set for a
receive command, the RT will also respond with the busy status
bit set. There are two programmable options regarding the
reception of data words for a non-mode code receive command
for which the RT is busy: (1) to transfer the received data words
to shared RAM; or (2) to not transfer the data words to shared
RAM.
RT ADDRESS
The Mini-ACE Mark3 offers several different options for desig-nating
the Remote Terminal address. These include the follow-ing:
(1) hardwired, by means of the 5 RT ADDRESS inputs, and
the RT ADDRESS PARITY input; (2) by means of the RT
ADDRESS (and PARITY) inputs, but latched via hardware, on
the rising edge of the RT_AD_LAT input signal; (3) input by
means of the RT ADDRESS (and PARITY) inputs, but latched via
host software; and (4) software programmable, by means of an
internal register. In all four configurations, the RT address is
readable by the host processor.
RT BUILT-IN-TEST (BIT) WORD
The bit map for the Mini-ACE Mark3's internal RT Built-in-Test
(BIT) Word is indicated in TABLE 42. 0 (LSB) COMMAND WORD CONTENTS ERROR
1 RT-to-RT 2ND COMMAND WORD ERROR

32
TABLE 43. TYPICAL WORD MONITOR MEMORY
MAP
FUNCTION
HEX
ADDRESS
0000 First Received 1553 Word
0001 First Identification Word
0002 Second Received 1553 Word
0003 Second Identification Word
0004
005 Third Identification Word
•
•
•
Stack Pointer
(Fixed Location - gets overwritten)
Received 1553 Words and Identification Word
•
•
•
0100
•
•
•
FFFF
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Third Received 1553 Word
•
•
•
WORD MONITOR MODE
In the Word Monitor Terminal mode, the Mini-ACE Mark3 moni-tors
both 1553 buses. After the software initialization and Monitor
Start sequences, the Mini-ACE Mark3 stores all Command,
Status, and Data Words received from both buses. For each
word received from either bus, a pair of words is stored to the
Mini-ACE Mark3's shared RAM. The first word is the word
received from the 1553 bus. The second word is the Monitor
Identification (ID), or "Tag" word. The ID word contains informa-tion
relating to bus channel, word validity, and inter-word time
gaps. The data and ID words are stored in a circular buffer in the
shared RAM address space.
WORD MONITOR MEMORY MAP
A typical word monitor memory map is illustrated in TABLE 43.
TABLE 43 assumes a 64K address space for the Mini-ACE
Mark3's monitor. The Active Area Stack pointer provides the
address where the first monitored word is stored. In the example,
it is assumed that the Active Area Stack Pointer for Area A (loca-tion
0100) is initialized to 0000. The first received data word is
stored in location 0000, the ID word for the first word is stored in
location 0001, etc.
The current Monitor address is maintained by means of a
counter register. This value may be read by the CPU by means
of the Data Stack Address Register. It is important to note that
when the counter reaches the Stack Pointer address of 0100 or
0104, the initial pointer value stored in this shared RAM location
will be overwritten by the monitored data and ID Words. When
the internal counter reaches an address of FFFF (or 0FFF, for an
Mini-ACE Mark3 with 4K RAM), the counter rolls over to 0000.
WORD MONITOR TRIGGER
In the Word Monitor mode, there is a pattern recognition trigger
and a pattern recognition interrupt. The 16-bit compare word for
both the trigger and the interrupt is stored in the Monitor Trigger
Word Register. The pattern recognition interrupt is enabled by
setting the MT Pattern Trigger bit in Interrupt Mask Register #1.
The pattern recognition trigger is enabled by setting the Trigger
Enable bit in Configuration Register #1 and selecting either the
Start-on-trigger or the Stop-on-trigger bit in Configuration
Register #1.
The Word Monitor may also be started by means of a low-to-high
transition on the EXT_TRIG input signal.
SELECTIVE MESSAGE MONITOR MODE
The Mini-ACE Mark3 Selective Message Monitor provides
monitoring of 1553 messages with filtering based on RT
address, T/R bit, and subaddress with no host processor inter-vention.
By autonomously distinguishing between 1553 com-mand
and status words, the Message Monitor determines
when messages begin and end, and stores the messages into
RAM, based on a programmable filter of RT address, T/R bit,
and subaddress.
The selective monitor may be configured as just a monitor, or as a
combined RT/Monitor. In the combined RT/Monitor mode, the
Mini-ACE Mark3 functions as an RT for one RT address (including
broadcast messages), and as a selective message monitor for the
other 30 RT addresses. The Mini-ACE Mark3 Message Monitor
contains two stacks, a command stack and a data stack, that are
independent from the RT command stack. The pointers for these
stacks are located at fixed locations in RAM.
MONITOR SELECTION FUNCTION
Following receipt of a valid command word in Selective Monitor
mode, the Mini-ACE Mark3 will reference the selective monitor
lookup table to determine if the particular command is enabled.
The address for this location in the table is determined by means
of an offset based on the RT Address, T/R bit, and Subaddress
bit 4 of the current command word, and concatenating it to the
monitor lookup table base address of 0280 (hex). The bit location
within this word is determined by subaddress bits 3-0 of the cur-rent
command word.
If the specified bit in the lookup table is logic "0", the command
is not enabled, and the Mini-ACE Mark3 will ignore this com-mand.
If this bit is logic "1", the command is enabled and the
Mini-ACE Mark3 will create an entry in the monitor command
descriptor stack (based on the monitor command stack pointer),
and store the data and status words associated with the com-mand
into sequential locations in the monitor data stack. In addi-tion,
for an RT-to-RT transfer in which the receive command is
selected, the second command word (the transmit command) is
stored in the monitor data stack.
The address definition for the Selective Monitor Lookup TABLE
is illustrated in TABLE 44.

33
TABLE 44. MONITOR SELECTION TABLE LOOKUP
ADDRESS
BIT DESCRIPTION
15(MSB) Logic “0”
14 Logic “0”
13 Logic “0”
12 Logic “0”
Logic “0”
11
10 Logic “0”
9 Logic “1”
8 Logic “0”
7 Logic “1”
6 RTAD_4
5 RTAD_3
4 RTAD_2
3 RTAD_1
2 RTAD_0
1 TRANSMIT / RECEIVE
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TABLE 45. TYPICAL SELECTIVE MESSAGE
MONITOR MEMORY MAP (shown for 4K RAM for
“Monitor only” mode)
DESCRIPTION
ADDRESS
(HEX)
0000-0101 Not Used
0102 Monitor Command Stack Pointer A (fixed location)
0103 Monitor Data Stack Pointer A (fixed location)
0104-0105 Not Used
0106
0107 Monitor Data Stack Pointer B (fixed location)
0108-027F Not Used
0280-02FF Selective Monitor Lookup Table (fixed location)
0300-03FF Not Used
0400-07FF Monitor Command Stack A
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SELECTIVE MESSAGE MONITOR MEMORY
ORGANIZATION
A typical memory map for the Mini-ACE Mark3 in the Selective
Message Monitor mode, assuming a 4K RAM space, is illustrat-ed
in TABLE 45. This mode of operation defines several fixed
locations in the RAM. These locations are allocated in a way in
which none of them overlap with the fixed RT locations. This
allows for the combined RT/Selective Message Monitor mode.
The fixed memory map consists of two Monitor Command Stack
Pointers (locations 102 and 106 hex), two Monitor Data Stack
Pointers (locations 103 and 107 hex), and a Selective Message
Monitor Lookup Table (locations 0280 through 02FF hex).
For this example, the Monitor Command Stack size is assumed
to be 1K words, and the Monitor Data Stack size is assumed to
be 2K words.
FIGURE 11 illustrates the Selective Message Monitor operation.
Upon receipt of a valid Command Word, the Mini-ACE Mark3 will
reference the Selective Monitor Lookup Table to determine if the
current command is enabled. If the current command is disabled,
the Mini-ACE Mark3 monitor will ignore (and not store) the cur-rent
message. If the command is enabled, the monitor will create
an entry in the Monitor Command Stack at the address location
referenced by the Monitor Command Stack Pointer, and an entry
in the monitor data stack starting at the location referenced by
the Monitor Data Stack Pointer.
The format of the information in the data stack depends on the for-mat
of the message that was processed. For example, for a BC-to-
RT transfer (receive command), the monitor will store the command
word in the monitor command descriptor stack, with the data words
and the receiving RT's status word stored in the monitor data stack.
Monitor Command Stack Pointer B (fixed location)
0800-0FFF Monitor Data Stack A
The size of the monitor command stack is programmable, with
choices of 256, 1K, 4K, or 16K words. The monitor data stack
size is programmable with choices of 512, 1K, 2K, 4K, 8K, 16K,
32K or 64K words.
MONITOR INTERRUPTS
Selective monitor interrupts may be issued for End-of-message
and for conditions relating to the monitor command stack point-er
and monitor data stack pointer. The latter, which are shown in
FIGURE 9, include Command Stack 50% Rollover, Command
Stack 100% Rollover, Data Stack 50% Rollover, and Data Stack
100% Rollover.
The 50% rollover interrupts may be used to inform the host proces-sor
when the command stack or data stack is half full. At that time,
the host may proceed to read the received messages in the upper
half of the respective stack, while the Mini-ACE Mark3 monitor
writes messages to the lower half of the stack. Later, when the
monitor issues a 100% stack rollover interrupt, the host can pro-ceed
to read the received data from the lower half of the stack,
while the Mini-ACE Mark3 monitor continues to write received data
words to the upper half of the stack.
INTERRUPT STATUS QUEUE
Like the Mini-ACE Mark3 RT, the Selective Monitor mode
includes the capability for generating an interrupt status queue.
As illustrated in FIGURE 10, this provides a chronological histo-ry
of interrupt generating events. Besides the two Interrupt Mask
Registers, the Interrupt Status Queue provides additional filter-ing
capability, such that only valid messages and/or only invalid
messages may result in entries to the Interrupt Status Queue.
The interrupt status queue is 64 words deep, providing the capa-bility
to store entries for up to 32 monitored messages.
0(LSB) SUBADDRESS 4

34
NOTE
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MONITOR DATA
BLOCK #N
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15 13 0
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER #1
MONITOR COMMAND
STACK POINTERS
MONITOR
COMMAND STACKS
CURRENT
AREA B/A
MONITOR DATA
STACKS
MONITOR DATA
BLOCK #N + 1
CURRENT
COMMAND WORD
MONITOR DATA
STACK POINTERS
IF THIS BIT IS "0" (NOT SELECTED)
NO WORDS ARE STORED IN EITHER
THE COMMAND STACK OR DATA STACK.
IN ADDITION, THE COMMAND AND DATA
STACK POINTERS WILL NOT BE UPDATED.
SELECTIVE MONITOR
LOOKUP TABLES
SELECTIVE MONITOR
ENABLE
(SEE NOTE)
OFFSET BASED ON
RTA4-RTA0, T/R, SA4
FIGURE 11. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT
MISCELLANEOUS
CLOCK INPUT
The Mini-ACE Mark3 decoder is capable of operating from a 10,
12, 16, or 20 MHz clock input. Depending on the configuration
of the specific model Mini-ACE Mark3 terminal, the selection of
the clock input frequency may be chosen by one of either two
methods. For all versions, the clock frequency may be specified
by means of the host processor writing to Configuration
Register #6. With the second method, which is applicable only
for the versions incorporating 4K (but not 64K) words of internal
RAM, the clock frequency may be specified by means of the
input signals that are otherwise used as the A15 and A14
address lines.
ENCODER/DECODERS
For the selected clock frequency, there is internal logic to derive
the necessary clocks for the Manchester encoder and decoders.
For all clock frequencies, the decoders sample the receiver out-puts
on both edges of the input clock. By in effect doubling the
decoders' sampling frequency, this serves to widen the tolerance
to zero-crossing distortion, and reduce the bit error rate.
For interfacing to fiber optic transceivers (e.g., for MIL-STD-1773
applications), the decoders are capable of operating with single-ended,
rather than double-ended, input signals. The standard
transceiverless version (BU-64XXXX0) of the Mini-ACE Mark3 is
internally strapped for single-ended input signals. For applica-tions
involving the use of double-ended transceivers, it is sug-gested
that you contact the factory at DDC regarding a double-ended
transceiverless version of the Mini-ACE Mark3.
TIME TAG
The Mini-ACE Mark3 includes an internal read/writable Time Tag
Register. This register is a CPU read/writable 16-bit counter with
a programmable resolution of either 2, 4, 8, 16, 32, or 64 μs per
LSB. Another option allows software controlled incrementing of
the Time Tag Register. This supports self-test for the Time Tag

35
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Register. For each message processed, the value of the Time
Tag Register is loaded into the second location of the respective
descriptor stack entry ("TIME TAG WORD") for both the BC and
RT modes.
The functionality involving the Time Tag Register that's compati-ble
with ACE/Mini-ACE (Plus) includes: the capability to issue an
interrupt request and set a bit in the Interrupt Status Register
when the Time Tag Register rolls over FFFF to 0000; for RT
mode, the capability to automatically clear the Time Tag Register
following reception of a Synchronize (without data) mode com-mand,
or to load the Time Tag Register following a Synchronize
(with data) mode command.
Additional time tag features supported by the Mini-ACE Mark3
include the capability for the BC to transmit the contents of the
Time Tag Register as the data word for a Synchronize (with data)
mode command; the capability for the RT to "filter" the data word
for the Synchronize with data mode command, by only loading
the Time Tag Register if the LSB of the received data word is "0";
an instruction enabling the BC Message Sequence Control
engine to load the Time Tag Register with a specified value; and
an instruction enabling the BC Message Sequence Control
engine to write the value of the Time Tag Register to the General
Purpose Queue.
INTERRUPTS
The Mini-ACE Mark3 series terminals provide many program-mable
options for interrupt generation and handling. The inter-rupt
output pin (INT) has three software programmable modes of
operation: a pulse, a level output cleared under software control,
or a level output automatically cleared following a read of the
Interrupt Status Register (#1 or #2).
Individual interrupts are enabled by the two Interrupt Mask
Registers. The host processor may determine the cause of the
interrupt by reading the two Interrupt Status Registers, which
provide the current state of interrupt events and conditions. The
Interrupt Status Registers may be updated in two ways. In one
interrupt handling mode, a particular bit in Interrupt Status
Register #1 or #2 will be updated only if the event occurs and the
corresponding bit in Interrupt Mask Register #1 or #2 is enabled.
In the enhanced interrupt handling mode, a particular bit in one
of the Interrupt Status Registers will be updated if the event/con-dition
occurs regardless of the value of the corresponding
Interrupt Mask Register bit. In either case, the respective
Interrupt Mask Register (#1 or #2) bit is used to enable an inter-rupt
for a particular event/condition.
The Mini-ACE Mark3 supports all the interrupt events from
ACE/Mini-ACE (Plus), including RAM Parity Error, Transmitter
Timeout, BC/RT Command Stack Rollover, MT Command Stack
and Data Stack Rollover, Handshake Error, BC Retry, RT Address
Parity Error, Time Tag Rollover, RT Circular Buffer Rollover, BC
Message, RT Subaddress, BC End-of-Frame, Format Error, BC
Status Set, RT Mode Code, MT Trigger, and End-of-Message.
For the Mini-ACE Mark3's Enhanced BC mode, there are four
user-defined interrupt bits. The BC Message Sequence Control
Engine includes an instruction enabling it to issue these inter-rupts
at any time.
For RT and Monitor modes, the Mini-ACE Mark3 architecture
includes an Interrupt Status Queue. This provides a mechanism
for logging messages that result in interrupt requests. Entries to
the Interrupt Status Queue may be filtered such that only valid
and/or invalid messages will result in entries on the queue.
The Mini-ACE Mark3 incorporates additional interrupt conditions
beyond the ACE/Mini-ACE (Plus), based on the addition of
Interrupt Mask Register #2 and Interrupt Status Register #2. This
is accomplished by chaining the two Interrupt Status Registers
using the INTERRUPT CHAIN BIT (bit 0) in Interrupt Status
Register #2 to indicate that an interrupt has occurred in Interrupt
Status Register #1. Additional interrupts include "Self-Test
Completed", masking bits for the Enhanced BC Control
Interrupts, 50% Rollover interrupts for RT Command Stack, RT
Circular Buffers, MT Command Stack, and MT Data Stack; BC
Op Code Parity Error, (RT) Illegal Command, (BC) General
Purpose Queue or (RT/MT) Interrupt Status Queue Rollover,
Call Stack Pointer Register Error, BC Trap Op Code, and the four
User-Defined interrupts for the Enhanced BC mode.
BUILT-IN TEST
A salient feature of the Mini-ACE Mark3 is its highly autonomous
self-test capability. This includes both protocol and RAM self-tests.
Either or both of these self-tests may be initiated by com-mand(
s) from the host processor.
The protocol test consists of a comprehensive toggle test of the
terminal's logic. The test includes testing of all registers,
Manchester decoders, protocol logic, and memory management
logs. This test is completed in approximately 32,000 clock cycles.
That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7
ms at 12 MHz, and 3.2 ms at 10 MHz.
There is also a separate built-in test (BIT) for the Mini-ACE
Mark3's 4K X 16 or 64K X 16 shared RAM. This test consists of
writing and then reading/verifying the two walking patterns "data
= address" and "data = address inverted". This test takes 10
clock cycles per word. For a Mini-ACE Mark3 with 4K words of
RAM, this is about 2.0 ms with a 20 MHz clock, 2.6 ms at 16
MHz, 3.4 ms at 12 MHz, or 4.1 ms at 10 MHz. For an Mini-ACE
Mark3 with 64K words of RAM, this test takes about 32.8 ms with
a 20 MHz clock, 40.1 ms at 16 MHz, 54.6 ms at 12 MHz, or 65.6
ms at 10 MHz.
The Mini-ACE Mark3 built-in protocol test is performed automati-cally
at power-up. In addition, the protocol or RAM self-tests may
be initiated by a command from the host processor, via the
START/RESET REGISTER. For RT mode, this may include the
host processor invoking self-test following receipt of an Initiate
self-test mode command. The results of the self-test are host

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accessible by means of the BIT status register. For RT mode, the
result of the self-test may be communicated to the bus controller
via bit 8 of the RT BIT word ("0" = pass, "1" = fail).
Assuming that the protocol self-test passes, all of the register
and shared RAM locations will be restored to their state prior to
the self-test, with the exception of the 60 RAM address locations
0342-037D and the TIME TAG REGISTER. Note that for RT
mode, these locations map to the illegalization lookup table for
"broadcast transmit subaddresses 1 through 30" (non-mode
code subaddresses). Since MIL-STD-1553 does not define
these as valid command words, this section of the illegalization
lookup table is normally not used during RT operation. The TIME
TAG REGISTER will continue to increment during the self-test.
If there is a failure of the protocol self-test, it is possible to access
information about the first failed vector.This may be done by means
of the Mini-ACE Mark3's upper registers (register addresses 32
through 63). Through these registers, it is possible to determine the
self-test ROM address of the first failed vector, the expected
response data pattern (from the ROM), the register or memory
address, and the actual (incorrect) data value read from register or
memory. The on-chip self-test ROM is 4K X 24.
Note that the RAM self-test is destructive. That is, following the
RAM self-test, regardless of whether the test passes or fails, the
shared RAM is not restored to its state prior to this test. Following
a failed RAM self-test, the host may read the internal RAM to
determine which location(s) failed the walking pattern test.
RAM PARITY
The BC/RT/MT version of the Mini-ACE Mark3 is available with
options of 4K or 64K words of internal RAM. For the 64K option,
the RAM is 17 bits wide. The 64K X 17 internal RAM allows for par-ity
generation for RAM write accesses, and parity checking for
RAM read accesses. This includes host RAM accesses, as well as
accesses by the Mini-ACE Mark3’s internal logic. When the Mini-
ACE Mark3 detects a RAM parity error, it reports it to the host
processor by means of an interrupt and a register bit. Also, for the
RT and Selective Message Monitor modes, the RAM address
where a parity error was detected will be stored on the Interrupt
Status Queue (if enabled).
RELOCATABLE MEMORY MANAGEMENT LOCATIONS
In the Mini-ACE Mark3’s default configuration, there is a fixed
area of shared RAM addresses, 0000h-03FF, that is allocated for
storage of the BC's or RT's pointers, counters, tables, and other
"non-message" data structures. As a means of reducing the over-all
memory address space for using multiple Mini-ACE Mark3’s in
a given system (e.g., for use with the DMA interface configura-tion),
the Mini-ACE Mark3 allows this area of RAM to be relocat-ed
by means of 6 configuration register bits.To provide backwards
compatibility to ACE and Mini-ACE, the default for this RAM area
is 0000h-03FFh.
HOST PROCESSOR INTERFACE
The Mini-ACE Mark3 supports a wide variety of processor interface
configurations. These include shared RAM and DMA configurations,
straightforward interfacing for 16-bit and 8-bit buses, support for both
non-multiplexed and multiplexed address/data buses, non-zero wait
mode for interfacing to a processor address/data buses, and zero
wait mode for interfacing (for example) to microcontroller I/O ports. In
addition, with respect to the ACE/Mini-ACE, the Mini-ACE Mark3
provides two major improvements: (1) reduced maximum host
access time for shared RAM mode; and (2) increased maximum
DMA grant time for the transparent/DMA mode.
The Mini-ACE Mark3's maximum host holdoff time (time prior to
the assertion of the READYD handshake signal) has been sig-nificantly
reduced. For ACE/Mini-ACE, this maximum holdoff
time is 17 internal word transfer cycles, resulting in an overall
holdoff time of approximately 4.6 μs, using a 16 MHz clock. By
comparison, using the Mini-ACE Mark3's ENHANCED CPU
ACCESS feature, this worst-case holdoff time is reduced signifi-cantly,
to a single internal transfer cycle. For example, when
operating the Mini-ACE Mark3 in its 16-bit buffered, non-zero
wait configuration with a 16 MHz clock input, this results in a
maximum overall host transfer cycle time of 632 ns for a read
cycle, or 570 ns for a write cycle.
In addition, when using the ACE or Mini-ACE in the transpar-ent/
DMA configuration, the maximum request-to-grant time,
which occurs prior to an RT start-of-message sequence, is
4.0 μs with a 16 MHz clock, or 3.5 μs with a 12 MHz clock. For
the Mini-ACE Mark3 functioning as a MIL-STD-1553B RT, this
time has been increased to 8.5 μs at 10 MHz, 9 μs at 12 MHz,
10 μs at 16 MHz,, and 10.5 μs at 20MHz. This provides greater
flexibility, particularly for systems in which a host has to arbitrate
among multiple DMA requestors.
By far, the most commonly used processor interface configura-tion
is the 16-bit buffered, non-zero wait mode. This configuration
may be used to interface between 16-bit or 32-bit microproces-sors
and an Mini-ACE Mark3. In this mode, only the Mini-ACE
Mark3's internal 4K or 64K words of internal RAM are used for
storing 1553 message data and associated "housekeeping"
functions. That is, in this configuration, the Mini-ACE Mark3 will
never attempt to access memory on the host bus.
FIGURE 12 illustrates a generic connection diagram between a
16-bit (or 32-bit) microprocessor and an Mini-ACE Mark3 for the
16-bit buffered configuration, while FIGURES 13 and 14, and
associated tables illustrate the processor read and write timing
respectively.

CPU ADDRESS LATCH (NOTE 1)
TRANSPARENT/BUFFERED
TRIGGER_SEL
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HOST
CH. A
TX/RXA
+3.3V
TX/RXA
CH. B
TX/RXB
+3.3V
TX/RXB
RTAD4-RTAD0 RT
ADDRESS,
PARITY
RTADP
D15-D0
+3.3V
CLOCK CLK IN
OSCILLATOR
N/C
N/C
A15-A12
A11-A0
N/C
ADDR_LAT
+3.3V
16/8_BIT
MSB/LSB
(NOTE 2) POLARITY_SEL
(NOTE 3) ZERO_WAIT
ADDRESS
DECODER
SELECT
MEM/REG
RD/WR
STRBD
READYD
TAG_CLK
RD/WR
CPU STROBE
+5V
CPU ACKNOWLEDGE (NOTE 4)
RESET
+5V
MSTCLR
SSFLAG/EXT_TRIG
CPU INTERRUPT REQUEST INT
Mini-ACE
Mark3
NOTES:
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUSES. FOR PROCESSORS WITH NON-MULTIPLEXED
ADDRESS AND DATA BUSES, ADDR_LAT SHOULD BE CONNECTED TO +3.3V.
2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ, LOW TO WRITE. IF POLARITY_SEL = "0", RD/WR IS LOW TO READ, HIGH TO WRITE.
3. ZERO_WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.
4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO WAIT TYPE OF INTERFACE.
FIGURE 12. HOST PROCESSOR INTERFACE - 16-BIT BUFFERED CONFIGURATION

NOTES:
1. For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ / 16/8
must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +3.3 V or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT • STRBD is sampled low (satisfying t1)
and the Mark3’s protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer
cycle. After IOEN goes low, SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for register access.
4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
5. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1." If POLARITY_SEL is connected to logic "0,"
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed
7. The timing for A15-A0, MEM/REG and SELECT assumes that ADDR-LAT is connected to logic "1." Refer to Address Latch timing for additional
38
STRBD
MEM/REG
RD/WR
READYD
A15-A0
(Note 7,8,9)
D15-D0
RD/WR become latched internally.
RD/WR must be asserted low to read.
by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
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CLOCK IN
VALID
t5
t7
t3 t8
t11
t13 t15
VALID
t10
t4
t9 t12
t19

VALID
t16
t17
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
IOEN
(Note 2,6)
(Note 6)
(Note 6)

t1
t2
t6
t14 t18
FIGURE 13. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
details.
8. The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0
become latched internally.
9. Setup time given for use in worst case timing calculations. None of the Mark3’s input signals are required to be synchronized to the system clock.
When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an additional clock cycle
will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the Address (A15-A0).
When this occurs, the delay from IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time (t10) must be
increased be one clock cycle.

TABLE FOR FIGURE 13. CPU READING RAM OR REGISTERS
(SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
REF DESCRIPTION MIN TYP MAX UNITS
t1 SELECT and STRBD low setup time prior to clock rising edge ns
SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz) ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 20 MHz) μs
(contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz) ns
(uncontended access @ 16 MHz) ns
ns
Time for MEM/REG and RD/WR to become valid following SELECT and STRBD
low(@ 20 MHz)
@ 16 MHz ns
Time for Address to become valid following SELECT and STRBD low (@ 20 MHz) ns
@ 16 MHz ns
@ 12 MHz ns
t2
t5 CLOCK IN rising edge delay to IOEN falling edge ns
t6 SELECT hold time following IOEN falling ns
t7 MEM/REG, RD/WR setup time prior to CLOCK IN falling edge ns
t8 MEM/REG, RD/WR hold time following CLOCK IN falling edge ns
t9 Address valid setup time prior to CLOCK IN rising edge ns
t10 Address hold time following CLOCK IN rising edge ns
t11
IOEN falling delay to READYD falling (@ 20 MHz) ns
@ 16 MHz ns
@ 12 MHz ns
@ 10 MHz ns
Output Data valid prior to READYD falling (@ 20 MHz) ns
@ 16 MHz ns
@ 12 MHz ns
t12
t13 CLOCK IN rising edge delay to READYD falling ns
t14 READYD falling to STRBD rising release time ns
t15 STRBD rising edge delay to IOEN rising edge and READYD rising edge ns
t16 Output Data hold time following STRBD rising edge ns
t17 STRBD rising delay to output data tri-state ns
t18 STRBD high hold time from READYD rising ns
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105
2.2
355
2.8
430
138
3.7
555
155
10
16
27
12
45
15
30
30
170 187.5 205
285 300 315
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2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
3, 4, 5, 7
3, 4, 5, 7
3, 4, 5, 7
3, 4, 5, 7
6
2
3, 4, 5, 7
3, 4, 5, 7
7, 8
7, 8, 9
6, 9
6, 9
6, 9
6, 9
6
6
6
6
6
6
4.4
655
35
62
11
44
61
40
0
40
0
40
0
25
35
135 150 165
235 250 265
23
40
15
NOTES
2, 9
2, 6 117
@ 10 MHz ns
t3
t4
@ 12 MHz ns
@ 10 MHz ns
@ 10 MHz ns
t19 CLOCK IN rising edge delay to output data valid ns

NOTES:
1. For the 16-bit buffered nonzero wait configuration TRANSPARENT/BUFFERED must be connected to logic 0, ZERO_WAIT and DTREG / 16/8
must be connected to logic 1. The inputs TRIGGER_SEL and MSB/LSB may be connected to either +3.3 V or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT • STRBD is sampled low (satisfying t1)
and the Mark3’s protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer
cycle. After IOEN goes low, SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for register access.
4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
5. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic 1. If POLARITY_SEL is connected to logic 0,
6. The timing for the IOEN and READYD outputs assume a 50 pf load. For loading above 50 pf, the validity of IOEN and READYD is delayed by an
7. The timing for A15-A0, MEM/REG, and SELECT assumes that ADDR-LAT is connected to logic 1. Refer to Address Latch timing for additional
40
STRBD
MEM/REG
RD/WR
READYD
A15-A0
(Note 7,8,9,10)
D15-D0
RD/WR become latched internally.
RD/WR must be asserted high to write.
additional 0.14 ns/pf typ, 0.28 ns/pf max.
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CLOCK IN
t1
t6
t7
t2
t3
t16 t18
VALID
t8 t9
t14
t15 t17
VALID
t12
t10
t4
t11
t5
VALID
t13
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
IOEN
(Note 2,6)
(Note 6)
(Note 9,10)
FIGURE 14. CPU WRITING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
details.
8. The address bus A15-A0 and data bus D15-D0 are internally buffered transparently until the first rising edge of CLK after IOEN goes low. After
this CLK edge, A15-A0 and D15-D0 become latched internally.
9. Setup time given for use in worst case timing calculations. None of the Mark3’s input signals are required to be synchronized to the system clock.
When SELECT and STRBD do not meet the setup time of t1, but occur during the setup time of an internal flip-flop, an additional clock cycle may
be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the address (A15-A0) and
data (D15-D0). When this occurs, the delay from IOEN falling to READYD falling (t14) increases by one clock cycle and the address and data hold
time (t12 and t13) must be increased by one clock.

REF DESCRIPTION NOTES
MIN TYP MAX UNITS
t1 SELECT and STRBD low setup time prior to clock rising edge 2, 10
15
ns
t2
SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz) ns
105
2.2
(contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz) 2, 6
355
ns
(uncontended access @ 16 MHz) 2, 6 117
ns
2.8
μs
430
ns
(uncontended access @ 12 MHz) 2, 6
138
ns
3.7
μs
555
ns
(uncontended access @ 10 MHz) 2, 6
155
ns
4.4
μs
655
ns
Time for MEM/REG and RD/WR to become valid following SELECT and STRBD
low(@ 20 MHz) ns
10
16
@ 16 MHz ns
@ 12 MHz ns
27
35
3, 4, 5, 7
3, 4, 5, 7
@ 10 MHz ns
Time for Address to become valid following SELECT and STRBD low (@ 20 MHz) 12
ns
@ 16 MHz 25
ns
@ 12 MHz ns
@ 10 MHz ns
Time for data to become valid following SELECT and STRBD low ( @ 20 MHz ) ns
t3
t4
t5
@ 10 MHz
ns
32
82
t6 CLOCK IN rising edge delay to IOEN falling edge ns
0
15
40
6
3, 4, 5, 7
3, 4, 5, 7
t9 MEM/REG, RD/WR setup time following CLOCK IN falling edge 35
ns
35
15
t12 Address valid hold time prior to CLOCK IN rising edge 30
ns
15
@ 10 MHz 6, 9 185 200 215 ns
41
t14
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6, 9 152 167 182 ns
40
∞
40
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TABLE FOR FIGURE 14. CPU WRITING RAM OR REGISTERS
(SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
@ 16 MHz
ns
45
@ 12 MHz
t7 SELECT hold time following IOEN falling ns
t10 Address valid setup time prior to CLOCK IN rising edge ns
IOEN falling delay to READYD falling @ 20 MHz 6, 9 85 100 115
ns
@ 16 MHz
ns
t8 MEM/REG, RD/WR setup time prior to CLOCK IN falling edge ns
6, 9 110 125 140 ns
@ 12 MHz
65
t11 Data valid setup time prior to CLOCK IN rising edge ns
t13 Data valid hold time following CLOCK IN rising edge ns
t15 CLOCK IN rising edge delay to READYD falling ns
t16 READYD falling to STRBD rising release time ns
t17 STRBD rising delay to IOEN rising edge and READYD rising edge ns
t18 STRBD high hold time from READYD rising 10
ns
45
62
2, 6
2, 6
3, 4, 5, 7
3, 4, 5, 7
2
7, 8
7, 8, 9
9
6
6

42
Mini-ACE Mark3
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BU-64743/64843/64863
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INTERFACE TO MIL-STD-1553 BUS
The Mini-ACE Mark3 is the world's first MIL-STD-1553 terminal
powered entirely by 3.3 volts. Unique isolation transformer turns
ratios, single output winding transformers and new interconnec-tion
methods are required in order to meet mandated MIL-STD-
1553 differential voltage levels.
FIGURE 15 illustrates the two possible interface methods
between the Mini-ACE Mark3 series and a MIL-STD-1553 bus.
Connections for both direct (short stub, 1:3.75) and transformer
(long stub, 1:2.7) coupling, as well as nominal peak-to-peak volt-age
levels at various points (when transmitting), are indicated in
the diagram.
The new isolation transformers for the Mini-ACE Mark3 series
now contain only one set of output windings. Different isolation
transformers are now required for a direct or transformer cou-pled,
MIL-STD-1553 Bus implementation.
The center tap of the primary winding (the side of the transformer
that connects to the Mark3) must be directly connected to the
+3.3 volt plane. Additionally, a 10μf, low inductance tantalum
capacitor and a 0.01μf ceramic capacitor must be mounted as
close as possible and with the shortest leads to the center tap of
the transformer(s) and ground plane.
Additionally, during transmission large currents flow from the trans-former
center tap, through the primaries and the TX/RX pins, and
then out the transceiver grounds (pins 22 and 79) into the ground
plane. The traces in this path should be sized accordingly and the
connections to the ground plane should be as short as possible.
10μF
+
.01μF
TX/RX
TX/RX
+
FIGURE 15. MINI-ACE MARK3 INTERFACE TO MIL-STD-1553 BUS
DATA
BUS
Z0
55 Ω
55 Ω
TX/RX
TX/RX
(1:3.75)
(7.4 Vpp) 28 Vpp
1 FT MAX
Z0
(1:2.7)
20 Vpp
(1:1.41)
COUPLING
TRANSFORMER
0.75 Z0
0.75 Z0
LONG STUB
(TRANSFORMER
COUPLED)
20 FT MAX
28 Vpp
SHORT STUB
(DIRECT COUPLED)
OR
DIRECT-COUPLED
ISOLATION TRANSFORMER
BETA B-3383
7 Vpp
7 Vpp
Mini-ACE Mark3
(7.4 Vpp)
3.3V
10μF
.01μF
3.3V
TRANSFORMER-COUPLED
ISOLATION TRANSFORMER
BETA B-3372
NOTES: 1. Transformer center tap capacitors: use a 10μF tantalum for low inductance, and a 0.01μF ceramic.
Both must be mounted as close as possible, and with the shortest leads to the center tap of the
transformer(s) and ground.
2. Connect the Mark3 hybrid grounds as directly as possible to the 3.3V ground plane.
3. Zo = 70 to 85 Ohms.

TABLE 46. BTTC TRANSFORMERS FOR USE WITH MINI-ACE MARK3
TRANSFORMER CONFIGURATION BTTC PART NO.
Single epoxy transformer, through hole, transformer coupled only, 0.625 X 0.630, 0.300 max
height
43
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B-3372
BU-64743/64843/64863
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TRANSFORMERS
In selecting isolation transformers to be used with the Mini-ACE
Mark3, there is a limitation on the maximum amount of leakage
inductance. If this limit is exceeded, the transmitter rise and fall
times may increase, possibly causing the bus amplitude to fall
below the minimum level required by MIL-STD-1553. In addition,
an excessive leakage imbalance may result in a transformer
dynamic offset that exceeds 1553 specifications.
The maximum allowable leakage inductance is a function of the
coupling method. For Transformer Coupled applications, it is a
maximum of 5.0 μH. For Direct it is a maximum of 10.0 μH, and
is measured as follows:
The side of the transformer that connects to the Mark3 is defined
as the primary winding. If one side of the primary is shorted to
the primary center-tap, the inductance should be measured
across the secondary (stub side) winding. This inductance
must be less than 5.0 μH (Transformer Coupled) and 10.0 μH
(Direct Coupled). Similarly, if the other side of the primary is
shorted to the primary center-tap, the inductance measured
across the secondary (stub side) winding must also be less
than 5.0 μH (Transformer Coupled) and 10.0 μH (Direct
Coupled).
The difference between these two measurements is the differ-ential
leakage inductance. This value must be less than 1.0 μH
(Transformer Coupled) and 2.0 μH (Direct Coupled).
Beta Transformer Technology Corporation (BTTC), a subsidiary
of DDC, manufactures transformers in a variety of mechanical
configurations with the required turns ratios of 1:3.75 direct cou-pled,
and 1:2.7 transformer coupled. TABLE 46 provides a listing
of these transformers.
For further information, contact BTTC at 631-244-7393 or at
www.bttc-beta.com.
B-3383
Single epoxy transformer, through hole, direct coupled only, 0.625 X 0.630, 0.300 max height
B-3389
Single epoxy transformer, surface mount, transformer coupled only, 85°C max, 0.625 X 0.625,
0.130 max height

NOTE: Logic ground and transceiver ground are not tied together inside the package.
TABLE 48. 1553 ISOLATION TRANSFORMER (BU-64XX3X8/9 VERSIONS)
SIGNAL NAME DESCRIPTION
TX/RX-A (I/O) 3 Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation transformers.
TX/RX-A (I/O) 5
TX/RX-B (I/O) 15
TX/RX-B (I/O) 17
TABLE 49. INTERFACE TO EXTERNAL TRANSCEIVER (BU-64XX3X0 TRANSCEIVERLESS VERSION)
44
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SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
+3.3V_Xcvr 10
+3.3V_Logic 30, 51, 69
Gnd_Xcvr 22, 79
Gnd_Logic 31, 50, 70
TABLE 47. POWER AND GROUND
SIGNAL NAME
BU-64743X8/X9
BU-64843X8/X9
BU-64863X8/X9
PIN
BU-64743X0
BU-64843X0
BU-64863X0
PIN
-
10, 30, 51, 69
-
22, 79, 31, 50, 70
Transceiver Power
Logic Power
Transceiver Ground
Logic Ground
DESCRIPTION
TXDATA_A (O) 3
TXDATA_A (O) 5
RXDATA_A (I) 8
RXDATA_A
4
(I, not enabled)*
SIGNAL NAME
BU-64743X0
BU-64843X0
BU-64863X0
PIN
DESCRIPTION
Digital Manchester biphase transmit outputs, A bus
Digital Manchester biphase receive inputs, A bus
TXINH_A_OUT (O) 11
TXDATA_B (O) 15
TXDATA_B (O) 17
RXDATA_B (I) 21
Digital output to inhibit external transmitter, A bus
Digital Manchester biphase transmit outputs, B bus
RXDATA_B Digital Manchester biphase receive inputs, B bus
16
(I, not enabled)*
TXINH_B_OUT (O) 9 Digital output to inhibit external transmitter, B bus
UPADDREN / NC 14
4K versions: UPADDREN / 64K versions: NC
For 4K RAM versions, this signal is always configured as UPADDREN.
This signal is used to control the function of the upper 4 address inputs (A15-A12). For these versions of
Mark3 if UPADDREN is connected to logic 1, then these four signals operate as address lines A15-A12. If
UPADDREN is connected to logic 0, then A15 and A14 function as CLK_SEL_1 and CLK_SEL_0 respec-tively;
A13 MUST be connected to +3.3V-LOGIC; and A12 functions as RTBOOT.
BU-64743X8/9
BU-64843X8/9
BU-64863X8/9
PIN
*NOTE: Standard transceiverless parts have their receiver inputs internally strapped for single-ended operation. The RXDATAx_L
pins are connected to inputs that are not enabled. Contact the factory for a non-standard part that enables differential receive
inputs.

TABLE 51. PROCESSOR ADDRESS BUS
BU-64743XX
BU-64843XX
BU-64863XX
D15 (MSB) 59
D14 56
D13 54
D12 55
D11 58
A15 (MSB) 73 16-bit bi-directional address bus.
A14 80 For 64K RAM versions, this signal is always configured as address line A14. Refer to
45
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A15 /
CLK_SEL_1
For 64K RAM versions, this signal is always configured as address line A15 (MSB).
Refer to the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic 1, this signal operates as
address line A15.
CLK_SEL_1. In this case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select
the Mark3 clock frequency, as follows:
CLK_SEL_1 CLK_SEL_0 Clock Frequency
0 0 10 MHz
0 1 20 MHz
1 0 12 MHz
1 1 16 MHz
A14 /
CLK_SEL_0
the description of A11-A0 below.
A14.
For 4K RAM versions, if UPADDREN is connected to logic 0, then this signal oper-ates
as CLK_SEL_0. In this case, CLK_SEL_1 and CLK_SEL_0 are used to select the
Mark3 clock frequency, as defined in the description for A15/CLK_SEL1 above.
SIGNAL NAME
DESCRIPTION
BU-64743XX
BU-64843XX
BU-64863XX
PIN
4K RAM
(BU-64743XX
BU-64843XX)
64K RAM
(BU-64863XX)
16-bit bi-directional data bus.This bus interfaces the host processor to the Mini-ACE Mark3's internal regis-ters
and internal RAM. In addition, in transparent mode, this bus allows data transfers to take place
between the internal protocol/memory management logic and up to 64K x 16 of external RAM. Most of the
time, the outputs for D15 through D0 are in the high impedance state. They drive outward in the buffered or
transparent mode when the host CPU reads the internal RAM or registers.
Also, in the transparent mode, D15-D0 will drive outward (towards the host) when the protocol/management
logic is accessing (either reading or writing) internal RAM, or writing to external RAM. In the transparent
mode, D15-D0 drives inward when the CPU writes internal registers or RAM, or when the protocol/memory
management logic reads external RAM.
D10 60
D9 57
D8 52
D7 53
D6 41
D5 49
D4 43
D3 48
D2 47
D1 42
D0 (LSB) 46
TABLE 50. DATA BUS
PIN

A13 /
+3.3V-LOGIC
BU-64743XX
BU-64843XX
BU-64863XX
46
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PIN
A11 1
Lower 12 bits of 16-bit bi-directional address bus.
In both the buffered and transparent modes, the host CPU accesses Mark3 registers and internal RAM by
means of A11 - A0 (4K versions). For 64K versions, A15-A12 are also used for this purpose.
In buffered mode, A12-A0 (or A15-A0) are inputs only. In the transparent mode, A12-A0 (or A15-A0) are
inputs during CPU accesses and become outputs, driving outward (towards the CPU) when the 1553 pro-tocol/
memory management logic accesses up to 64K words of external RAM.
In transparent mode, the address bus is driven outward only when the signal DTACK is low (indicating that
the Mark3 has control of the RAM interface bus) and IOEN is high, indicating a non-host access. Most of
the time, including immediately after power turn-on, A12-A0 (or A15-A0) will be in high impedance (input)
state.
A10 2
A09 75
A08 7
A07 12
A06 27
A05 74
A04 78
A03 13
A02 19
A01 33
A00 (LSB) 18
77 For 64K RAM versions, this signal is always configured as address line A13. Refer to
the description for A11-A0 below.
A13.
For 4K RAM versions, if UPADDREN is connected to logic 0, then this signal MUST
be connected to +3.3V-LOGIC (logic 1).
A13
A12 / RTBOOT 76 For 64K RAM versions, this signal is always configured as address line A12. Refer to
the description for A11-A0 below.
A12.
For 4K RAM versions, if UPADDREN is connected to logic 0, then this signal func-tions
as RTBOOT. If RTBOOT is connected to logic 0, the Mark3 will initialize in RT
mode with the Busy status word bit set following power turn-on. If RTBOOT is hard-wired
to logic 1, the Mark3 will initialize in either Idle mode (for an RT-only part), or in
BC mode (for a BC/RT/MT part).
A12
TABLE 51. PROCESSOR ADDRESS BUS (CONT.)
SIGNAL NAME
DESCRIPTION
BU-64743XX
BU-64843XX
BU-64863XX
PIN
4K RAM
(BU-64743XX
BU-64843XX)
64K RAM
(BU-64863XX)

TABLE 52. PROCESSOR INTERFACE CONTROL
47
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SELECT (I) 66 Device Select.
Generally connected to a CPU address decoder output to select the Mark3 for a transfer to/from either
RAM or register.
STRBD (I) 68 Strobe Data.
Used in conjunction with SELECT to initiate and control the data transfer cycle between the host processor
and the Mark3. STRBD must be asserted low through the full duration of the transfer cycle.
RD / WR (I) 71 Read/Write.
For host processor access, RD/WR selects between reading and writing. In the 16-bit buffered mode, if
POL_SEL is logic 0, then RD/WR should be low (logic 0) for read accesses and high (logic 1) for write
accesses. If POL_SEL is logic 1, or the interface is configured for a mode other than 16-bit buffered
mode, then RD/WR is high (logic 1) for read accesses and low (logic 0) for write accesses.
ADDR_LAT(I) /
MEMOE (O)
20 Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0, SELECT, MEM/REG,
and MSB/LSB (for 8-bit mode only) in latched mode (when low) or transparent mode (when high). That is,
the Mark3's internal transparent latches will track the values on A15-A0, SELECT, MEM/REG, and
MSB/LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus, ADDR_LAT should be
hardwired to logic 1. For interfacing to processors with a multiplexed address/data bus, ADDR_LAT
should be connected to a signal that indicates a valid address when ADDR_LAT is logic 1.
In transparent mode, MEMOE output signal is used to enable data outputs for external RAM read cycles
(normally connected to the OE input signal on external RAM chips).
ZEROWAIT (I) /
MEMWR (O)
28 Memory Write or Zero Wait.
In buffered mode, input signal (ZEROWAIT) used to select between the zero wait mode (ZEROWAIT = 0)
and the non-zero wait mode (ZEROWAIT = 1).
In transparent mode, active low output signal (MEMWR) asserted low during memory write transfers to
strobe data into external RAM (normally connected to the WR input signal on external RAM chips).
16 / 8 (I) /
DTREQ (O)
29 Data Transfer Request or Data Bus Select.
In buffered mode, input signal 16/8 used to select between the 16 bit data transfer mode (16/8*= 1) and
the 8-bit data transfer mode (16/8 = 0).
In transparent mode (16-bit only), active low level output signal DTREQ used to request access to the
processor/RAM interface bus (address and data buses).
MSB / LSB (I) /
DTGRT (I)
72 Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently being transferred
(MSB or LSB). The logic sense of MSB/LSB is controlled by the POL_SEL input. MSB/LSB is not used in
the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the DTREQ output to indi-cate
that control of the external processor/RAM bus has been transferred from the host processor to the
Mark3.
BU-64743XX
BU-64843XX
BU-64863XX
PIN

TABLE 52. PROCESSOR INTERFACE CONTROL (CONT.)
48
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POL_SEL (I) /
DTACK (O)
35 Data Transfer Acknowledge or Polarity Select.
In 16-bit buffered mode, if POL_SEL is connected to logic 1, RD/WR should be asserted high (logic 1)
for a read operation and low (logic 0) for a write operation. In 16-bit buffered mode, if POL_SEL is con-nected
to logic 0, RD/WR should be asserted low (logic 0) for a read operation and high (logic 1) for a
write operation.
In 8-bit buffered mode (TRANSPARENT/ BUFFERED = 0 and 16/8 = 0), POL_SEL input signal used to
control the logic sense of the MSB/LSB signal. If POL_SEL is connected to logic 0, MSB/LSB should be
asserted low (logic 0) to indicate the transfer of the least significant byte and high (logic 1) to indicate
the transfer of the most significant byte. If POL_SEL is connected to logic 1, MSB/LSB should be asserted
high (logic 1) to indicate the transfer of the least significant byte and low (logic 0) to indicate the transfer
of the most significant byte.
In transparent mode, active low output signal (DTACK) used to indicate acceptance of the processor/RAM
interface bus in response to a data transfer grant (DTGRT). Mark3 RAM transfers over A15-A0 and D15-D0
will be framed by the time that DTACK is asserted low.
TRIG_SEL (I) /
MEMENA_IN (I)
34 Memory Enable or Trigger Select input.
In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which byte pairs are transferred
to or from the Mark3 by the host processor. In the 8-bit buffered mode, TRIG_SEL should be asserted high
(logic 1) if the byte order for both read operations and write operations is MSB followed by LSB. TRIG_SEL
should be asserted low (logic 0) if the byte order for both read operations and write operations is LSB fol-lowed
by MSB.
This signal has no operation in the 16-bit buffered mode (it does not need to be connected).
In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS) input to the Mark3's inter-nal
shared RAM. If only internal RAM is used, should be connected directly to the output of a gate that is
OR'ing the DTACK and IOEN output signals.
MEM / REG(I) 6 Memory/Register.
Generally connected to either a CPU address line or address decoder output. Selects between memory
access (MEM/REG = 1) or register access (MEM/REG = 0).
TRANSPARENT/
BUFFERED (I)
61 Used to select between the buffered mode (when strapped to logic 0) and transparent/DMA mode (when
strapped to logic 1) for the host processor interface.
SSFLAG (I) /
EXT_TRIG(I)
37 Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input.
In RT mode, if this input is asserted low, the Subsystem Flag bit will be set in the Mark3's RT Status Word.
If the SSFLAG input is logic 0 while bit 8 of Configuration Register #1 has been programmed to logic 1
(cleared), the Subsystem Flag RT Status Word bit will become logic 1, but bit 8 of Configuration Register
#1, SUBSYSTEM FLAG, will return logic 1 when read. That is, the sense on the SSFLAG* input has no
effect on the SUBSYSTEM FLAG register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC mode, if the exter-nal
BC Start option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will
issue a BC Start command, starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the Mark3
BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to
high transition on this input will initiate a monitor start.
This input has no effect in Message Monitor mode.
BU-64743XX
BU-64843XX
BU-64863XX
PIN

TABLE 52. PROCESSOR INTERFACE CONTROL (CONT.)
READYD (O) 62 Handshake output to host processor.
For a nonzero wait state read access, READYD is asserted at the end of a host transfer cycle to indicate that
data is available to be read on D15 through D0 when asserted (low). For a nonzero wait state write cycle,
READYD is asserted at the end of the cycle to indicate that data has been transferred to a register or RAM
location. For both nonzero wait reads and writes, the host must assert STRBD low until READYD is asserted
low.
In the (buffered) zero wait state mode, this output is normally logic 1, indicating that the Mark3 is in a state
ready to accept a subsequent host transfer cycle. In zero wait mode, READYD will transition from high to low
during (or just after) a host transfer cycle, when the Mark3 initiates its internal transfer to or from registers or
internal RAM. When the Mark3 completes its internal transfer, READYD returns to logic 1, indicating it is
ready for the host to initiate a subsequent transfer cycle.
TABLE 53. RT ADDRESS
This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the RT to respond to non-broad-cast
commands. That is, there must be an odd number of logic 1s from among RTAD-4-RTAD0 and RTADP.
49
RTADP (I) 44 Remote Terminal Address Parity.
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IOEN(O) 64 I/O Enable.
Tri-state control for external address and data buffers. Generally not used in buffered mode. When low, indi-cates
that the Mark3 is currently performing a host access to an internal register, or internal (for transparent
mode) external RAM. In transparent mode, IOEN (low) should be used to enable external address and data
bus tri-state buffers.
BU-64743XX
BU-64843XX
BU-64863XX
PIN
RTAD4 (MSB) (I) 40 RT Address input.
If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic 0 (default), then the
Mark3's RT address is provided by means of these 5 input signals. In addition, if RT ADDRESS SOURCE is
logic 0, the source of RT address parity is RTADP.
There are many methods for using these input signals for designating the Mark3's RT address. For details,
refer to the description of RT_AD_LAT.
If RT ADDRESS SOURCE is programmed to logic 1, then the Mark3's source for its RT address and parity is
under software control, via data lines D5-D0. In this case, the RTAD4-RTAD0 and RTADP signals are not used.
RTAD3 (I) 39
RTAD2 (I) 24
RTAD1 (I) 45
RTAD0 (LSB) (I) 38
RT_AD_LAT (I) 36 RT Address Latch.
Input signal used to control the Mark3's internal RT address latch. If RT_AD_LAT is connected to logic 0, then
the Mark3 RT is configured to accept a hardwired (transparent) RT address from RTAD4-RTAD) and RTADP.
If RT_AD_LAT is initially logic 0, and then transitions to logic 1, the values presented on RTAD4-RTAD0
and RTADP will be latched internally on the rising edge of RT_AD_LAT.
If RT_AD_LAT is connected to logic 1, then the Mark3's RT address is latchable under host processor con-trol.
In this case, there are two possibilities: (1) If bit 5 of Configuration Register #6, RT ADDRESS SOURCE,
is programmed to logic 0 (default), then the source of the RT Address is the RTAD4-RTAD0 and RTADP
input signals. (2) If RT ADDRESS SOURCE is programmed to logic 1, then the source of the RT Address is
the lower 6 bits of the processor data bus, D5-D1 (for RTAD4-0) and D0 (for RTADP).
In either of these two cases (with RT_AD_LAT = 1), the processor will cause the RT address to be latched
by: (1) Writing bit 15 of Configuration Register #3, ENHANCED MODE ENABLE, to logic 1. (2) Writing bit 3
of Configuration Register #4, LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to logic 1. (3)
Writing to Configuration Register #5. In the case of RT ADDRESS SOURCE = 1, then the values of RT
address and RT address parity must be written to the lower 6 bits of Configuration Register #5, via D5-D0. In
the case where RT ADDRESS SOURCE = 0, the bit values presented on D5-D0 become don't care.
BU-64743XX
BU-64843XX
BU-64863XX
PIN

64K RAM
(BU-
64863X0)
SLEEPIN (I) UPADDREN For 64K RAM versions with internal transceivers, this signal is always configured as SLEEPIN.
This signal is used to control the transceiver sleep (power-down) circuitry. For these
versions of Mark3 if SLEEPIN is connected to logic 0, the transceivers are fully pow-ered
and operate normally. If SLEEPIN is connected to logic 1, the transceivers are in
sleep mode (dormant, low-power mode) of operation and are NOT operational.
For 4K RAM versions, this signal is always configured as UPADDREN.
This signal is used to control the function of the upper 4 address inputs (A15-A12). For
these versions of Mark3 if UPADDREN is connected to logic 1, then these four signals
operate as address lines A15-A12. If UPADDREN is connected to logic 0, then A15
and A14 function as CLK_SEL_1 and CLK_SEL_0 respectively; A13 MUST be con-nected
50
INCMD (O) /
MCRST (O)
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BU-64743/64843/64863
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to +3.3V-LOGIC; and A12 functions as RTBOOT.
For 64K RAM transceiverless versions, this signal is always a No Connect (NC).
14
INT (O) Interrupt Request output.
If the LEVEL/PULSE interrupt bit (bit 3) of Configuration Register #2 is logic 0, a neg-ative
pulse of approximately 500ns in width is output on INT to signal an interrupt
request.
If LEVEL/PULSE is high, a low level interrupt request output will be asserted on INT.
The level interrupt will be cleared (high) after either: (1) The processor writes a value of
logic 1 to INTERRUPT RESET, bit 2 of the Start/Reset Register; or (2) If bit 4 of
Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is logic 1 then it will
only be necessary to read the Interrupt Status Register (#1 and/or #2) that is request-ing
an interrupt enabled by the corresponding Interrupt Mask Register. However, for the
case where both Interrupt Status Register #1 and Interrupt Status Register #2 have bits
set reflecting interrupt events, it will be necessary to read both interrupt status registers
in order to clear INT.
63
CLOCK_IN (I) 26 20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
TX_INH_A (I) Transmitter inhibit inputs for Channel A and Channel B, MIL-STD-1553 transmitters.
For normal operation, these inputs should be connected to logic 0. To force a shut-down
of Channel A and/or Channel B, a value of logic 1 should be applied to the
respective TX_INH input.
65
TX_INH_B (I) 67
Master Clear.
Negative true Reset input, normally asserted low following power turn-on.
MSTCLR(I) 25
Time Tag Clock.
External clock that may be used to increment the Time Tag Register. This option is
selected by setting Bits 7,8 and 9 of Configuration Register # 2 to Logic 1.
TAG_CLK (I) 23
In-command or Mode Code Reset.
The function of this pin is controlled by bit 0 of Configuration Register #7, MODE CODE
RESET/INCMD SELECT.
If this register bit is logic 0 (default), INCMD will be active on this pin. For BC, RT, or
Selective Message Monitor modes, INCMD is asserted low whenever a message is
being processed by the Mark3. In Word Monitor mode, INCMD will be asserted low for
as long as the monitor is online.
For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic 1,
MCRST will be active. In this case, MCRST will be asserted low for two clock cycles fol-lowing
receipt of a Reset remote terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic 1, this sig-nal
is inoperative; i.e., in this case, it will always output a value of logic 1.
32
TABLE 54. MISCELLANEOUS
SIGNAL NAME
DESCRIPTION
BU-64743XX
BU-64843XX
BU-64863XX
PIN
4K RAM
(BU-64743XX
BU-64843XX)
NC
64K RAM
(BU-64863X8
BU-64863X9)

51
BU-64743XX
BU-64843XX
BU-64863XX
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NC
4
No User Connections to these pins allowed.
8
9
11
16
21
TABLE 55. NO USER CONNECTIONS
PIN

TABLE 56. MINI-ACE MARK3 BU-64XX3X8/9 VERSIONS PINOUTS
35
36
37 SSFLAG/EXT_TRIG 77 AD13
38 RTAD0 78 AD04
39 RTAD3 79 GND_XCVR
40 RTAD4 80 AD14
52
8
9
10
11 DO NOT CONNECT - FACTORY TEST POINT
16
17
18
19 AD02
20 ADDR_LAT/MEMOE
21 DO NOT CONNECT - FACTORY TEST POINT
22
23
24
25 MSTCLR
26 CLOCK_IN
27
28
29 16/8/DTREQ
30 3.3V_LOGIC
31
32
33 AD01
34 TRIG_SEL/MEMENA_IN
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46
DB00
47 DB02
48
GND_LOGIC
54
DB13
55 DB12
56
58 DB11
59
DB15
60
DB10
61 TRANS/BUFF
62 READYD
INT
IOEN
SELECT
66
67 TX_INH_B
68
STRBD
69 3.3V_LOGIC
70
71 RD/WR
72 MSB/LSB/DTGRT
73
AD15
74
AD05
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PIN
41
DB06
42
DB08
43
3.3V_LOGIC
44
DB05
45
DB03
49
RTAD1
50
RTADP
51
FUNCTION
DB04
52
DB01
DB09
53
DB14
57
DB07
TX_INH_A
63
64
65
GND_LOGIC
75 AD09
76 AD12
1 AD11
AD10
TX/RX_A
PIN
DO NOT CONNECT - FACTORY TEST POINT
2
FUNCTION
3
4
5 TX/RX_A
6 MEM/REG
7 AD08
3.3V_XCVR
12 AD07
13 AD03
14 SLEEPIN/UPADDREN
15 TX/RX_B
TX/RX_B
AD00
GND_XCVR
TAG_CLK
RTAD2
AD06
ZEROWAIT/MEMWR
GND_LOGIC
INCMD/MCRST
POL_SEL/DTACK
RT_AD_LAT

TABLE 57. MINI-ACE MARK3 BU-64XX3X0 (TRANSCEIVERLESS) VERSION PINOUTS
35
36
37 SSFLAG/EXT_TRIG 77 AD13
38 RTAD0 78 AD04
39 RTAD3 79 GND_LOGIC
40 RTAD4 80 AD14
53
8
9
10
11 TXINH_A_OUT
16
17
18
19 AD02
20 ADDR_LAT/MEMOE
21 RXDATA_B
22
23
24
25 MSTCLR
26 CLOCK_IN
27
28
29 16/8/DTREQ
30 3.3V_LOGIC
31
32
33 AD01
34 TRIG_SEL/MEMENA_IN
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46
DB00
47 DB02
48
GND_LOGIC
54
DB13
55 DB12
56
58 DB11
59
DB15
60
DB10
61 TRANS/BUFF
62 READYD
INT
IOEN
SELECT
66
67 TX_INH_B
68
STRBD
69 3.3V_LOGIC
70
71 RD/WR
72 MSB/LSB/DTGRT
73
AD15
74
AD05
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PIN
41
DB06
42
DB08
43
3.3V_LOGIC
44
DB05
45
DB03
49
RTAD1
50
RTADP
51
FUNCTION
DB04
52
DB01
DB09
53
DB14
57
DB07
TX_INH_A
63
64
65
GND_LOGIC
75 AD09
76 AD12
1 AD11
AD10
TXDATA_A
PIN
RXDATA_A *
2
FUNCTION
3
4
5 TXDATA_A
6 MEM/REG
7 AD08
RXDATA_A
TXINH_B_OUT
+3.3V_LOGIC
12 AD07
13 AD03
14 UPADDREN/NC
15 TXDATA_B
RXDATA_B *
TXDATA_B
AD00
GND_LOGIC
TAG_CLK
RTAD2
AD06
ZEROWAIT/MEMWR
GND_LOGIC
INCMD/MCRST
POL_SEL/DTACK
RT_AD_LAT
* NOTE: Standard transceiverless parts have their receiver inputs internally strapped for single-ended operation. The RXDATAx pins are connected to inputs that
are not enabled.

0.890 MAX
(22.606)
19 EQUAL SPACES
0.760 (19.304)
(TOL. NON-CUMM.)
TOP VIEW
INDEX DENOTES
PIN NO. 1
0.910 MAX.
(23.114)
SIDE VIEW
54
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19 EQUAL SPACES
0.760 (19.304)
(TOL. NON-CUMM.)
BU-64743/64843/64863
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1
Notes:
1) Dimensions are in inches (mm).
20
21
60 41
61
80
PIN 1 DENOTED BY
INDEX MARK
PIN NUMBERS FOR
REFERENCE ONLY
0.040 TYP.
(1.016)
0.015 TYP.
(0.381)
0.040 TYP.
(1.016)
40
0.890 MAX
(22.606)
R 0.012 TYP
(R 0.305)
0.006 +0.010
- 0.004
+0.254
(0.152 - 0 .1 0 2 )
1.020 MAX.
(25.908)
1.130 MAX.
(28.702)
0.130 MAX.
(3.302)
0.008 MAX.
(0.2032)
0.055 MAX.
(1.397)
0.055
(1.397)
1.130 MAX
(28.702)
FIGURE 16. MECHANICAL OUTLINE DRAWING FOR MINI-ACE MARK3 80-PIN GULL WING PACKAGE

0.130
(3.302)
INDEX DENOTES
PIN NO. 1
FIGURE 17. MECHANICAL OUTLINE DRAWING FOR MINI-ACE MARK3 80-PIN FLAT PACKAGE
55
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1
Notes:
1) Dimensions are in inches (mm).
0.890 MAX
(22.606)
19 EQUAL SPACES
0.760 (19.304)
(TOL. NON-CUMM.)
TOP VIEW
SIDE VIEW
20
21
60 41
61
80
PIN NUMBERS FOR
REFERENCE ONLY
0.880
(23.352)
0.040 TYP.
(1.016)
0.015 TYP.
(0.381)
40
1.880 MAX
(47.75)
0.200 (05.08)
2.360 MAX
(59.94)
0.500 TYP
(12.70)
0.050 (1.27)
0.040 (1.016)
0.008 (0.2032)
0.025 (0.635)

ORDERING INFORMATION FOR MINI-ACE MARK3
BU-64XX3XX-XXXX
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and Pre-Cap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, Pre-Cap Source and 100% Pull Test
Blank = None of the Above
STANDARD DDC PROCESSING
MIL-STD-883
METHOD(S) CONDITION(S)
TEST
INSPECTION 2009, 2010, 2017, and 2032 —
SEAL 1014 A and C
TEMPERATURE CYCLE 1010 C
CONSTANT ACCELERATION 2001 A
56
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BURN-IN 1015, Table 1 —
Test Criteria:
0 = Standard Testing
2 = MIL-STD-1760 Amplitude Compliant (not available with Voltage/Transceiver Options 0 “Transceiverless or
9 “McAir compatible”)
Process Requirements:
0 = Standard DDC practices, no Burn-In
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (see table below)
Temperature Range**/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
6 = Custom Part (Reserved)
7 = Custom Part (Reserved)
8 = 0°C to +70°C with Variables Test Data
Voltage/Transceiver Option:
0 = Transceiverless
8 = +3.3 Volts rise/fall times = 100 to 300 ns (-1553B)
9 = +3.3 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible. Not available with
Test Criteria option 2 “MIL-STD-1760 Amplitude Compliant”)
Package Type:
F = 80-Lead Flat Pack
G = 80-Lead “Gull Wing” (Formed Lead)
Logic / RAM Voltage
3 = 3.3 Volt
Product Type:
BU-6474 = RT only with 4K RAM
BU-6484 = BC /RT / MT with 4K x 16 RAM
BU-6486 = BC /RT / MT with 64K x 17 RAM
* Standard DDC processing with burn-in and full temperature test. See table below.
** Temperature Range applies to case temperature.

57
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NOTES:

58
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NOTES:

59
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NOTES:

® U
REGISTEREDFIRM
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
Please visit our web site at www.ddc-web.com for the latest information.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7234
Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358
Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610
West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
Ireland - Tel: +353-21-341065, Fax: +353-21-341568
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
C-03/03-300 60 PRINTED IN THE U.S.A.

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