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Bus Arbitration Techniques in Computer Organization
 Single-bus
Figure 1.3. Single-bus structure.
Memory
Input Output Processor
 There are many ways to connect different parts
inside a computer together.
 A group of lines that serves as a connecting
path for several devices is called a bus.
 Address/data/control
Bus Arbitration Techniques in Computer Organization
 Reasonably efficient architecture but begins to
break down as higher and higher performance is
seen in I/O devices.
 A common approach adopted by industry is to
build a high speed bus closely integrated with
the rest of the system.
 It require only a bridge between the processor’s
bus and high speed bus.
Bus Arbitration Techniques in Computer Organization
 The advantage of this arrangement is that the
high speed bus brings high-demand devices
into closer integration with the processor and
at the same time, is independent of the
processor.
 Changes in processor architecture do not affect
the high speed bus and vice-versa
 In a computer system, there may be more than
one bus masters such as processor, DMA
controller, etc, which share the system bus.
 When current master relinquishes control of
the bus, another bus master can acquire the
control of the bus.
 Bus Arbitration is the process by which the next
device to become the bus master is selected
and bus mastership is transferred to it.
 There are two approaches to bus arbitration:
1. Centralized bus arbitration, and
2. Distributed bus arbitration
 A single bus arbiter performs the required
arbitration.
 The bus arbiter may be the processor or a
separate controller connected to the bus.
 Three different arbiter schemes using
centralized arbitration:
1. Daisy Chaining
2. Polling Method
3. Independent Priority
 A simple and cheaper method for a centralized
bus arbitration process.
 All masters make use of the same line for bus
request.
 In response, the controller sends a bus grant if
the bus is free.
 The bus grant serially propagates through each
master until it encounters the first one that is
requesting the access to the bus.
Bus Arbitration Techniques in Computer Organization
 This master then blocks the propagation of the
bus grant signal, activates the busy line and
gains the control of the bus.
Advantages:
 Simple and cheaper method.
 Requires the least number of lines which is
independent of the number of masters in the
system.
Disadvantages:
 The propagation delay is more which makes
arbitration slow and hence limits the number
of masters in the system.
 The priority of the master is fixed by its physical
location.
 Failure of any one master causes the whole
system to fail.
Bus Request
Bus Busy
Module Address
 In this method the controller is used to
generate the addresses for the masters.
 Number of address lines required depends on
the number of masters connected in the
system.
 In response to a bus request, controller
generates a sequence of master addresses.
When the requesting master recognizes its
address, it activates the busy line and begins to
use the bus.
Advantages:
 The priority can be changed by altering the
polling sequence stored in the controller.
 If one module fails, entire system does not fail.
 Each master has a separate pair of bus request
and bus grant lines and each pair has a priority
assigned to it.
 The built-in priority decoder within the controller
selects the highest priority request and asserts the
corresponding bus grant signal.
Advantage:
Due to separate pairs of bus request and bus
grant signals, arbitration is fast and is independent
of the number of masters in the system.
Bus
request
Bus
Grant1
Bus Grant2
Bus Grant3
Bus Busy
Disadvantage:
It requires more bus request and bus grant
signals ( 2*n signals for n modules).
 In Distributed arbitration, all devices participate in the
selection of next bus master.
 Each device in the bus is assigned a 4-bit identification
number.
 Number of bits used for identification number actually
depends on the number of devices connected on the
bus.
 When one or more devices request for the control of
the bus, they assert the Start-Arbitration signal and
place their 4-bit ID numbers on arbitration lines,
ARB0 through ARB3.
 All four lines are open collector therefore, more
than one devices can place their 4-bit ID
number to indicate that they need the control
of bus.
 If one device puts 1 on the bus line and
another puts 0 on the same bus line, the bus
line status will be 0.
 In this scheme, the device having the highest
ID number has the highest priority.
 When two or more devices place their ID
number on bus line then it is necessary to
identify the highest ID number from the status
of bus line.
 The connection performs an OR operation in
which logic 1 wins.
Bus Arbitration Techniques in Computer Organization
 Assume that two devices, A and B, having ID
numbers 5 and 6 respectively, are requesting
the use of the bus. Device A transmits the
pattern 0101, while B transmits 0110.
 The code seen by both the devices is 0111.
Each device compares the pattern on the
arbitration lines to its own ID, starting from the
most significant bit. If it detects a difference at
any bit position, it disables its drivers at that bit
position and for all lower order bits.
 Advantages:
Offers higher reliability because operation of
the bus is not dependent on any single device.

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Bus Arbitration Techniques in Computer Organization

  • 2.  Single-bus Figure 1.3. Single-bus structure. Memory Input Output Processor
  • 3.  There are many ways to connect different parts inside a computer together.  A group of lines that serves as a connecting path for several devices is called a bus.  Address/data/control
  • 5.  Reasonably efficient architecture but begins to break down as higher and higher performance is seen in I/O devices.  A common approach adopted by industry is to build a high speed bus closely integrated with the rest of the system.  It require only a bridge between the processor’s bus and high speed bus.
  • 7.  The advantage of this arrangement is that the high speed bus brings high-demand devices into closer integration with the processor and at the same time, is independent of the processor.  Changes in processor architecture do not affect the high speed bus and vice-versa
  • 8.  In a computer system, there may be more than one bus masters such as processor, DMA controller, etc, which share the system bus.  When current master relinquishes control of the bus, another bus master can acquire the control of the bus.  Bus Arbitration is the process by which the next device to become the bus master is selected and bus mastership is transferred to it.
  • 9.  There are two approaches to bus arbitration: 1. Centralized bus arbitration, and 2. Distributed bus arbitration
  • 10.  A single bus arbiter performs the required arbitration.  The bus arbiter may be the processor or a separate controller connected to the bus.  Three different arbiter schemes using centralized arbitration: 1. Daisy Chaining 2. Polling Method 3. Independent Priority
  • 11.  A simple and cheaper method for a centralized bus arbitration process.  All masters make use of the same line for bus request.  In response, the controller sends a bus grant if the bus is free.  The bus grant serially propagates through each master until it encounters the first one that is requesting the access to the bus.
  • 13.  This master then blocks the propagation of the bus grant signal, activates the busy line and gains the control of the bus. Advantages:  Simple and cheaper method.  Requires the least number of lines which is independent of the number of masters in the system.
  • 14. Disadvantages:  The propagation delay is more which makes arbitration slow and hence limits the number of masters in the system.  The priority of the master is fixed by its physical location.  Failure of any one master causes the whole system to fail.
  • 16.  In this method the controller is used to generate the addresses for the masters.  Number of address lines required depends on the number of masters connected in the system.  In response to a bus request, controller generates a sequence of master addresses. When the requesting master recognizes its address, it activates the busy line and begins to use the bus.
  • 17. Advantages:  The priority can be changed by altering the polling sequence stored in the controller.  If one module fails, entire system does not fail.
  • 18.  Each master has a separate pair of bus request and bus grant lines and each pair has a priority assigned to it.  The built-in priority decoder within the controller selects the highest priority request and asserts the corresponding bus grant signal. Advantage: Due to separate pairs of bus request and bus grant signals, arbitration is fast and is independent of the number of masters in the system.
  • 20. Disadvantage: It requires more bus request and bus grant signals ( 2*n signals for n modules).
  • 21.  In Distributed arbitration, all devices participate in the selection of next bus master.  Each device in the bus is assigned a 4-bit identification number.  Number of bits used for identification number actually depends on the number of devices connected on the bus.  When one or more devices request for the control of the bus, they assert the Start-Arbitration signal and place their 4-bit ID numbers on arbitration lines, ARB0 through ARB3.
  • 22.  All four lines are open collector therefore, more than one devices can place their 4-bit ID number to indicate that they need the control of bus.  If one device puts 1 on the bus line and another puts 0 on the same bus line, the bus line status will be 0.  In this scheme, the device having the highest ID number has the highest priority.
  • 23.  When two or more devices place their ID number on bus line then it is necessary to identify the highest ID number from the status of bus line.  The connection performs an OR operation in which logic 1 wins.
  • 25.  Assume that two devices, A and B, having ID numbers 5 and 6 respectively, are requesting the use of the bus. Device A transmits the pattern 0101, while B transmits 0110.  The code seen by both the devices is 0111. Each device compares the pattern on the arbitration lines to its own ID, starting from the most significant bit. If it detects a difference at any bit position, it disables its drivers at that bit position and for all lower order bits.
  • 26.  Advantages: Offers higher reliability because operation of the bus is not dependent on any single device.