Arbitration in computer organization

Editor's Notes

• #2: In a computer system, the various subsystems must be able to talk to one another. For example, the memory and processor need to communicate with each other. Similarly, the processor needs to communicate with the I/O devices. The most common way to do is to use a bus. A bus is a shared communication link that uses 1 set of wires to connect multiple subsystems. +1 = 6 min. (X:46)
• #3: The two major advantages of the bus organization are versatility and low cost. By versatility, we mean new devices can easily be added. Furthermore, if a device is designed according to a industry bus standard, it can be move between computer systems that use the same bus standard. The bus organization is a low cost solution because a single set of wires is shared in multiple ways. +1 = 7 min. (X:47)
• #4: The major disadvantage of the bus organization is that it creates a communication bottleneck. When I/O must pass through a single bus, the bandwidth of that bus can limit the maximum I/O throughput. The maximum bus speed is also largely limited by: (a) The length of the bus. (b) The number of I/O devices on the bus. (C) And the need to support a wide range of devices with a widely varying latencies and data transfer rates. +2 = 9 min. (Y:49)
• #5: A bus generally contains a set of control lines and a set of data lines. The control lines are used to signal requests and acknowledgments and to indicate what type of information is on the data lines. The data lines carry information between the source and the destination. This information may consists of data, addresses, or complex commands. A bus transaction includes tow parts: (a) sending the address and (b) then receiving or sending the data. +1 = 10 min (X:50)
• #6: The bus master is the one who starts the bus transaction by sending out the address. The slave is the one who responds to the master by either sending data to the master if the master asks for data. Or the slave may end up receiving data from the master if the master wants to send data. In most simple I/O operations, the processor will be the bus master but as I will show you later in today’s lecture, this is not always be the case. +1 = 11 min. (X:51)
• #7: Buses are traditionally classified as one of 3 types: processor memory buses, I/O buses, or backplane buses. The processor memory bus is usually design specific while the I/O and backplane buses are often standard buses. In general processor bus are short and high speed. It tries to match the memory system in order to maximize the memory-to-processor BW and is connected directly to the processor. I/O bus usually is lengthy and slow because it has to match a wide range of I/O devices and it usually connects to the processor-memory bus or backplane bus. Backplane bus receives its name because it was often built into the backplane of the computer--it is an interconnection structure within the chassis. It is designed to allow processors, memory, and I/O devices to coexist on a single bus so it has the cost advantage of having only one single bus for all components. +2 = 16 min. (X:56)
• #8: Here is an example showing a single bus, the backplane bus is used to provide communication between the processor and memory. As well as communication between I/O devices and memory. The advantage here is of course low cost. One disadvantage of this approach is that the bus with so many things attached to it will be lengthy and slow. Furthermore, the bus can become a major communication bottleneck if everybody wants to use the bus at the same time. The IBM PC is an example that uses only a backplane bus for all communication. +2 = 18 min. (X:58)
• #9: Right before the break, I showed you a system with one bus only. Here is an example using two buses where multiple I/O buses tap into the processor-memory bus via bus adaptors. The Processor-memory bus is used mainly for processor-memory traffic while the I/O buses are used to provide expansion slots for the I/O devices. The Apple Macintosh-II adopts this organization where the NuBus is used to connect processor, memory, and a few selected I/O devices together. The rest of the I/O devices reside on an industry standard bus, the SCCI Bus, which is connected to the NuBus via a bus adaptor. +2 = 25 min. (Y:05)
• #10: Finally, in a 3-bus system, a small number of backplane buses (in our example here, just 1) tap into the processor-memory bus. The processor-memory bus is used mainly for processor memory traffic while the I/O buses are connected to the backplane bus via bus adaptors. An advantage of this organization is that the loading on the processor-memory bus is greatly reduced because of the small number of taps into the high-speed processor-memory bus. +1 = 26 min. (Y:06)
• #12: There are substantial differences between the design requirements for the I/O buses and processor-memory buses and the backplane buses. Consequently, there are two different schemes for communication on the bus: synchronous and asynchronous. Synchronous bus includes a clock in the control lines and a fixed protocol for communication that is relative to the clock. Since the protocol is fixed and everything happens with respect to the clock, it involves very logic and can run very fast. Most processor-memory buses fall into this category. Synchronous buses have two major disadvantages: (1) every device on the bus must run at the same clock rate. (2) And if they are fast, they must be short to avoid clock skew problem. By definition, an asynchronous bus is not clocked so it can accommodate a wide range of devices at different clock rates and can be lengthened without worrying about clock skew. The draw back is that it can be slow and more complex because a handshaking protocol is needed to coordinate the transmission of data between the sender and receiver. +2 = 28 min. (Y:08)
• #13: Taking about trying to get onto the bus: how does a device get onto the bus anyway? If everybody tries to use the bus at the same time, chaos will result. Chaos is avoided by a maser-slave arrangement where only the bus master is allow to initiate and control bus requests. The slave has no control over the bus. It just responds to the master’s response. Pretty sad. In the simplest system, the processor is the one and ONLY one bus master and all bus requests must be controlled by the processor. The major drawback of this simple approach is that the processor needs to be involved in every bus transaction and can use up too many processor cycles. +2 = 35 min. (Y:15)
• #14: A more aggressive approach is to allow multiple potential bus masters in the system. With multiple potential bus masters, a mechanism is needed to decide which master gets to use the bus next. This decision process is called bus arbitration and this is how it works. A potential bus master (which can be a device or the processor) wanting to use the bus first asserts the bus request line and it cannot start using the bus until the request is granted. Once it finishes using the bus, it must tell the arbiter that it is done so the arbiter can allow other potential bus master to get onto the bus. All bus arbitration schemes try to balance two factors: bus priority and fairness. Priority is self explanatory. Fairness means even the device with the lowest priority should never be completely locked out from the bus. Bus arbitration schemes can be divided into four broad classes. In the fist one: (a) Each device wanting the bus places a code indicating its identity on the bus. (b) By examining the bus, the device can determine the highest priority device that has made a request and decide whether it can get on. In the second scheme, each device independently requests the bus and collision will result in garbage on the bus if multiple request occurs simultaneously. Each device will detect whether its request result in a collision and if it does, it will back off for an random period of time before trying again. The Ethernet you use for your workstation uses this scheme. We will talk about the 3rd and 4th schemes in the next two slides. +3 = 38 min. (Y:18)
• #15: The daisy chain arbitration scheme got its name from the structure for the grant line which chains through each device from the highest priority to the lowest priority. The higher priority device will pass the grant line to the lower priority device ONLY if it does not want it so priority is built into the scheme. The advantage of this scheme is simple. The disadvantages are: (a) It cannot assure fairness. A low priority device may be locked out indefinitely. (b) Also, the daisy chain grant line will limit the bus speed. +1 = 39 min. (Y:19)
• #16: The daisy chain arbitration scheme got its name from the structure for the grant line which chains through each device from the highest priority to the lowest priority. The higher priority device will pass the grant line to the lower priority device ONLY if it does not want it so priority is built into the scheme. The advantage of this scheme is simple. The disadvantages are: (a) It cannot assure fairness. A low priority device may be locked out indefinitely. (b) Also, the daisy chain grant line will limit the bus speed. +1 = 39 min. (Y:19)
• #17: The daisy chain arbitration scheme got its name from the structure for the grant line which chains through each device from the highest priority to the lowest priority. The higher priority device will pass the grant line to the lower priority device ONLY if it does not want it so priority is built into the scheme. The advantage of this scheme is simple. The disadvantages are: (a) It cannot assure fairness. A low priority device may be locked out indefinitely. (b) Also, the daisy chain grant line will limit the bus speed. +1 = 39 min. (Y:19)
• #18: The daisy chain arbitration scheme got its name from the structure for the grant line which chains through each device from the highest priority to the lowest priority. The higher priority device will pass the grant line to the lower priority device ONLY if it does not want it so priority is built into the scheme. The advantage of this scheme is simple. The disadvantages are: (a) It cannot assure fairness. A low priority device may be locked out indefinitely. (b) Also, the daisy chain grant line will limit the bus speed. +1 = 39 min. (Y:19)