Modes of transfer - Computer Organization & Architecture - Nithiyapriya Pasavaraj
Download as PPTX, PDF3 likes3,284 views
The document discusses three modes of data transfer between the central processing unit (CPU) and input/output (I/O) devices: programmed I/O, interrupt-initiated I/O, and direct memory access (DMA). Programmed I/O requires the CPU to continuously monitor the I/O device for data readiness, slowing performance. Interrupt-initiated I/O allows the I/O device to generate interrupts when ready, pausing the CPU to service transfers. DMA bypasses the CPU by allowing direct memory access between I/O devices and memory, speeding large data transfers.
Modes of transfer - Computer Organization & Architecture - Nithiyapriya Pasavaraj
- 1. Modes of Transfer Computer organization & Architecture By Nithiyapriya Pasavaraj
- 2. The Data transfer between the central unit and I/O devices can be handled in one of the possible three modes:: 1. Programmed I/O 2. Interrupt Initiated I/O 3. Direct Memory Access
- 3. Programmed I/O ● Programmed I/O instructions are the result of I/O instructions written in computer program. ● Each data item transfer is initiated by the instruction in the program. ● I/O instructions are needed to transfer data from & to a CPU a register & peripherals. ● Once a data transfer is initiated , the CPU is required to monitor the interface to see when a transfer can again be made. ● In the programmed I/O method, the CPU stays in a program loop until the I/O unit indicates that it is ready for data transfer.
- 4. Programmed I/O ● In the programmed I/O method, the I/O device does not have direct access to memory ● A transfer from an I/O device to memory requires the execution of several instructions by the CPU, including ■ an input instruction to transfer the data from the device to the CPU ■ a store instruction to transfer the data from the CPU to memory. ● The device transfer bytes of data one at a time as they are available.
- 5. Data transfer from I/O device to CPU Programmed IO - Example
- 6. ★ When a byte of data is available, the device places it in the I/O bus and enables its data valid line. ★ The interface accepts the byte into its data register and enables the data accepted line. ★ The interface sets a bit in the status register that we will refer to as an F or "flag" bit. The device can now disable the data valid line, but it will not transfer another byte until the data accepted line is disabled by the interface. ★ A program is written for the computer to check the flag in the status register to determine if a byte has been placed in the data register by the I/O device.& it is is done by reading the status register into a CPU register and checking the value of the flag bit. ■ If the flag is equal to 1, the CPU reads the data from the data register.& then the flag bit is cleared to 0 by either the CPU or the interface. ■ Once the flag is cleared, the interface disables the data accepted line and the device can then transfer the next data byte.
- 7. The Transfer of each byte requires 3 instructions(Steps). 1. Read the status register 2. Check the status of flag bit & go to step 1 , if it is not set (or) go to step 3 if it is set. 3. Read the data register.
- 8. The Transfer of each byte requires 3 instructions. 1. Read the status register 2. Check the status of flag bit & go to step 1 , if it is not set (or) go to step 3 if it is set. 3. Read the data register.
- 9. Disadvantage of Programmed I/O: ● The problem with programmed I/O is that it is time consuming , since it keeps the processor busy ● The processor, while waiting, must repeatedly interrogate the status of the I/O module. ● Performance of the entire system is severely degraded.
- 10. Interrupt - initiated I/O ★ In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates that it is ready for data transfer. This is time consuming process because it keeps the processor busy needlessly. ★ This problem can be overcome by using interrupt initiated I/O. ★ In Interrupt initiated IO, when the interface determines that the peripheral is ready for data transfer, it generates an interrupt. ★ After receiving the interrupt signal, the CPU stops the task which it is processing and service the I/O transfer and then returns back to its previous processing task.
- 11. ● The CPU responds to the interrupt signal by storing the return address from the program counter into a memory stack and then control branches to a service routine that processes the required I/O transfer. ● This can be done by two methods: ■ Vectored interrupt ■ Non-vectored interrupt ● Vectored Interrupt: In a vectored interrupt, the source that interrupts supplies the branch information to the computer. This information is called the interrupt vector. ● Non-vectored Interrupt: In a non vectored interrupt, the branch address is assigned to a fixed location in memory.
- 12. Priority Interrupt A priority interrupt is a system that establishes a priority over the various sources to determine which condition is to be serviced first when two or more requests arrive simultaneously.
- 14. Direct Memory Access ● The technique of Removing the CPU from the path of data transfer and letting the peripheral device to manage the memory buses directly to improve the speed of transfer ,is known as DMA. ● In this method , the interface transfer data to and from the memory through memory bus. ● The DMA controller manages to transfer data between peripherals and memory unit. ● In DMA , ■ when the CPU initiate the transfer, DMA request memory cycle through the memory bus. ■ When the request is granted by the memory controller, th DMA transfer the data directly to the memory. ● Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards and sound cards etc. It is also used for intra chip data transfer in multicore processors.
- 15. Thank you...