Data transfer techniques 8085
- 2. Need of Data Transfer Techniques In all process content applications, 𝜇p would like to communicate with different I/O devices for data transfers, i.e., transfer of data between circuitry external to the microprocessor and the processor itself. This transfer of data is in addition to transfers between the microprocessor and memory and is referred to as input/output or I/O. Data transfer may take place between microprocessor and memory, microprocessor and I/O devices and memory & I/O devices. Not much of the problems arise for the data communication between microprocessor and memory as same technology is used in the manufacturing of memory and microprocessor however problems arise due to mismatch of the speed of the I/O devices and the speed of microprocessor or memory. To overcome this problem of speed mismatch between the microprocessor and I/O devices we introduce data transfer schemes of 8085 microprocessor
- 4. Synchronous Mode Synchronous means “at the same time” i.e. the device which sends the data and the device which receives the data are synchronized with the same clock speed. This technique of data transfer can be employed when the speed of I/O devices and the speed of CPU are compatible. This technique can also be used when the speed characteristic of the I/O devices are known, so we can delay the data transfer for a fixed time. When the device is ready with the data it can indicate to 8085 on the READY pin.
- 5. Asynchronous Mode Asynchronous means “at regular interval”. In this method data transfer is not based on the predetermined timing pattern. This technique is suitable when timing characteristics of I/O devices doesn't match with the speed of microprocessor and are not known. In this mode the status of I/O devices i.e. whether the device is ready or not, is checked by the microprocessor before the data are transferred. The microprocessor initiates the I/O device to get ready by sending a REQUEST signal to the I/O device and then continuously checks the status of the I/O device till the I/O device become ready to transfer data. When the I/O device becomes ready it send the ACKNOWLEDGE signal to processor and then the processor executes the I/O instructions. This method of data transfer is also known as Handshaking mode of data transfer because some signals are exchanged between microprocessor and the I/O device before the actual transfer occurs.
- 6. Interrupt Driven I/O In the asynchronous mode of transfer, microprocessor is busy all the time in checking for the availability of data from the slower I/O devices. And it also busy in checking if I/O device is ready for the data transfer or not. In other words in this data transfer scheme, some of the microprocessor time is wasted in waiting while an I/O device is getting ready. To overcome this problem interrupt driven I/O data transfer introduced. In this interrupt driven I/O data transfer method the I/O device informs the microprocessor for the data transfer whenever the I/O device is ready. This is achieved by interrupting the microprocessor by using the interrupt pins of microprocessor.
- 7. Contd. In the beginning the microprocessor initiates data transfer by requesting the I/O device ‘to get ready’ and then continue executing its original program rather wasting its time by checking the status of I/O device. Whenever the device is ready to accept or supply data, it informs the processor through a control signal. This control signal known as interrupt (INTR) signal. In response to this interrupt signal, the microprocessor sends back an interrupt acknowledge signal to the I/O device Interrupts driven data transfer is better from asynchronous mode but it is still not very effective technique when data needs to be transferred in large amounts because it requires an interrupt for every character read or written. This leads us to an another approach called direct memory access(DMA) mode.
- 8. DMA Mode of Data Transfer Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or receive data directly to or from the main memory, bypassing the CPU to speed up memory operations. The process is managed by a chip known as a DMA controller (DMAC) DMA channels are used to communicate data between the peripheral device and the system memory. A DMA channel enables a device to transfer data without exposing the CPU to a work overload. Without the DMA channels, the CPU copies every piece of data using the peripheral bus from the I/O device which does not allow the microprocessor to perform other work until the operation is completed.
- 9. Contd. With DMA, the CPU can process other tasks while data transfer is being performed. The transfer of data is first initiated by the CPU. During the transfer of data between the DMA channel and I/O device, the CPU performs other tasks. When the data transfer is complete, the CPU receives an interrupt request from the DMA controller. For the data transfer using DMA process, a request to the microprocessor in form of HOLD signal, by the I/O device is sent. When microprocessor receipt of such request, the microprocessor relinquishes the address and data buses and informs the I/O devices of the situation by sending Acknowledge signal HLDA after completing the current machine cycle. The DMA controller then takes over the control of the buses of microprocessor and controls the data transfer between RAM and I/O device. When the data transfer is complete, DMA controller returns the control over the buses to the microprocessor by disabling the HOLD signal.
- 10. Modes of DMA Transfer The different DMA transfer modes are as follows: 1. Burst or block transfer DMA 2. Cycle steal or single byte transfer DMA. 3. Transparent or hidden DMA.
- 11. Burst or block transfer DMA It is the fastest DMA mode. In this two or more data bytes are transferred continuously i.e. entire block of data is transferred in one contiguous sequence. Processor is disconnected from system bus during DMA transfer. N number of machine cycles are adopted into the machine cycles of the processor where N is the number of bytes to be transferred. So once the DMA controller is granted access to the system bus by the CPU, it transfer all bytes of data in the data block before releasing control of the system buses back to the CPU. After receiving HLDA signal, DMA gains control of system bus and transfers one byte. After transferring one byte, it increments memory address, decrements counter and transfers next byte. In this way, it transfer all data bytes between memory and I/O devices. After transferring all data bytes, the DMA controller disables HOLD signal & enters into slave mode.
- 12. Cycle steal or single byte transfer DMA In this mode only one byte is transferred at a time. This is slower than burst DMA. In cycle stealing mode, after one byte of data transfer, the control of the system bus gives back to the CPU so after transfer one byte, it disables HOLD signal and enters into slave mode. Processor gains control of system bus and executes next machine cycle. If count is not zero and data is available then the DMA controller again sends HOLD signal to the processor and transfer next byte of data block. By continually obtaining and releasing the control of the system bus, the DMA controller essentially interleaves instructions and data transfers.
- 13. Transparent or Hidden DMA transfer Processor executes some states during which is floats the address and data buses. During this process, processor is isolated from the system bus. DMA transfers data between memory and I/O devices during these states. This operation is transparent to the processor. This is slowest DMA transfer. In this mode, the instruction execution speed of processor is not reduced. But, the transparent DMA requires logic to detect the states when the processor is floating the buses
- 14. Programmed I/O Mode of Data Transfer Programmable I/O is one of the I/O technique other than the interrupt-driven I/O and direct memory access (DMA), it was the most simple type of I/O technique for the exchanges of data or any types of communication between the processor and the external devices. The processor executes a program that gives it direct control of the I/O operation, including sensing device status, sending a read or write command, and transferring the data. When the processor issues a command to the I/O module, it must wait until the I/O operation is complete. If the processor is faster than the I/O module, this is wasteful of processor time.
- 15. Steps in Programmed I/O 1. The processor is executing a program and encounters an instruction relating to I/O operation. 2. The processor then executes that instruction by issuing a command to the appropriate I/O module. 3. The I/O module will perform the requested action based on the I/O command issued by the processor (READ/WRITE) and set the appropriate bits in the I/O status register. 4. The processor will periodically check the status of the I/O module until it find that the operation is complete.
- 16. Programmed I/O Mode Data Transfer
- 17. Serial Communication Serial communication transmits data one bit at a time, sequentially over a single communication link to a receiver where each bit has its clock pulse rate.. This method is used when data transfer rate is slow and data have to transmit over a long distances and also where the cost of cable and synchronization difficulties makes parallel communication impractical. Since the microprocessors process data in bit-parallel mode, the transmitter performs parallel-to-serial conversion, while the receiver performs serial-to- parallel conversion.
- 18. Parallel Transmission In Parallel Transmission, various bits are sent together simultaneously with a single clock pulse. It is a fast way to transmit as it uses many input/output lines for transferring the data. The basic difference between a parallel and a serial communication channel is the number of electrical conductors used at the physical layer to convey bits. Parallel communication implies more than one such conductor. For example, an 8-bit parallel channel will convey eight bits (or a byte) simultaneously, whereas a serial channel would convey those same bits sequentially, one at a time. If both channels operated at the same clock speed, the parallel channel would be eight times faster.
- 19. Contd. In order to transmit n bits, n wires or lines are used. Thus each bit has its own line. All n bits of one group are transmitted with each clock pulse from one device to another i.e. multiple bits are sent with each clock pulse. Parallel transmission is used for short distance communication.
- 20. Key Differences Between Serial And Parallel Transmission 1. Serial transmission requires a single line to communicate and transfer data whereas, parallel transmission requires multiple lines. 2. Serial transmission used for long distance communication whereas, the parallel transmission used for shorter distance. 3. Error and noise are least in serial as compared to parallel transmission. Since one bit follows another in Serial Transmission whereas, in Parallel Transmission multiple bits are sent together. 4. Parallel transmission is faster as the data is transmitted using multiples lines whereas, in Serial transmission data flows through a single wire. 5. Serial transmission cables are thinner, longer and economical in comparison with the Parallel Transmission cables. 6. Serial Transmission is reliable and straightforward whereas, Parallel Transmission is unreliable and complicated.