Bus System (part 2)
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The document discusses bus systems in computer architecture. It describes some problems that can occur with single bus systems, such as propagation delays and performance issues when aggregate data transfer approaches bus capacity. To overcome these problems, most systems use multiple buses. It then covers different bus types (dedicated, multiplexed), bus arbitration methods (centralized, distributed), bus timing (synchronous vs asynchronous), and examples of specific bus standards like PCI bus.
Bus System (part 2)
- 1. Organisasi dan Arsitektur Komputer Ajeng Savitri Puspaningrum, M.Kom Pertemuan 17
- 2. Bus System (part 2)
- 3. Learning bus interconnection Learning elements of bus
- 4. Single Bus Problems Lots of devices on one bus leads to: Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems
- 5. Traditional ISA (with cache)
- 7. Bus Types Dedicated Separate data & address lines Multiplexed Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages More complex control Ultimate performance
- 8. Bus Arbitration More than one module controlling the bus e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed
- 9. Centralised or Distributed Arbitration Centralised Single hardware device controlling bus access Bus Controller Arbiter May be part of CPU or separate Distributed Each module may claim the bus Control logic on all modules
- 10. Timing Co-ordination of events on bus Synchronous Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle All devices can read clock line Usually sync on leading edge Usually a single cycle for an event
- 11. PCI Bus Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines
- 12. PCI Bus Lines (required) Systems lines Including clock and reset Address & Data 32 time mux lines for address/data Interrupt & validate lines Interface Control Arbitration Not shared Direct connection to PCI bus arbiter Error lines
- 13. PCI Bus Lines (Optional) Interrupt lines Not shared Cache support 64-bit Bus Extension Additional 32 lines Time multiplexed 2 lines to enable devices to agree to use 64-bit transfer JTAG/Boundary Scan For testing procedures
- 14. PCI Commands Transaction between initiator (master) and target Master claims bus Determine type of transaction e.g. I/O read/write Address phase One or more data phases
- 15. Refference Stalling, William, Computer Organization and Architecture, 10th Edition, Pearson, 2015 Abdurohman, Maman, Organisasi dan Arsitektur Komputer revisi ke-4, Penerbit Informatika, 2017