How CPU’s and Memory Work

Running head: HOW CPU’S AND MEMORY WORK 1
How CPU’s and Memory Work
Larry Reid
Kaplan University
IT332-1 Principles of Information Systems Architecture

HOW CPU’S AND MEMORY WORK 2
How CPU’s and Memory Work
Today’s computer is comprised of very technologically advanced components. The main
components in a computer that have to do with data processing and speed are the Central
Processing Unit (CPU) and Random Access Memory (RAM). This article will explore the CPU,
multiprocessing, bus, cache, data movement instructions, RAM (memory), and address registers.
Throughout this paper please refer to the diagram on page 6 that displays a visual representation
of the CPU, memory, and bus architectures.
The CPU has been through many upgrades since its introduction to the commercial world
in 1971. A central processing conducts simple mathematical operations at hundreds of millions
times per second. The CPU is comprised of several components and a bus network that makes
everything work. A CPU’s main components are comprised of a Control Unit (CU) which
controls all operations within the CPU, the Clock is what the CU uses to control its speed of
operation and is connected directly to the CU and other components throughout the PC,
additionally the clock speed is what’s used to calculate the speed of the CPU in GHz. The
Arithmetic Logic Unit (ALU) is the calculator that conducts all arithmetic operations, the L
Cache 1, 2, and 3 is located within the CPU on the chip and provides really fast access to data
instructions and/or data addresses that are typically going to be needed soon or instructions that
are performed often (Hruska, 2016). Additionally, there are several registers throughout the CPU
such as the general registers, instruction register (IR), memory address register (MAR), memory
data register (MDR), interrupt register, and many more that are used to store data instructions or
addresses which provides the ALU and CU an even faster memory to utilize than L Cache
(Englander, 2014).

Address registers play a very important role in the operation of the CPU and memory.
The Memory Address Register (MAR) job is to send the address in its register to the address
decoder and along the address bus to main memory, the data at that address is then found and
pulled out by the MDR to send out along the data bus to be processed by the CU, lastly, the
MAR will receive and hold the address that is to be fetched next from the IR along the address
bus.
Modern memory which is Random access memory (RAM) is a fundamental necessity for
modern computer systems because it is what enables us to run programs due to the fast access to
large amounts of data and program instructions that are held during their operation, and memory
also enables the CPU to access its storage randomly instead of sequentially which is how the
CPU usually operates. The most used memory currently is Double Data Rate Dynamic RAM
(DDR DRAM) which there are currently four types, DDR, DDR2, DDR3, and DDR4, each step
up in DDR ram delivers a vast power savings, and double the processing speed and bandwidth of
its predecessor. Memory is made up millions of cells laid out in rows and columns that each hold
1 bit of data, each byte is written across a column through by the CPU sending an electrical
charge on the bus to a specified row (Murray, 2012). Additionally, the CPU uses its IR to get the
next set of instructions which occurs by the IR accessing the program counter (PC) in the CPU
which has the next instructions address, the IR passes the address to the MAR which then sends
it to the address decoder, then it finds the memory location and the bits are then read by the
MDR and sent back to the IR until the CU processes the data, all of which is supervised by the
memory management unit located in the CU (Tyson & Coustan, 2000).
The BUS is what’s used to send requests, addresses, and data to and from the CPU
through a data bus, address bus, control bus, system bus and several others. Within the CPU

every component is connected to an internal bus and/or connected to one of the other types of
bus to send and receive data. Each bus has its own purpose; the data bus is used to transport data
or instructions between several components in the CPU and memory. The address bus is used to
transfer address locations to the necessary components such as the MAR, memory, the IR, and
the CU. A control bus is used to communicate with devices through control signals, check their
status, allow devices to send control signals to the CPU, and transmission of interrupt signals to
the interrupt register. The internal bus is used to transfer data, addresses, and control signals
throughout the internal components (Techopedia, n.d.).
Above I have explained the workings of the CPU, its internal components, the bus
architecture, and memory architecture, now we will go over what multicore processing is and
how it works compared to single core and multi-processor. First, let’s lightly touch on what
multi-processing which is not the same as multicore processing. Multi-processor setups are
exactly how they sound, they require a motherboard with multiple processor slots and are not
near the efficiency or speed of multicore processors. Multicore processors have multiple
processors within the same die, which allows for transferring of data and communication
between CPU cores at a very fast rate. By implementing a multicore processor such as a quad
core CPU allows for you to run multiple processes at one time which is why we are able to
multitask on modern computers with this new architecture of CPU. Not only are we able to run
several programs at once, depending on the speed and a few other factors, we are able to process
large tasks, like video editing, in much less time since each one of the two, four, or eight CPU
cores complete one task at the same time meaning they can process 2, 4, or 8 instructions every
clock cycle, unlike a single core CPU that completes one instruction at a time as described
earlier.

Central processing unit architecture, memory architecture, and bus architecture has
improved dramatically throughout the years and new material and designs are constantly being
developed for employment of smaller, faster, and battery friendly components that will power
new electronic devices.

CPU Diagram:
Arythmetic Logic
Unit (ALU)
Control Unit
(CU)
Clock
Memory
111110101100011010001000
L1 Cache
MARMDR
Registers
Instruction
Register
Address Decoder
L2 Cache
I/O
Interface
Legend
Data BUS
Address BUS
Internal BUS
Control BUS
L3 Cache
L1 Cache
MDR- Memory Data Register
MAR- Memory Address Register
10101011
10010011
11100011
10001000
00011000
10010110
11111000
00111110
InteruptRegister
Address

Reference
Englander, Irv. (2014-01-21). The Architecture of Computer Hardware and System Software: An
Information Technology Approach, 5th Edition. [VitalSource Bookshelf Online].
Retrieved from https://kaplan.vitalsource.com/#/books/9781118803127/
Hruska, J (2016). How L1 and L2 CPU caches work, and why they’re an essential part of
modern chips. retrieved April 17 2016, from ExtremeTech Web Site:
http://www.extremetech.com/extreme/188776-how-l1-and-l2-cpu-caches-work-and-why-
theyre-an-essential-part-of-modern-chips
Murray, M (2012). DDR vs. DDR2 vs. DDR3: Types Of RAM Explained. retrieved April 17
2016, from PC Mag Web Site: http://www.pcmag.com/article2/0,2817,2400801,00.asp
Tyson, J & Coustan, D (2000). How RAM Works. retrieved April 17 2016, from How Stuff
Works Tech Web Site: http://computer.howstuffworks.com/ram.htm
Techopedia. (n.d.). Control Bus. retrieved April 18, 2016, from Techopedia Web Site:
https://www.techopedia.com/definition/303/control-bus

How CPU’s and Memory Work

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