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Cache Memory
Prof. Neeraj Bhargava
Kapil Chauhan
Department of Computer Science
School of Engineering & Systems Sciences
MDS University, Ajmer
Introduction
Cache memory is a not dynamic RAM its work on
static RAM.
Cache memory is a small size type of volatile
computer memory that provides high-speed data.
The basic purpose of cache memory is to store
program instruction that are frequently accessed by
software during operation.
Memory Hierarchy
Facts
Compact
Fast
Increase performance by having “hierarchy” of
memory subsystems
“Temporal Locality” and “Spatial Locality” are big
ideas
Memory Hierarchy
Terms
Cache Miss
Cache Hit
Hit Rate
Miss Rate
Index, Offset and Tag
Direct Mapped Cache
Advantage
Simple
Fast
Disadvantage
Mapping is fixed !!!
• Compulsory (cold start or process migration, first reference): first
access to a block
– “Cold” fact of life: not a whole lot you can do about it
– Note: If you are going to run “billions” of instruction,
Compulsory Misses are insignificant
• Capacity:
– Cache cannot contain all blocks access by the program
– Solution: increase cache size
• Conflict (collision):
– Multiple memory locations mapped
to the same cache location
– Solution 1: increase cache size
– Solution 2: increase associativity
• Coherence (Invalidation): other process (e.g., I/O) updates memory
Improving Cache Performance
Reduce Miss Rate
Associativity
Victim Cache
Compiler Optimizations
Reduce Miss Penalty
Faster DRAM
Write Buffers
Reduce Hit Time
Compiler Optimizations
Compiler Optimizations to reduce miss rate
Loop Fusion
Loop Interchange
Merge Arrays
Reduce Hit Time
Lower Associativity
Add L1 and L2 caches
L1 cache is small => Hit Time is critical
L2 cache has large => Miss Penalty is critical
PerformanceCPU time = (CPU execution clock cycles +
Memory stall clock cycles) x clock cycle time
Memory stall clock cycles =
(Reads x Read miss rate x Read miss penalty +
Writes x Write miss rate x Write miss penalty)
Memory stall clock cycles =
Memory accesses x Miss rate x Miss penalty
Different measure: AMAT
Average Memory Access time (AMAT) =
Hit Time + (Miss Rate x Miss Penalty)

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Cache memory

  • 1. Cache Memory Prof. Neeraj Bhargava Kapil Chauhan Department of Computer Science School of Engineering & Systems Sciences MDS University, Ajmer
  • 2. Introduction Cache memory is a not dynamic RAM its work on static RAM. Cache memory is a small size type of volatile computer memory that provides high-speed data. The basic purpose of cache memory is to store program instruction that are frequently accessed by software during operation.
  • 3. Memory Hierarchy Facts Compact Fast Increase performance by having “hierarchy” of memory subsystems “Temporal Locality” and “Spatial Locality” are big ideas
  • 4. Memory Hierarchy Terms Cache Miss Cache Hit Hit Rate Miss Rate Index, Offset and Tag
  • 6. • Compulsory (cold start or process migration, first reference): first access to a block – “Cold” fact of life: not a whole lot you can do about it – Note: If you are going to run “billions” of instruction, Compulsory Misses are insignificant • Capacity: – Cache cannot contain all blocks access by the program – Solution: increase cache size • Conflict (collision): – Multiple memory locations mapped to the same cache location – Solution 1: increase cache size – Solution 2: increase associativity • Coherence (Invalidation): other process (e.g., I/O) updates memory
  • 7. Improving Cache Performance Reduce Miss Rate Associativity Victim Cache Compiler Optimizations Reduce Miss Penalty Faster DRAM Write Buffers Reduce Hit Time
  • 8. Compiler Optimizations Compiler Optimizations to reduce miss rate Loop Fusion Loop Interchange Merge Arrays
  • 9. Reduce Hit Time Lower Associativity Add L1 and L2 caches L1 cache is small => Hit Time is critical L2 cache has large => Miss Penalty is critical
  • 10. PerformanceCPU time = (CPU execution clock cycles + Memory stall clock cycles) x clock cycle time Memory stall clock cycles = (Reads x Read miss rate x Read miss penalty + Writes x Write miss rate x Write miss penalty) Memory stall clock cycles = Memory accesses x Miss rate x Miss penalty Different measure: AMAT Average Memory Access time (AMAT) = Hit Time + (Miss Rate x Miss Penalty)