CAMP-V: Ultimate RISC-V Bootcamp sponsored by MERL and RISC-V
- 3. RISC-V Advocate Research Associate @ MERL CPU Design Engineer @ Intensivate CAMP-V
- 4. AGENDA Introductory Note 10:00 AM MERL Projects Showcase 12:30 PM Speed Programming 2:00 PM RISC-V Assembly Seminar 10:30 AM Lunch Break 1:00 PM Closing Note 4:00 PM CAMP-V CAMP-V
- 5. Research assistant @ MERL lfx mentee 2023 CAMP-V
- 7. Instruction Set Architecture (ISA) Defines how software controls hardware. Two types of ISAs. Complex Instruction Set Computer (CISC) Reduced Instruction Set Computer (RISC) CAMP-V
- 10. Complex Instruction Set Computer (CISC) Supports complex instructions taking multiple clock cycles. Supports variable-length instructions. Consists of a few registers. Example: x86 CAMP-V
- 11. Reduced Instruction Set Computer (RISC) Supports simple instructions taking a single clock cycle. Supports only fixed-length instructions. Register count is big. Example: ARM and RISC-V CAMP-V
- 12. CISC vs RISC CISC Reduced code size. Complex design. Slower execution. Greater power consumption. RISC Greater code size. Simpler design. Faster execution. Lower power consumption. CAMP-V
- 14. RISC-V CAMP-V
- 15. Background Pronounced “risk-five”. Developed in 2010 at University of California, Berkeley. Fifth iteration of the RISC architecture. Two variants: RV32 and RV64. Extension based ISA. RV32I as base extension. M extension for multiplication instructions. A extension for atomic instructions. F extension for single-precision floating-point instructions. D extension for double-precision floating-point instructions. These extensions are collectively known as RV32G. CAMP-V
- 16. RV32I Characteristics 32-bit general purpose integer registers named x0 through x31. ABI names are standardized names for registers. A RISC-V hart has byte-addressable address space. 32-bit register called a Program Counter (PC). CAMP-V
- 17. Register Conventions ABI name: zero Value of the register is always zero. x0 CAMP-V
- 18. Register Conventions ABI name: ra Stores the return address of a function call. x1 CAMP-V
- 19. Register Conventions ABI name: sp Stores the address pointing to the top of the stack in memory. x2 CAMP-V
- 20. Register Conventions ABI name: gp Stores the address pointing to the segment of memory holding global variables (aka the data section). gp x3 CAMP-V
- 21. Register Conventions ABI name: tp Stores the address pointing to the thread-local storage area of memory containing data unique to each thread. x4 CAMP-V
- 22. Register Conventions ABI names: t0-t2, t3-t6 Stores temporary data or data not to be preserved between function calls. x5-x7 x28-x31 CAMP-V
- 23. Register Conventions ABI names: s0/fp Stores the address pointing to the bottom of the current stack frame. x8 CAMP-V
- 24. Register Conventions ABI names: s1, s2-s11 Stores data that is to be preserved between function calls. x9 x18-x27 CAMP-V
- 25. Register Conventions ABI name: a0-a7 These store function argument values. a0-a1 registers also store the return values of functions. x10-x17 CAMP-V
- 26. Quizizz CAMP-V
- 28. Assembly Low-level programming language. Strong correspondence between assembly instructions and machine language. Direct communication with hardware. All compilers and interpreters compile or interpret to assembly. CAMP-V
- 29. RISC-V Assembly Types of instructions Computational register-register register-immediate Conditional Jumps Unconditional Jumps Memory operations Supplementary CAMP-V
- 30. Computational Instructions Register-register instructions Format: inst rd, rs1, rs2 Register-immediate instructions Format: inst rd, rs1, imm Arithmetic Comparison Logical Shifts Register-register add, sub slt, sltu and, or, xor sll, srl, sra Register-immediate addi slti, sltiu andi, ori, xori slli, srli, srai CAMP-V
- 31. Register-register instruction encoding Computational Instructions Register-immediate instruction encoding CAMP-V
- 32. Instruction beq bne blt bltu bge bgeu Operation == != < < >= >= Conditional Jumps or Branch Instructions If the condition is true, jump to the label. Format: inst rs1, rs2, label CAMP-V
- 33. Conditional Jumps or Branch Instructions Used in if and loop conditions. CAMP-V
- 34. Branch instruction encoding Conditional Jumps or Branch Instructions CAMP-V
- 35. Unconditional Jumps If this instruction is encountered, jump to the label or address. The address of the instruction following the jump instruction is saved to the destination register. jal: Jump and Link Jump target specified as label. Format: jal rd, label jalr: Jump and Link Register Jump target specified as sum of register value and constant offset. Format: jalr, rd, rs1, imm CAMP-V
- 36. Unconditional Jumps Used in function calls. jal is used to jump to function definition. jalr is used to return from the function call. CAMP-V
- 37. Unconditional Jumps jal instruction encoding jalr instruction encoding CAMP-V
- 38. Instructions for communicating with memory. Load instruction. Reads data from memory. Format: lw rd, imm(rs1) Store instruction. Writes data to memory. Format: sw rs2, imm(rs1) Memory Operation Instructions CAMP-V
- 39. Memory Operation Instructions Load instruction encoding Store instruction encoding CAMP-V
- 40. Supplementary Instructions To be used in conjunction with other instructions. lui: Load Upper-Immediate loads the 20-bit immediate into the upper 20 bits of rd. Used to build 32-bit constants. auipc: Add Upper-Immediate to PC loads the 20-bit immediate into the upper 20-bits, adding this offset to the PC. Used to build PC-relative addresses. Format: inst rd, imm CAMP-V
- 41. Supplementary Instructions Supplementary instruction encoding CAMP-V
- 42. Quizizz CAMP-V