![Complex Addressing Mode
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Load (X(R1)), R2](https://image.slidesharecdn.com/chapter6-pipelining-250422152740-25b9bccf/85/chapter6-Pipelining-ppt-chaptPipelining-42-320.jpg)
![Simple Addressing Mode
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Load (R2), R2](https://image.slidesharecdn.com/chapter6-pipelining-250422152740-25b9bccf/85/chapter6-Pipelining-ppt-chaptPipelining-43-320.jpg)
chapter6- Pipelining.ppt chaptPipelining
- 2. Overview Pipelining is widely used in modern processors. Pipelining improves system performance in terms of throughput. Pipelined organization requires sophisticated compilation techniques.
- 4. Making the Execution of Programs Faster Use faster circuit technology to build the processor and the main memory. Arrange the hardware so that more than one operation can be performed at the same time. In the latter way, the number of operations performed per second is increased even though the elapsed time needed to perform any one operation is not changed.
- 5. Traditional Pipeline Concept Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 40 minutes “Folder” takes 20 minutes A B C D
- 6. Traditional Pipeline Concept Sequential laundry takes 6 hours for 4 loads If they learned pipelining, how long would laundry take? A B C D 30 40 20 30 40 20 30 40 20 30 40 20 6 PM 7 8 9 10 11 Midnight Time
- 7. Traditional Pipeline Concept Pipelined laundry takes 3.5 hours for 4 loads A B C D 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time 30 40 40 40 40 20
- 8. Traditional Pipeline Concept Pipelining doesn’t help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously using different resources Potential speedup = Number pipe stages Unbalanced lengths of pipe stages reduces speedup Time to “fill” pipeline and time to “drain” it reduces speedup Stall for Dependences A B C D 6 PM 7 8 9 T a s k O r d e r Time 30 40 40 40 40 20
- 9. Use the Idea of Pipelining in a Computer F 1 E 1 F 2 E 2 F 3 E 3 I1 I2 I3 (a) Sequential execution Instruction fetch unit Execution unit Interstage buffer B1 (b) Hardware organization Time F1 E1 F2 E2 F3 E3 I1 I2 I3 Instruction (c) Pipelined execution Figure 8.1. Basic idea of instruction pipelining. Clock cycle 1 2 3 4 Time Fetch + Execution
- 10. Use the Idea of Pipelining in a Computer F4 I4 F1 F2 F3 I1 I2 I3 D1 D2 D3 D4 E1 E2 E3 E4 W1 W2 W3 W4 Instruction Figure 8.2. A 4-stage pipeline. Clock cycle 1 2 3 4 5 6 7 (a) Instruction execution divided into four steps F : Fetch instruction D : Decode instruction and fetch operands E: Execute operation W : Write results Interstage buffers (b) Hardware organization B1 B2 B3 Time Fetch + Decode + Execution + Write Textbook page: 457
- 11. Role of Cache Memory Each pipeline stage is expected to complete in one clock cycle. The clock period should be long enough to let the slowest pipeline stage to complete. Faster stages can only wait for the slowest one to complete. Since main memory is very slow compared to the execution, if each instruction needs to be fetched from main memory, pipeline is almost useless. Fortunately, we have cache.
- 12. Pipeline Performance The potential increase in performance resulting from pipelining is proportional to the number of pipeline stages. However, this increase would be achieved only if all pipeline stages require the same time to complete, and there is no interruption throughout program execution. Unfortunately, this is not true.
- 13. Pipeline Performance F1 F2 F3 I1 I2 I3 E1 E2 E3 D1 D2 D3 W1 W2 W3 Instruction F4 D4 I4 Clock c ycle 1 2 3 4 5 6 7 8 9 Figure 8.3. Effect of an execution operation taking more than one clock cycle. E4 F5 I5 D5 Time E5 W4
- 14. Pipeline Performance The previous pipeline is said to have been stalled for two clock cycles. Any condition that causes a pipeline to stall is called a hazard. Data hazard – any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline. So some operation has to be delayed, and the pipeline stalls. Instruction (control) hazard – a delay in the availability of an instruction causes the pipeline to stall. Structural hazard – the situation when two instructions require the use of a given hardware resource at the same time.
- 15. Pipeline Performance F1 F2 F3 I1 I2 I3 D1 D2 D3 E1 E2 E3 W1 W2 W3 Instruction Figure 8.4. Pipeline stall caused by a cache miss in F2. 1 2 3 4 5 6 7 8 9 Clock cycle (a) Instruction execution steps in successive clock cycles 1 2 3 4 5 6 7 8 Clock cycle Stage F: Fetch D: Decode E: Execute W: Write F1 F2 F3 D1 D2 D3 idle idle idle E1 E2 E3 idle idle idle W1 W2 idle idle idle (b) Function performed by each processor stage in successive clock cycles 9 W3 F2 F2 F2 Time Time Idle periods – stalls (bubbles) Instruction hazard
- 16. Pipeline Performance F1 F2 F3 I1 I2 (Load) I3 E1 M2 D1 D2 D3 W1 W2 Instruction F4 I4 Clock cycle 1 2 3 4 5 6 7 Figure 8.5. Effect of a Load instruction on pipeline timing. F5 I5 D5 Time E2 E3 W3 E4 D4 Load X(R1), R2 Structural hazard
- 17. Pipeline Performance Again, pipelining does not result in individual instructions being executed faster; rather, it is the throughput that increases. Throughput is measured by the rate at which instruction execution is completed. Pipeline stall causes degradation in pipeline performance. We need to identify all hazards that may cause the pipeline to stall and to find ways to minimize their impact.
- 18. Quiz Four instructions, the I2 takes two clock cycles for execution. Pls draw the figure for 4- stage pipeline, and figure out the total cycles needed for the four instructions to complete.
- 19. Data Hazards
- 20. Data Hazards We must ensure that the results obtained when instructions are executed in a pipelined processor are identical to those obtained when the same instructions are executed sequentially. Hazard occurs A ← 3 + A B ← 4 × A No hazard A ← 5 × C B ← 20 + C When two operations depend on each other, they must be executed sequentially in the correct order. Another example: Mul R2, R3, R4 Add R5, R4, R6
- 21. Data Hazards F1 F2 F3 I1 (Mul) I2 (Add) I3 D1 D3 E1 E3 E2 W3 Instruction Figure 8.6. Pipeline stalled by data dependency between D2 and W1. 1 2 3 4 5 6 7 8 9 Clock cycle W1 D2A W2 F4 D4 E4 W4 I4 D2 Time Figure 8.6. Pipeline stalled by data dependency between D2 and W1.
- 22. Operand Forwarding Instead of from the register file, the second instruction can get data directly from the output of ALU after the previous instruction is completed. A special arrangement needs to be made to “forward” the output of ALU to the input of ALU.
- 23. Register file SRC1 SRC2 RSLT Destination Source 1 Source 2 (a) Datapath ALU E: Execute (ALU) W: Write (Register file) SRC1,SRC2 RSLT (b) Position of the source and result registers in the processor pipeline Figure 8.7. Operand forwarding in a pipelined processor. Forwarding path
- 24. Handling Data Hazards in Software Let the compiler detect and handle the hazard: I1: Mul R2, R3, R4 NOP NOP I2: Add R5, R4, R6 The compiler can reorder the instructions to perform some useful work during the NOP slots.
- 25. Side Effects The previous example is explicit and easily detected. Sometimes an instruction changes the contents of a register other than the one named as the destination. When a location other than one explicitly named in an instruction as a destination operand is affected, the instruction is said to have a side effect. (Example?) Example: conditional code flags: Add R1, R3 AddWithCarry R2, R4 Instructions designed for execution on pipelined hardware should have few side effects.
- 27. Overview Whenever the stream of instructions supplied by the instruction fetch unit is interrupted, the pipeline stalls. Cache miss Branch
- 28. Unconditional Branches F2 I2 (Branch) I3 Ik E2 F3 Fk Ek Fk+1 Ek+1 Ik+1 Instruction Figure 8.8. An idle cycle caused by a branch instruction. Execution unit idle 1 2 3 4 5 Clock cycle Time F1 I1 E1 6 X
- 29. Branch Timing X Figure 8.9. Branch timing. F1 D1 E1 W1 I2 (Branch) I1 1 2 3 4 5 6 7 Clock cycle F2 D2 F3 X Fk Dk Ek Fk+1 Dk+1 I3 Ik Ik+1 Wk Ek+1 (b) Branch address computed in Decode stage F1 D1 E1 W1 I2 (Branch) I1 1 2 3 4 5 6 7 Clock cycle F2 D2 F3 Fk Dk Ek Fk+1 Dk+1 I3 Ik Ik+1 Wk Ek+1 (a) Branch address computed in Execute stage E2 D3 F4 X I4 8 Time Time - Branch penalty - Reducing the penalty
- 30. Instruction Queue and Prefetching F : Fetch instruction E : Execute instruction W : Write results D : Dispatch/ Decode Instruction queue Instruction fetch unit Figure 8.10. Use of an instruction queue in the hardware organization of Figure 8.2b. unit
- 31. Conditional Braches A conditional branch instruction introduces the added hazard caused by the dependency of the branch condition on the result of a preceding instruction. The decision to branch cannot be made until the execution of that instruction has been completed. Branch instructions represent about 20% of the dynamic instruction count of most programs.
- 32. Delayed Branch The instructions in the delay slots are always fetched. Therefore, we would like to arrange for them to be fully executed whether or not the branch is taken. The objective is to place useful instructions in these slots. The effectiveness of the delayed branch approach depends on how often it is possible to reorder instructions.
- 33. Delayed Branch Add LOOP Shift_left R1 Decrement Branch=0 R2 LOOP NEXT (a) Original program loop LOOP Decrement R2 Branch=0 Shift_left LOOP R1 NEXT (b) Reordered instructions Figure 8.12. Reordering of instructions for a delayed branch. Add R1,R3 R1,R3
- 34. Delayed Branch F E F E F E F E F E F E F E Instruction Decrement Branch Shift (delay slot) Figure 8.13. Execution timing showing the delay slot being filled during the last two passes through the loop in Figure 8.12. Decrement (Branch tak en) Branch Shift (delay slot) Add (Branch not taken) 1 2 3 4 5 6 7 8 Clock cycle Time
- 35. Branch Prediction To predict whether or not a particular branch will be taken. Simplest form: assume branch will not take place and continue to fetch instructions in sequential address order. Until the branch is evaluated, instruction execution along the predicted path must be done on a speculative basis. Speculative execution: instructions are executed before the processor is certain that they are in the correct execution sequence. Need to be careful so that no processor registers or memory locations are updated until it is confirmed that these instructions should indeed be executed.
- 36. Incorrectly Predicted Branch F1 F2 I1 (Compare) I2 (Branch>0) I3 D1 E1 W1 F3 F4 Fk Dk D3 X X I4 Ik Instruction Figure 8.14. Timing when a branch decision has been incorrectly predicted as not taken. E2 Clock cycle 1 2 3 4 5 6 D2/P2 Time
- 37. Branch Prediction Better performance can be achieved if we arrange for some branch instructions to be predicted as taken and others as not taken. Use hardware to observe whether the target address is lower or higher than that of the branch instruction. Let compiler include a branch prediction bit. So far the branch prediction decision is always the same every time a given instruction is executed – static branch prediction.
- 39. Overview Some instructions are much better suited to pipeline execution than others. Addressing modes Conditional code flags
- 40. Addressing Modes Addressing modes include simple ones and complex ones. In choosing the addressing modes to be implemented in a pipelined processor, we must consider the effect of each addressing mode on instruction flow in the pipeline: Side effects The extent to which complex addressing modes cause the pipeline to stall Whether a given mode is likely to be used by compilers
- 41. Recall F1 F2 F3 I1 I2 (Load) I3 E1 M2 D1 D2 D3 W1 W2 Instruction F4 I4 Clock cycle 1 2 3 4 5 6 7 Figure 8.5. Effect of a Load instruction on pipeline timing. F5 I5 D5 Time E2 E3 W3 E4 D4 Load X(R1), R2 Load (R1), R2
- 42. Complex Addressing Mode F F D D E X+[R1] [X+[R1]] [[X +[R1]]] Load Next instruction (a) Complex addressing mode W 1 2 3 4 5 6 7 Clock cycle Time W Forward Load (X(R1)), R2
- 43. Simple Addressing Mode X+ [R1] F D F F F D D D E [X +[R1]] [[X +[R1]]] Add Load Load Next instruction (b) Simple addressing mode W W W W Add #X, R1, R2 Load (R2), R2 Load (R2), R2
- 44. Addressing Modes In a pipelined processor, complex addressing modes do not necessarily lead to faster execution. Advantage: reducing the number of instructions / program space Disadvantage: cause pipeline to stall / more hardware to decode / not convenient for compiler to work with Conclusion: complex addressing modes are not suitable for pipelined execution.
- 45. Addressing Modes Good addressing modes should have: Access to an operand does not require more than one access to the memory Only load and store instruction access memory operands The addressing modes used do not have side effects Register, register indirect, index
- 46. Conditional Codes If an optimizing compiler attempts to reorder instruction to avoid stalling the pipeline when branches or data dependencies between successive instructions occur, it must ensure that reordering does not cause a change in the outcome of a computation. The dependency introduced by the condition- code flags reduces the flexibility available for the compiler to reorder instructions.
- 47. Conditional Codes Add Compare Branch=0 R1,R2 R3,R4 . . . Compare Add Branch=0 R3,R4 R1,R2 . . . (a) A program fragment (b) Instructions reordered Figure 8.17. Instruction reordering.
- 48. Conditional Codes Two conclusion: To provide flexibility in reordering instructions, the condition-code flags should be affected by as few instruction as possible. The compiler should be able to specify in which instructions of a program the condition codes are affected and in which they are not.
- 50. Original Design Memory bus data lines Figure 7.8. Three-bus organization of the datapath. Bus A Bus B Bus C Instruction decoder PC Register file Constant 4 ALU MDR A B R MUX Incrementer Address lines MAR IR
- 51. Instruction cache Figure 8.18. Datapath modified for pipelined execution, with Bus A Bus B Control signal pipeline IMAR PC Register file ALU Instruction A B R decoder Incrementer MDR/Write Instruction queue Bus C Data cache Memory address MDR/Read DMAR Memory address (Instruction fetches) (Data access) interstage buffers at the input and output of the ALU. Pipelined Design - Separate instruction and data caches - PC is connected to IMAR - DMAR - Separate MDR - Buffers for ALU - Instruction queue - Instruction decoder output - Reading an instruction from the instruction cache - Incrementing the PC - Decoding an instruction - Reading from or writing into the data cache - Reading the contents of up to two regs - Writing into one register in the reg file - Performing an ALU operation
- 53. Overview The maximum throughput of a pipelined processor is one instruction per clock cycle. If we equip the processor with multiple processing units to handle several instructions in parallel in each processing stage, several instructions start execution in the same clock cycle – multiple-issue. Processors are capable of achieving an instruction execution throughput of more than one instruction per cycle – superscalar processors. Multiple-issue requires a wider path to the cache and multiple execution units.
- 54. Superscalar W : Write results Dispatch unit Instruction queue Floating- point unit Integer unit Figure 8.19. A processor with two execution units. F : Instruction fetch unit
- 55. Timing I1 (Fadd) D1 D2 D3 D4 E1A E1B E1C E2 E3 E3 E3 E4 W1 W2 W3 W4 I2 (Add) I3 (Fsub) I4 (Sub) Figure 8.20. An example of instruction execution flow in the processor of Figure 8.19, assuming no hazards are encountered. 1 2 3 4 5 6 Clock cycle Time F1 F2 F3 F4 7
- 56. Out-of-Order Execution Hazards Exceptions Imprecise exceptions Precise exceptions I1 (Fadd) D1 D2 D3 D4 E1A E1B E1C E2 E3A E3B E3C E4 W1 W2 W3 W4 I2 (Add) I3 (Fsub) I4 (Sub) 1 2 3 4 5 6 Clock cycle Time (a) Delayed write F1 F2 F3 F4 7
- 57. Execution Completion It is desirable to used out-of-order execution, so that an execution unit is freed to execute other instructions as soon as possible. At the same time, instructions must be completed in program order to allow precise exceptions. The use of temporary registers Commitment unit I1 (Fadd) D1 D2 D3 D4 E1A E1B E1C E2 E3A E3B E3C E4 W1 W2 W3 W4 I2 (Add) I3 (Fsub) I4 (Sub) 1 2 3 4 5 6 Clock cycle Time (b) Using temporary registers TW2 TW4 7 F1 F2 F3 F4
- 59. Overview The execution time T of a program that has a dynamic instruction count N is given by: where S is the average number of clock cycles it takes to fetch and execute one instruction, and R is the clock rate. Instruction throughput is defined as the number of instructions executed per second. R S N T S R Ps
- 60. Overview An n-stage pipeline has the potential to increase the throughput by n times. However, the only real measure of performance is the total execution time of a program. Higher instruction throughput will not necessarily lead to higher performance. Two questions regarding pipelining How much of this potential increase in instruction throughput can be realized in practice? What is good value of n?
- 61. Number of Pipeline Stages Since an n-stage pipeline has the potential to increase the throughput by n times, how about we use a 10,000-stage pipeline? As the number of stages increase, the probability of the pipeline being stalled increases. The inherent delay in the basic operations increases. Hardware considerations (area, power, complexity, …)