Pipelining In computer
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Pipelining is a technique used in microprocessors that allows multiple instruction stages to execute concurrently, improving processing efficiency. It involves various elements like instruction fetch, decode, execution, memory I/O, and write-back within defined time frames, while facing potential hazards such as data, control, and structural conflicts. The advantages include better resource utilization and faster execution, but it also requires additional hardware and may suffer from speed disruptions due to pipeline hazards.
Pipelining In computer
- 1. Hafiz Hamza AshrafHafiz Hamza Ashraf hafizhamza313@gmail.comhafizhamza313@gmail.com
- 3. CharacterizeCharacterize PipelinesPipelines 1)1) Hardware or software implementation – pipelining can be implemented inHardware or software implementation – pipelining can be implemented in either software or hardware.either software or hardware. 2)2) Large or Small Scale – Stations in a pipeline can range from simplistic toLarge or Small Scale – Stations in a pipeline can range from simplistic to powerful, and a pipeline can range in length from short to long.powerful, and a pipeline can range in length from short to long. 3)3) Synchronous or asynchronous flow – A synchronous pipeline operatesSynchronous or asynchronous flow – A synchronous pipeline operates like an assembly line: at a given time, each station is processing somelike an assembly line: at a given time, each station is processing some amount of information. A asynchronous pipeline, allow a station toamount of information. A asynchronous pipeline, allow a station to forward information at any time.forward information at any time. 4)4) Buffered or unbuffered flow – One stage of pipeline sends data directly toBuffered or unbuffered flow – One stage of pipeline sends data directly to another one or a buffer is place between each pairs of stages.another one or a buffer is place between each pairs of stages. 5)5) Finite Chunks or Continuous Bit Streams – The digital information thatFinite Chunks or Continuous Bit Streams – The digital information that passes though a pipeline can consist of a sequence or small data itemspasses though a pipeline can consist of a sequence or small data items or an arbitrarily long bit stream.or an arbitrarily long bit stream. 6)6) Automatic Data Feed Or Manual Data Feed – Some implementations ofAutomatic Data Feed Or Manual Data Feed – Some implementations of pipelines use a separate mechanism to move information, and otherpipelines use a separate mechanism to move information, and other implementations require each stage to participate in moving information.implementations require each stage to participate in moving information.
- 4. What is PipeliningWhat is Pipelining A technique used in advanced microprocessors whereA technique used in advanced microprocessors where the microprocessor begins executing a secondthe microprocessor begins executing a second instruction before the first has been completed.instruction before the first has been completed. - A Pipeline is a series of stages, where some work isA Pipeline is a series of stages, where some work is done at each stage. The work is not finished until it hasdone at each stage. The work is not finished until it has passed through all stages.passed through all stages. With pipelining, the computer architecture allows theWith pipelining, the computer architecture allows the next instructions to be fetched while the processor isnext instructions to be fetched while the processor is performing arithmetic operations, holding them in aperforming arithmetic operations, holding them in a buffer close to the processor until each instructionbuffer close to the processor until each instruction operation can performed.operation can performed.
- 5. How Pipelines WorksHow Pipelines Works The pipeline is divided into segments andThe pipeline is divided into segments and each segment can execute it operationeach segment can execute it operation concurrently with the other segments.concurrently with the other segments. Once a segment completes an operations,Once a segment completes an operations, it passes the result to the next segment init passes the result to the next segment in the pipeline and fetches the nextthe pipeline and fetches the next operations from the preceding segment.operations from the preceding segment.
- 8. Instructions FetchInstructions Fetch The instruction Fetch (IF) stage is responsible forThe instruction Fetch (IF) stage is responsible for obtaining the requested instruction from memory. Theobtaining the requested instruction from memory. The instruction and the program counter (which isinstruction and the program counter (which is incremented to the next instruction) are stored in theincremented to the next instruction) are stored in the IF/ID pipeline register as temporary storage so that mayIF/ID pipeline register as temporary storage so that may be used in the next stage at the start of the next clockbe used in the next stage at the start of the next clock cycle.cycle.
- 9. Instruction DecodeInstruction Decode The Instruction Decode (ID) stage is responsible forThe Instruction Decode (ID) stage is responsible for decoding the instruction and sending out the variousdecoding the instruction and sending out the various control lines to the other parts of the processor. Thecontrol lines to the other parts of the processor. The instruction is sent to the control unit where it is decodedinstruction is sent to the control unit where it is decoded and the registers are fetched from the register file.and the registers are fetched from the register file.
- 10. ExecutionExecution The Execution (EX) stage is where any calculations areThe Execution (EX) stage is where any calculations are performed. The main component in this stage is theperformed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic andALU. The ALU is made up of arithmetic, logic and capabilities.capabilities.
- 11. Memory and IOMemory and IO The Memory and IO (MEM) stage is responsible forThe Memory and IO (MEM) stage is responsible for storing and loading values to and from memory. It alsostoring and loading values to and from memory. It also responsible for input or output from the processor. If theresponsible for input or output from the processor. If the current instruction is not of Memory or IO type than thecurrent instruction is not of Memory or IO type than the result from the ALU is passed through to the write backresult from the ALU is passed through to the write back stage.stage.
- 12. Write BackWrite Back The Write Back (WB) stage is responsibleThe Write Back (WB) stage is responsible for writing the result of a calculation,for writing the result of a calculation, memory access or input into the registermemory access or input into the register file.file.
- 13. Operation TimingsOperation Timings Estimated timings for each ofEstimated timings for each of the stages:the stages: InstructionInstruction FetchFetch 2ns2ns InstructionInstruction DecodeDecode 1ns1ns ExecutionExecution 2ns2ns MemoryMemory and IOand IO 2ns2ns Write BackWrite Back 1ns1ns
- 14. Advantages/DisadvantagesAdvantages/Disadvantages Advantages:Advantages: More efficient use of processorMore efficient use of processor Quicker time of execution of large number ofQuicker time of execution of large number of instructionsinstructions Disadvantages:Disadvantages: Pipelining involves adding hardware to the chipPipelining involves adding hardware to the chip Inability to continuously run the pipelineInability to continuously run the pipeline at full speed because of pipeline hazardsat full speed because of pipeline hazards which disrupt the smooth execution of thewhich disrupt the smooth execution of the pipeline.pipeline.
- 15. Pipeline HazardsPipeline Hazards Data Hazards – an instruction uses the result of theData Hazards – an instruction uses the result of the previous instruction. A hazard occurs exactly when anprevious instruction. A hazard occurs exactly when an instruction tries to read a register in its ID stage that aninstruction tries to read a register in its ID stage that an earlier instruction intends to write in its WB stage.earlier instruction intends to write in its WB stage. Control Hazards – the location of an instruction dependsControl Hazards – the location of an instruction depends on previous instructionon previous instruction Structural Hazards – two instructions need to access theStructural Hazards – two instructions need to access the same resourcesame resource
- 17. StallingStalling Stalling involves halting the flow of instructions until theStalling involves halting the flow of instructions until the required result is ready to be used. However stallingrequired result is ready to be used. However stalling wastes processor time by doing nothing while waitingwastes processor time by doing nothing while waiting for the result.for the result.
- 19. Type of PipeliningType of Pipelining Software PipeliningSoftware Pipelining 1) Can Handle Complex Instructions1) Can Handle Complex Instructions 2) Allows programs to be reused2) Allows programs to be reused Hardware PipeliningHardware Pipelining 1) Help designer manage complexity – a1) Help designer manage complexity – a complex task can be divided into smaller,complex task can be divided into smaller, more manageable pieces.more manageable pieces. 2) Hardware pipelining offers higher2) Hardware pipelining offers higher performanceperformance
- 20. Type of Hardware PipelinesType of Hardware Pipelines Instruction Pipeline -Instruction Pipeline - AnAn instruction pipelineinstruction pipeline is veryis very similar to a manufacturing assembly line.similar to a manufacturing assembly line. 1st stage receives some parts, performs its assembly task,1st stage receives some parts, performs its assembly task, and passes the results to the second stage;and passes the results to the second stage; 2nd stage takes the partially assembled product from the2nd stage takes the partially assembled product from the first stage, performs its task, and passes its work to thefirst stage, performs its task, and passes its work to the third stage;third stage; 3rd stage does its work, passing the results to the last3rd stage does its work, passing the results to the last stage, which completes the task and outputs its results.stage, which completes the task and outputs its results. Data Pipeline – data pipeline is designed to pass dataData Pipeline – data pipeline is designed to pass data from stage to stage.from stage to stage.
- 21. Instruction Pipelines ConflictInstruction Pipelines Conflict It divided into two categories.It divided into two categories. Data ConflictsData Conflicts Branch ConflictsBranch Conflicts When the current instruction changes a register that theWhen the current instruction changes a register that the next one needed, data conflicts happens.next one needed, data conflicts happens. When the current instruction make a jump, branchWhen the current instruction make a jump, branch conflicts happens.conflicts happens.
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