pipeline in computer architecture design
- 1. Samrat Ashok Technical Institute Class : Iot 3rd sem.. Subject : Computer system organisation
- 2. PITCH DECK SAGAR PANDEY P R AV ESH ARYA YASHWANT SINGH VANSH CHOU R ASIYA ANANT SONI
- 3. Pipeline in a System Welcome to our presentation on pipelines in a system. In this session, we will explore the definition, components, benefits, challenges, and best practices of implementing pipelines Parallel Processing, Pipelining-Arithmetic Pipeline, Instruction Pipeline .
- 4. What is Pipeline : Pipelining is the process of accumulating instruction from the processor through a pipeline. It allows storing and executing instructions in an orderly process. It is also known as pipeline processing. Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and these stages are connected with one another to form a pipe like structure. Instructions enter from one end and exit from another end. Pipelining increases the overall instruction throughput.
- 5. Access memory Decode and read register Fetch instruction Write result Execute IF ( Instruction fetch) Stage 1 ID ( Instruction decode) Stage 2 EX (Execute) Stage 3 MEM (Memory) Stage 4 WB ( Write - back) Stage 5 Input Simple Processor Pipeline
- 6. • In this stage, the processor fetches the next instruction from memory. • The program counter (PC) is used to determine the address of the instruction to be fetched. • The fetched instruction is then placed in a temporary storage called the instruction register (IR). • In this stage, the fetched instruction is decoded to determine the operation it represents and the operands involved. • It involves identifying the instruction type, decoding registers, and determining the control signals. • The instruction's operation is executed in this stage. • For arithmetic instructions, this stage performs calculations. • For branch instructions, it evaluates conditions to determine the next instruction's address. • For memory access instructions, it calculates memory addresses and accesses data. Decode (ID - Instruction Decode) : Execute (EX - Execution) : Fetch (IF - Instruction Fetch) :
- 7. Memory (MEM - Memory Access) : • In this stage, memory operations are performed, if required. • It includes reading from or writing to memory, typically used for load and store operations. • The results of the instruction's execution are written back to the appropriate registers in this stage. • For example, the result of an arithmetic operation is stored in the destination register. These are the fundamental stages in a basic pipeline. Write-back (WB - Write Back):
- 8. Type Of Pipeline 1. Arithmetic Pipeline Arithmetic pipelines are usually found in most of the computers. They are used for floating point operations, multiplication of fixed point numbers etc. For example: The input to the Floating Point Adder pipeline is: A = X * 2x = 0.9504 * 103 B = Y * 2y = 0.8200 * 102 Where x and y refer to the exponents and X and Y refer to two fractions representing the mantissa. The floating-point addition and subtraction process is broken into four pieces. The matching sub-operation to be executed in the specified pipeline is contained in each segment. The four segments depict the following sub-operations: 1. Comparing the exponents using subtraction 2. Aligning the mantissa 3. Adding or subtracting the mantissa 4. Normalizing the result Later in this section, we’ll go through each sub-operation in greater depth. The sub-operations conducted in each pipeline section are depicted
- 9. 1. Comparing Exponents by Subtraction The difference between the exponents is calculated by subtracting them. The result’s exponent is chosen to be the larger exponent. The exponent difference, 3 – 2 = 1, defines the total number of times the mantissa associated with the lesser exponent should be shifted to the right. 2. Aligning the Mantissa As per the difference of exponents calculated in segment one, the mantissa corresponding with the smaller exponent would be moved. A = 0.9504 * 103 B = 0.08200 * 103 3. Adding the Mantissa Both the mantissa would be added in the third segment. C = A + B = 1.0324 * 103 4. Normalizing the Result After the process of normalization, the result would be written as follows: C = 0.1324 * 104
- 10. 2. Instruction Pipeline In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an instruction cycle. This type of technique is used to increase the throughput of the computer system. Pipeline processing can happen not only in the data stream but also in the instruction stream. To perform tasks such as fetching, decoding and execution of instructions, most digital computers with complicated instructions would require an instruction pipeline. In general, each and every instruction must be processed by the computer in the following order: 1. Fetching the instruction from memory 2. Decoding the obtained instruction 3. Calculating the effective address 4. Fetching the operands from the given memory 5. Execution of the instruction 6. Storing the result in a proper place
- 11. A four-segment instruction pipeline is illustrated in the block diagram given above. The instructional cycle is divided into four parts: Segment 1 The implementation of the instruction fetch segment can be done using the FIFO or first-in, first-out buffer. Segment 2 In the second segment, the memory instruction is decoded, and the effective address is then determined in a separate arithmetic circuit. Segment 3 In the third segment, some operands would be fetched from memory. Segment 4 The instructions would finally be executed in the very last segment of a pipeline organisation.
- 12. Disadvantages Of Pipeline Resource Conflicts: Pipelines can suffer from resource conflicts, where multiple stages need the same hardware simultaneously, leading to pipeline stalls and reduced efficiency. Branch Prediction: Handling branch instructions can be challenging in a pipeline, as predicting the outcome of a branch correctly is not always possible, resulting in wasted clock cycles. Data Hazards: Data dependencies between instructions can cause hazards, requiring complex forwarding and stall mechanisms to resolve, impacting pipeline throughput. Costly Pipeline Stalls: When an instruction encounters an issue like a cache miss or a long-latency operation, it can cause pipeline stalls, reducing overall performance. Instruction Mix Sensitivity: Pipelines may be sensitive to the mix of instructions in a program, with some types of code (e.g., heavily branching) performing less efficiently in a pipeline. Increased Complexity: Pipelined architectures are more complex to design and implement than non-pipelined architectures, which can increase manufacturing costs. Energy Efficiency: In some cases, pipelined processors may consume more power compared to simpler designs, affecting energy efficiency. Limited Gains for Simple Tasks: For very simple or short tasks, the overhead of pipelining may outweigh the performance benefits, making it less efficient. Synchronization Overhead: Handling multiple stages and ensuring correct instruction execution order can introduce synchronization overhead, potentially slowing down the processor. Programming Challenges: Writing software that fully utilizes the pipeline's capabilities and avoids hazards can be complex, making programming for pipelined architectures more challenging. These disadvantages highlight the trade-offs and challenges associated with pipelining in computer architecture. While pipelines can significantly improve processor performance for certain workloads, they also introduce complexities that need to be managed.
- 13. AdvantagesOf Pipeline Improved Throughput: Pipelining allows multiple instructions to be processed simultaneously, increasing the overall throughput of the processor. Faster Execution: Instructions can overlap, reducing the time it takes to complete a single instruction. Resource Utilization: Different stages of the pipeline can be used by different instructions at the same time, maximizing resource utilization. Reduced CPU Idle Time: It minimizes CPU idle time by keeping the pipeline busy, which improves overall performance. Simplifies Control: The control logic is simplified as each stage has a specific function, making it easier to design and manage. Scalability: Pipelining can be scaled by adding more stages or increasing the depth to accommodate more complex processors. Lower Clock Speed: It allows for lower clock speeds per pipeline stage, which can reduce power consumption and heat generation. Parallel Processing: Pipelines can be used for parallel processing, where multiple tasks are executed concurrently, improving system efficiency. Instruction Mix: It can handle a mix of instruction types, including arithmetic, logic, and memory operations, efficiently. Overall Performance Boost: The combination of these advantages results in an overall performance boost for the processor. Keep in mind that while pipelining offers numerous advantages, it also introduces challenges like pipeline hazards, which need to be managed for optimal performance.
- 14. Examples of Successful Pipeline Implementations Company A Reduced deployment time by 70% using an automated CI/CD pipeline. Company B Achieved 50% reduction in bugs with a well-designed testing pipeline. Company C Improved efficiency by 40% by implementing a streamlined build and deployment pipeline.
- 15. Conclusion In conclusion, pipelines in computer architecture offer several advantages, such as increased instruction throughput and improved performance for certain workloads. However, they also come with notable disadvantages and challenges, including resource conflicts, data hazards, and increased complexity. Whether a pipeline is beneficial depends on the specific application and design considerations. Properly managing hazards, branch prediction, and synchronization is crucial to maximize the benefits of pipelining. Overall, pipelines are a powerful tool in modern processors but require careful design and optimization to achieve their full potential.
- 16. Thank You! Any Doubt & Query BAD BOY